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| author | Thierry Reding <treding@nvidia.com> | 2015-08-20 11:52:14 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-10-15 14:46:43 +0200 |
| commit | ad3d6e88a1a4e6aacc55b39c2bad1528100784c0 (patch) | |
| tree | 0e6da861d32909eb34dce4f2c20d30d803d0f2ea /arch/arm/cpu | |
| parent | 55aa0bed9803b8a5bd3e462fd712741c2e1cff1b (diff) | |
| download | u-boot-imx-ad3d6e88a1a4e6aacc55b39c2bad1528100784c0.zip u-boot-imx-ad3d6e88a1a4e6aacc55b39c2bad1528100784c0.tar.gz u-boot-imx-ad3d6e88a1a4e6aacc55b39c2bad1528100784c0.tar.bz2 | |
armv8/mmu: Set bits marked RES1 in TCR
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/cache_v8.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 6bde1cf..b1ea822 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -59,15 +59,15 @@ static void mmu_setup(void) el = current_el(); if (el == 1) { set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL1_IPS_BITS, + TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS, MEMORY_ATTRIBUTES); } else if (el == 2) { set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL2_IPS_BITS, + TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS, MEMORY_ATTRIBUTES); } else { set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - TCR_FLAGS | TCR_EL3_IPS_BITS, + TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS, MEMORY_ATTRIBUTES); } /* enable the mmu */ |