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| author | Stephen Warren <swarren@nvidia.com> | 2014-07-02 14:12:30 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-08-18 16:57:03 -0700 |
| commit | aeb3fcb35956461077804720b8a252d50758d7e0 (patch) | |
| tree | b49a5e34ee8c34f2c08fd9cb63380bb3dd516217 /arch/arm/cpu | |
| parent | 39446bcefafa178e4072bd28c4f8325835d473d2 (diff) | |
| download | u-boot-imx-aeb3fcb35956461077804720b8a252d50758d7e0.zip u-boot-imx-aeb3fcb35956461077804720b8a252d50758d7e0.tar.gz u-boot-imx-aeb3fcb35956461077804720b8a252d50758d7e0.tar.bz2 | |
ARM: tegra: Use mem size from MC rather than ODMDATA
In at least Tegra124, the Tegra memory controller (MC) has a register
that controls the memory size. Read this to determine the memory size
rather than requiring this to be redundantly encoded into the ODMDATA.
This way, changes to the BCT (i.e. MC configuration) automatically
updated SW's view of the memory size, without requiring manual changes
to the ODMDATA.
Future work potentially required:
* Clip the memory size to architectural limits; U-Boot probably doesn't
and won't support either LPAE or Tegra's "swiss cheese" memory layout,
at least one of which would be required for >2GB RAM.
* Subtract out any carveout required by firmware on future SoCs.
Based-on-work-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/tegra-common/board.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c index 6a6faf4..433da09 100644 --- a/arch/arm/cpu/tegra-common/board.c +++ b/arch/arm/cpu/tegra-common/board.c @@ -27,11 +27,12 @@ enum { UART_COUNT = 5, }; +#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ + defined(CONFIG_TEGRA114) /* * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0, * so we are using this value to identify memory size. */ - unsigned int query_sdram_size(void) { struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; @@ -72,6 +73,21 @@ unsigned int query_sdram_size(void) } #endif } +#else +#include <asm/arch/mc.h> + +/* Read the RAM size directly from the memory controller */ +unsigned int query_sdram_size(void) +{ + struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE; + u32 size_mb; + + size_mb = readl(&mc->mc_emem_cfg); + debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb); + + return size_mb * 1024 * 1024; +} +#endif int dram_init(void) { |