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| author | Keerthy <j-keerthy@ti.com> | 2014-05-15 11:08:39 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-05-23 19:40:04 -0400 |
| commit | 8b0d1bbc7e181945d84db667d63081a96ea40a47 (patch) | |
| tree | 8067aa76eaf7262607f61387f3c11b257998c03d /arch/arm/cpu | |
| parent | ee77a2389b47d5ad15e0963e813c764ddc73b745 (diff) | |
| download | u-boot-imx-8b0d1bbc7e181945d84db667d63081a96ea40a47.zip u-boot-imx-8b0d1bbc7e181945d84db667d63081a96ea40a47.tar.gz u-boot-imx-8b0d1bbc7e181945d84db667d63081a96ea40a47.tar.bz2 | |
ARM: DRA72x: volt: Update the pmic offsets
TPS65917 is used in DRA722 evm. Update the address offsets accordingly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ad97132..802b155 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -372,6 +372,38 @@ struct vcores_data dra752_volts = { .iva.pmic = &tps659038, }; +struct vcores_data dra722_volts = { + .mpu.value = 1000, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = 0x23, + .mpu.pmic = &tps659038, + + .eve.value = 1000, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = 0x2f, + .eve.pmic = &tps659038, + + .gpu.value = 1000, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = 0x2f, + .gpu.pmic = &tps659038, + + .core.value = 1000, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = 0x27, + .core.pmic = &tps659038, + + .iva.value = 1000, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = 0x2f, + .iva.pmic = &tps659038, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed |