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| author | SRICHARAN R <r.sricharan@ti.com> | 2013-02-12 01:33:41 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-11 11:06:10 -0400 |
| commit | eed7c0f727cf8255b193dfefd21d66dfd6dbae94 (patch) | |
| tree | 7f3e0cb7742beaf5a49d7e3c6e7ff81d6aa895c0 /arch/arm/cpu | |
| parent | ef1697e99f482b0e6a64df465ffff77251719abb (diff) | |
| download | u-boot-imx-eed7c0f727cf8255b193dfefd21d66dfd6dbae94.zip u-boot-imx-eed7c0f727cf8255b193dfefd21d66dfd6dbae94.tar.gz u-boot-imx-eed7c0f727cf8255b193dfefd21d66dfd6dbae94.tar.bz2 | |
ARM: OMAP5: Add silicon id support for ES2.0 revision.
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hwinit.c | 27 |
1 files changed, 16 insertions, 11 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index dfc0e44..8e66a96 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -204,17 +204,22 @@ void init_omap_revision(void) */ unsigned int rev = cortex_rev(); - switch (rev) { - case MIDR_CORTEX_A15_R0P0: - switch (readl(CONTROL_ID_CODE)) { - case OMAP5430_CONTROL_ID_CODE_ES1_0: - *omap_si_rev = OMAP5430_ES1_0; - break; - case OMAP5432_CONTROL_ID_CODE_ES1_0: - default: - *omap_si_rev = OMAP5432_ES1_0; - break; - } + switch (readl(CONTROL_ID_CODE)) { + case OMAP5430_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5430_ES1_0; + if (rev == MIDR_CORTEX_A15_R2P2) + *omap_si_rev = OMAP5430_ES2_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5432_ES1_0; + if (rev == MIDR_CORTEX_A15_R2P2) + *omap_si_rev = OMAP5432_ES2_0; + break; + case OMAP5430_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5430_ES2_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5432_ES2_0; break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; |