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| author | Hao Zhang <hzhang@ti.com> | 2014-10-22 16:32:32 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-10-23 11:27:05 -0400 |
| commit | b66604fb66c3e8fee5d294ac548d6da52fd1fae1 (patch) | |
| tree | 5f46eae2a3a3051134a8932dbe7dc7a2757940b8 /arch/arm/cpu | |
| parent | 5ec66b140afff89c3ee5abde4a9eb4c0963c918c (diff) | |
| download | u-boot-imx-b66604fb66c3e8fee5d294ac548d6da52fd1fae1.zip u-boot-imx-b66604fb66c3e8fee5d294ac548d6da52fd1fae1.tar.gz u-boot-imx-b66604fb66c3e8fee5d294ac548d6da52fd1fae1.tar.bz2 | |
keystone2: enable OSR clock domain for K2L SoC
This patches enables the On-chip Shared Ram clock domain for K2L SoC.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/keystone/init.c | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index 62081b7..c2b9478 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -13,6 +13,7 @@ #include <asm/arch/msmc.h> #include <asm/arch/clock.h> #include <asm/arch/hardware.h> +#include <asm/arch/psc_defs.h> void chip_configuration_unlock(void) { @@ -20,6 +21,53 @@ void chip_configuration_unlock(void) __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); } +#ifdef CONFIG_SOC_K2L +void osr_init(void) +{ + u32 i; + u32 j; + u32 val; + u32 base = KS2_OSR_CFG_BASE; + u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS]; + + /* Enable the OSR clock domain */ + psc_enable_module(KS2_LPSC_OSR); + + /* Disable OSR ECC check for all the ram banks */ + for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) { + val = i | KS2_OSR_ECC_VEC_TRIG_RD | + (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH); + + writel(val , base + KS2_OSR_ECC_VEC); + + /** + * wait till read is done. + * Print should be added after earlyprintk support is added. + */ + for (j = 0; j < 10000; j++) { + val = readl(base + KS2_OSR_ECC_VEC); + if (val & KS2_OSR_ECC_VEC_RD_DONE) + break; + } + + ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^ + KS2_OSR_ECC_CTRL_CHK; + + writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4); + writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL); + } + + /* Reset OSR memory to all zeros */ + for (i = 0; i < KS2_OSR_SIZE; i += 4) + writel(0, KS2_OSR_DATA_BASE + i); + + /* Enable OSR ECC check for all the ram banks */ + for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) + writel(ecc_ctrl[i] | + KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL); +} +#endif + int arch_cpu_init(void) { chip_configuration_unlock(); @@ -32,6 +80,9 @@ int arch_cpu_init(void) #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1); #endif +#ifdef CONFIG_SOC_K2L + osr_init(); +#endif /* * just initialise the COM2 port so that TI specific |