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| author | Christian Riesch <christian.riesch@omicron.at> | 2012-02-02 00:44:39 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-12 10:11:33 +0100 |
| commit | b67d8816fd62f0a379caa16846381b5a4e4de398 (patch) | |
| tree | 26c11e8d3187e2081290feb7d9fa6955aafb1973 /arch/arm/cpu | |
| parent | da104e04ecc30b90fdc121737f220f0d9c252196 (diff) | |
| download | u-boot-imx-b67d8816fd62f0a379caa16846381b5a4e4de398.zip u-boot-imx-b67d8816fd62f0a379caa16846381b5a4e4de398.tar.gz u-boot-imx-b67d8816fd62f0a379caa16846381b5a4e4de398.tar.bz2 | |
arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
The V bit of the c1 register of CP15 should not be cleared on DA850
SoCs since they have no valid memory at 0x00000000. This patch
introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
that allows setting the correct value for the V bit.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Reported-by: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/start.S | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index b39ed8a..525c112 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -372,8 +372,13 @@ flush_dcache: * disable MMU and D cache, and enable I cache */ mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ +#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH + orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ +#else + bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ +#endif orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 |