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authorYe.Li <B37916@freescale.com>2014-06-11 15:49:22 +0800
committerYe.Li <B37916@freescale.com>2014-06-17 11:13:57 +0800
commit98c15deb3083d5dac7900c58e95f2ac2f422a4d3 (patch)
tree04384a22760755a17a5757f11b46dcbbe9934447 /arch/arm/cpu
parentfd00c322d058e02953a336517547174edaf2c573 (diff)
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ENGR00315894-57 iMX6SX: Add M4 boot support at soc level
Implement the override function "arch_auxiliary_core_up" to boot Cortex-M4 by executing command "bootaux". The parameter "boot_private_data" points to fields where stores the stack address and PC address for M4 to run. Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index b31ad04..3b8f613 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -516,6 +516,31 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
}
#endif
+#ifdef CONFIG_MX6SX
+int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
+{
+ struct src *src_reg;
+ u32 stack, pc;
+
+ if (!boot_private_data)
+ return 1;
+
+ stack = *(u32 *)boot_private_data;
+ pc = *(u32 *)(boot_private_data + 4);
+
+ /* Set the stack and pc to M4 bootROM */
+ writel(stack, M4_BOOTROM_BASE_ADDR);
+ writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+
+ /* Enable M4 */
+ src_reg = (struct src *)SRC_BASE_ADDR;
+ setbits_le32(&src_reg->scr, 0x00400000);
+ clrbits_le32(&src_reg->scr, 0x00000010);
+
+ return 0;
+}
+#endif
+
void boot_mode_apply(unsigned cfg_val)
{
unsigned reg;