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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-03-27 20:24:42 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-05-10 08:25:55 -0400 |
| commit | 166e5cc6278881f2951e7c06a122ecb080dc8968 (patch) | |
| tree | 4df87ca079c9eaae1600430eafde995d2b087476 /arch/arm/cpu | |
| parent | 8ce4e5f9329183a162775946558092166cb7cab3 (diff) | |
| download | u-boot-imx-166e5cc6278881f2951e7c06a122ecb080dc8968.zip u-boot-imx-166e5cc6278881f2951e7c06a122ecb080dc8968.tar.gz u-boot-imx-166e5cc6278881f2951e7c06a122ecb080dc8968.tar.bz2 | |
arm: omap: emif: Fix DDR3 init after warm reset
EMIF supports a global warm reset mode, during which the
EMIF keeps the SDRAM content. But if leveling is enabled
at the time of warm reset for DDR3, the following steps
needs to be done after warm reset:
1) Keep EMIF in self refresh mode.
2) Reset PHY to bring back the PHY to a known state.
3) Start Levelling procedure.
Doing the same.
And also enabling DLL lock and code output after warm reset.
Tested on OMAP5432 ES2.0
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/emif-common.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index cdb4439..11e830a 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1075,6 +1075,11 @@ static void do_sdram_init(u32 base) else ddr3_init(base, regs); } + if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { + set_lpmode_selfrefresh(base); + emif_reset_phy(base); + ddr3_leveling(base, regs); + } /* Write to the shadow registers */ emif_update_timings(base, regs); @@ -1262,10 +1267,10 @@ void sdram_init(void) in_sdram = running_from_sdram(); debug("in_sdram = %d\n", in_sdram); - if (!(in_sdram || warm_reset())) { - if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) + if (!in_sdram) { + if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset()) bypass_dpll((*prcm)->cm_clkmode_dpll_core); - else + else if (sdram_type == EMIF_SDRAM_TYPE_DDR3) writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); } |