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| author | Nitin Garg <nitin.garg@freescale.com> | 2014-04-02 08:55:01 -0500 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-04-07 18:11:00 +0200 |
| commit | f71cbfe3ca5d2ad20159871700e8e248c8818ba8 (patch) | |
| tree | 8f514793e71ebf0eaf91fe66147ce4fd8ac8cc4c /arch/arm/cpu | |
| parent | 1a9df13d5bc0b68c9dcae88d244c995c9351db67 (diff) | |
| download | u-boot-imx-f71cbfe3ca5d2ad20159871700e8e248c8818ba8.zip u-boot-imx-f71cbfe3ca5d2ad20159871700e8e248c8818ba8.tar.gz u-boot-imx-f71cbfe3ca5d2ad20159871700e8e248c8818ba8.tar.bz2 | |
ARM: Add workaround for Cortex-A9 errata 794072
A short loop including a DMB instruction might cause a denial of
service on another processor which executes a CP15 broadcast operation.
Exists on r1, r2, r3, r4 revisions.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index ac1e55a..f3830c8 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c1, c0, 0 @ write system control register #endif -#ifdef CONFIG_ARM_ERRATA_742230 +#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register |