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authorYe.Li <B37916@freescale.com>2014-06-12 19:34:18 +0800
committerYe.Li <B37916@freescale.com>2014-06-17 11:14:07 +0800
commit96d990ef754a879f6ca9da4adf6e0be3d21cdc51 (patch)
treeaac521e9294235ecf35473cb35ee55b585c0d693 /arch/arm/cpu
parent721c7a1448c5b7265b597b83d18f8338a27ea213 (diff)
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ENGR00315894-77 mx6 soc: Add vadc power up/down function
Add vadc power up/down function. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c46
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 3b8f613..5ef54ae 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -378,6 +378,52 @@ static void clear_mmdc_ch_mask(void)
writel(0, &mxc_ccm->ccdr);
}
+#ifdef CONFIG_MX6SX
+void vadc_power_up(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_GPR_BASE_ADDR;
+ u32 val;
+
+ /* csi0 */
+ val = readl(&iomux->gpr[5]);
+ val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
+ val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD;
+ writel(val, &iomux->gpr[5]);
+
+ /* Power on vadc analog
+ * Power down vadc ext power */
+ val = readl(GPC_BASE_ADDR + 0);
+ val &= ~0x60000;
+ writel(val, GPC_BASE_ADDR + 0);
+
+ /* software reset afe */
+ val = readl(&iomux->gpr[1]);
+ writel(val | 0x80000, &iomux->gpr[1]);
+
+ udelay(10*1000);
+
+ /* Release reset bit */
+ writel(val & ~0x80000, &iomux->gpr[1]);
+
+ /* Power on vadc ext power */
+ val = readl(GPC_BASE_ADDR + 0);
+ val |= 0x40000;
+ writel(val, GPC_BASE_ADDR + 0);
+}
+
+void vadc_power_down(void)
+{
+ u32 val;
+
+ /* Power down vadc ext power
+ * Power off vadc analog */
+ val = readl(GPC_BASE_ADDR + 0);
+ val &= ~0x40000;
+ val |= 0x20000;
+ writel(val, GPC_BASE_ADDR + 0);
+}
+#endif
+
static void imx_set_vddpu_power_down(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;