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| author | Anson Huang <b20788@freescale.com> | 2014-09-09 14:43:51 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2014-09-18 13:30:52 +0800 |
| commit | 8b903f529370fdc59cc03b3ced954ed894753044 (patch) | |
| tree | cb87171c5b0292fd946f1f9a3253ec1939e3d5b0 /arch/arm/cpu | |
| parent | 031d633aea8a33125f4b9874eb3119e462a8cff4 (diff) | |
| download | u-boot-imx-8b903f529370fdc59cc03b3ced954ed894753044.zip u-boot-imx-8b903f529370fdc59cc03b3ced954ed894753044.tar.gz u-boot-imx-8b903f529370fdc59cc03b3ced954ed894753044.tar.bz2 | |
ENGR00331269 arm: mx6: select OSC as uart's clk parent
As M4 is sourcing UART clk from OSC, to make UART work
when M4 is enabled, need to select OSC as clk parent,
24M OSC is enough for debug UART in uboot.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index f1d2cea..aab2582 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -553,6 +553,15 @@ int arch_cpu_init(void) set_preclk_from_osc(); #endif +#ifdef CONFIG_MX6SX + u32 reg; + + /* set uart clk to OSC */ + reg = readl(CCM_BASE_ADDR + 0x24); + reg |= 0x40; + writel(reg, CCM_BASE_ADDR + 0x24); +#endif + imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ #ifndef CONFIG_MX6SL |