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| author | Roger Quadros <rogerq@ti.com> | 2013-11-11 16:56:40 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-04 08:12:09 -0500 |
| commit | 8ffcf74bb057d049c379b2bdc126871c81215ec3 (patch) | |
| tree | 8b8c4279e5a7cdc1c55b31eab38af10e9dd682b9 /arch/arm/cpu | |
| parent | 9c4b64fb612e3129823ba83691e08f4c6d2042ea (diff) | |
| download | u-boot-imx-8ffcf74bb057d049c379b2bdc126871c81215ec3.zip u-boot-imx-8ffcf74bb057d049c379b2bdc126871c81215ec3.tar.gz u-boot-imx-8ffcf74bb057d049c379b2bdc126871c81215ec3.tar.bz2 | |
ARM: OMAP5: Add PRCM and Control information for SATA
Adds the necessary PRCM and Control register information for
SATA on OMAP5.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/prcm-regs.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 304ac1c..5c60d74 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = { .cm_l3init_hsusbotg_clkctrl = 0x4a009360, .cm_l3init_hsusbtll_clkctrl = 0x4a009368, .cm_l3init_p1500_clkctrl = 0x4a009378, + .cm_l3init_sata_clkctrl = 0x4a009388, .cm_l3init_fsusb_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, /* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009400, @@ -296,6 +298,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_status = 0x4A002134, .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, .control_phy_power_usb = 0x4A002370, + .control_phy_power_sata = 0x4A002374, .control_padconf_core_base = 0x4A002800, .control_paconf_global = 0x4A002DA0, .control_paconf_mode = 0x4A002DA4, @@ -698,6 +701,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_l3init_hsusbotg_clkctrl = 0x4a009660, .cm_l3init_hsusbtll_clkctrl = 0x4a009668, .cm_l3init_p1500_clkctrl = 0x4a009678, + .cm_l3init_sata_clkctrl = 0x4a009688, .cm_l3init_fsusb_clkctrl = 0x4a0096d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, |