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| author | Aneesh V <aneesh@ti.com> | 2011-06-16 23:30:52 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-07-04 10:55:25 +0200 |
| commit | 8b457fa828971ac036b15e98e65d99b6354c5496 (patch) | |
| tree | 6b79627efe11e2c39e91682ac8e16849c6a60f2d /arch/arm/cpu | |
| parent | 93bc21930a1bfbc98e3121035207eafa427ee07f (diff) | |
| download | u-boot-imx-8b457fa828971ac036b15e98e65d99b6354c5496.zip u-boot-imx-8b457fa828971ac036b15e98e65d99b6354c5496.tar.gz u-boot-imx-8b457fa828971ac036b15e98e65d99b6354c5496.tar.bz2 | |
armv7: adapt omap4 to the new cache maintenance framework
adapt omap4 to the new layered cache maintenance framework
Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/board.c | 12 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/lowlevel_init.S | 9 |
2 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index fcd29a7..de4cc2a 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -127,3 +127,15 @@ int arch_cpu_init(void) set_muxconf_regs(); return 0; } + +#ifndef CONFIG_SYS_L2CACHE_OFF +void v7_outer_cache_enable(void) +{ + set_pl310_ctrl_reg(1); +} + +void v7_outer_cache_disable(void) +{ + set_pl310_ctrl_reg(0); +} +#endif diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S index 026dfa4..6abfbba 100644 --- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S @@ -45,3 +45,12 @@ lowlevel_init: */ bl s_init pop {ip, pc} + +.globl set_pl310_ctrl_reg +set_pl310_ctrl_reg: + PUSH {r4-r11, lr} @ save registers - ROM code may pollute + @ our registers + LDR r12, =0x102 @ Set PL310 control register - value in R0 + .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 + @ call ROM Code API to set control register + POP {r4-r11, pc} |