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authorLei Wen <leiwen@marvell.com>2011-10-03 20:33:41 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-10-27 21:56:37 +0200
commit3d90a2adcb1c240c9ef9e9088a4d49a40a3c9504 (patch)
treedcd7dd00b6fda54e8c7fa9e61f95107bdee2ff9b /arch/arm/cpu
parent23365af0992e939b12b85050212b44b7dfae3d39 (diff)
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ARM: pantheon: add mmc definition
Signed-off-by: Lei Wen <leiwen@marvell.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/cpu.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
index efc9395..db9b348 100644
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -42,6 +42,9 @@ int arch_cpu_init(void)
struct panthmpmu_registers *mpmu =
(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
+ struct panthapmu_registers *apmu =
+ (struct panthapmu_registers *) PANTHEON_APMU_BASE;
+
/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
val = readl(&cpuregs->cpu_conf);
val = val | SET_MRVL_ID;
@@ -65,6 +68,14 @@ int arch_cpu_init(void)
writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
#endif
+#ifdef CONFIG_MV_SDHCI
+ /* Enable mmc clock */
+ writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+ &apmu->sd1);
+ writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+ &apmu->sd3);
+#endif
+
icache_enable();
return 0;