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| author | Bai Ping <ping.bai@nxp.com> | 2017-02-09 13:50:32 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 17:24:32 +0800 |
| commit | de38b748fcd138ddcae4dda2bcfbf04466c33d21 (patch) | |
| tree | a5f8c4776cfbd75317aade8da1a22cff9419aa92 /arch/arm/cpu | |
| parent | 0e6bbe0b01a4f7142c8d740b163265cd92499539 (diff) | |
| download | u-boot-imx-de38b748fcd138ddcae4dda2bcfbf04466c33d21.zip u-boot-imx-de38b748fcd138ddcae4dda2bcfbf04466c33d21.tar.gz u-boot-imx-de38b748fcd138ddcae4dda2bcfbf04466c33d21.tar.bz2 | |
MLK-13899 ARM: mx7ulp: Correct the clock index on imx7ulp
On i.MX7ULP, value zero is reserved in SCG1 RCCR register,
so the val should be decreased by 1 to get the correct clock
source index.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 7c9a3573ec0191f1e0bea12956346a5eab2db43a)
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/mx7ulp/scg.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx7ulp/scg.c b/arch/arm/cpu/armv7/mx7ulp/scg.c index ca8252d..d759d72 100644 --- a/arch/arm/cpu/armv7/mx7ulp/scg.c +++ b/arch/arm/cpu/armv7/mx7ulp/scg.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -443,7 +444,7 @@ static u32 scg_sys_get_rate(enum scg_clk clk) case SCG_SCS_SLOW_IRC: case SCG_SCS_FAST_IRC: case SCG_SCS_RTC_OSC: - rate = scg_src_get_rate(scg_scs_array[val]); + rate = scg_src_get_rate(scg_scs_array[val - 1]); break; case 5: rate = scg_apll_get_rate(); |