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authorAlison Wang <b18965@freescale.com>2015-11-05 11:15:49 +0800
committerYork Sun <yorksun@freescale.com>2015-11-30 09:11:11 -0800
commitd764129d30768df72cd07844dd50d11e74b0de14 (patch)
tree92ea1506c470dd8f0f04928858e57d4017b65272 /arch/arm/cpu
parent61bd2f75f5eaf645e2c90fe2294cba37f7d8627f (diff)
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armv8/layerscape: Update MMU table with execute-never bits
For most device addresses excution shouldn't be allowed. Revise the MMU table to enforce execute-never bits. OCRAM, DDR and IFC are allowed for excution. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv8/cache_v8.c4
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 1ece6a2..53bac3b 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -13,13 +13,13 @@ DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
- u64 memory_type, u64 share)
+ u64 memory_type, u64 attribute)
{
u64 value;
value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
- value |= share;
+ value |= attribute;
page_table[index] = value;
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index c6e00b8..571ee7b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -76,7 +76,7 @@ static int set_block_entry(const struct sys_mmu_table *list,
index,
block_addr,
list->memory_type,
- list->share);
+ list->attribute);
block_addr += block_size;
index++;
}