summaryrefslogtreecommitdiff
path: root/arch/arm/cpu
diff options
context:
space:
mode:
authorStefano Babic <sbabic@denx.de>2015-03-02 09:42:53 +0100
committerStefano Babic <sbabic@denx.de>2015-03-02 09:42:53 +0100
commitb9cb64825b5e6efeb715abd8b48d9b12f98973e9 (patch)
treed70d73a986308dee88474572006f5c60b10749be /arch/arm/cpu
parent4579dc37c3cce36d9521c26c6e82881393ec769e (diff)
parent1606b34aa50804227806971dbb6b82ea0bf81f55 (diff)
downloadu-boot-imx-b9cb64825b5e6efeb715abd8b48d9b12f98973e9.zip
u-boot-imx-b9cb64825b5e6efeb715abd8b48d9b12f98973e9.tar.gz
u-boot-imx-b9cb64825b5e6efeb715abd8b48d9b12f98973e9.tar.bz2
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/Makefile7
-rw-r--r--arch/arm/cpu/arm1176/Makefile1
-rw-r--r--arch/arm/cpu/arm1176/bcm2835/Kconfig12
-rw-r--r--arch/arm/cpu/arm1176/bcm2835/Makefile12
-rw-r--r--arch/arm/cpu/arm1176/start.S22
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/Makefile6
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/aemif.c78
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/clock.c432
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/init.c22
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S10
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/mux.c319
-rw-r--r--arch/arm/cpu/arm1176/tnetv107x/timer.c93
-rw-r--r--arch/arm/cpu/arm720t/Makefile6
-rw-r--r--arch/arm/cpu/arm720t/tegra-common/Makefile11
-rw-r--r--arch/arm/cpu/arm720t/tegra-common/cpu.c384
-rw-r--r--arch/arm/cpu/arm720t/tegra-common/cpu.h74
-rw-r--r--arch/arm/cpu/arm720t/tegra-common/spl.c49
-rw-r--r--arch/arm/cpu/arm720t/tegra114/Makefile21
-rw-r--r--arch/arm/cpu/arm720t/tegra114/cpu.c310
-rw-r--r--arch/arm/cpu/arm720t/tegra124/Makefile8
-rw-r--r--arch/arm/cpu/arm720t/tegra124/cpu.c265
-rw-r--r--arch/arm/cpu/arm720t/tegra20/Makefile10
-rw-r--r--arch/arm/cpu/arm720t/tegra20/cpu.c70
-rw-r--r--arch/arm/cpu/arm720t/tegra30/Makefile20
-rw-r--r--arch/arm/cpu/arm720t/tegra30/cpu.c183
-rw-r--r--arch/arm/cpu/arm920t/Makefile3
-rw-r--r--arch/arm/cpu/arm920t/a320/Makefile9
-rw-r--r--arch/arm/cpu/arm920t/a320/reset.S10
-rw-r--r--arch/arm/cpu/arm920t/a320/timer.c118
-rw-r--r--arch/arm/cpu/arm920t/at91/Makefile13
-rw-r--r--arch/arm/cpu/arm920t/at91/at91rm9200_devices.c67
-rw-r--r--arch/arm/cpu/arm920t/at91/clock.c157
-rw-r--r--arch/arm/cpu/arm920t/at91/cpu.c26
-rw-r--r--arch/arm/cpu/arm920t/at91/lowlevel_init.S152
-rw-r--r--arch/arm/cpu/arm920t/at91/reset.c41
-rw-r--r--arch/arm/cpu/arm920t/at91/timer.c127
-rw-r--r--arch/arm/cpu/arm920t/ks8695/Makefile9
-rw-r--r--arch/arm/cpu/arm920t/ks8695/lowlevel_init.S189
-rw-r--r--arch/arm/cpu/arm920t/ks8695/timer.c77
-rw-r--r--arch/arm/cpu/arm926ejs/Makefile8
-rw-r--r--arch/arm/cpu/arm926ejs/at91/Makefile28
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c245
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c140
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c218
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c184
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c161
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c103
-rw-r--r--arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c244
-rw-r--r--arch/arm/cpu/arm926ejs/at91/clock.c249
-rw-r--r--arch/arm/cpu/arm926ejs/at91/config.mk2
-rw-r--r--arch/arm/cpu/arm926ejs/at91/cpu.c57
-rw-r--r--arch/arm/cpu/arm926ejs/at91/eflash.c254
-rw-r--r--arch/arm/cpu/arm926ejs/at91/led.c48
-rw-r--r--arch/arm/cpu/arm926ejs/at91/lowlevel_init.S246
-rw-r--r--arch/arm/cpu/arm926ejs/at91/reset.c29
-rw-r--r--arch/arm/cpu/arm926ejs/at91/timer.c120
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/Kconfig78
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/Makefile28
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/config.mk8
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/cpu.c223
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c139
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c313
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c181
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/dm355.c30
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/dm365.c20
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c460
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/dm644x.c81
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/dm646x.c26
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/dp83848.c128
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/et1011c.c42
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/ksz8873.c53
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S693
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/lxt972.c113
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/misc.c138
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/pinmux.c90
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/psc.c160
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/reset.c32
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/spl.c65
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/timer.c128
-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/Kconfig88
-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/Makefile11
-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/cache.c19
-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/cpu.c321
-rw-r--r--arch/arm/cpu/arm926ejs/kirkwood/mpp.c90
-rw-r--r--arch/arm/cpu/arm926ejs/mb86r0x/Makefile8
-rw-r--r--arch/arm/cpu/arm926ejs/mb86r0x/clock.c27
-rw-r--r--arch/arm/cpu/arm926ejs/mb86r0x/reset.c24
-rw-r--r--arch/arm/cpu/arm926ejs/mb86r0x/timer.c115
-rw-r--r--arch/arm/cpu/arm926ejs/nomadik/Kconfig16
-rw-r--r--arch/arm/cpu/arm926ejs/nomadik/Makefile9
-rw-r--r--arch/arm/cpu/arm926ejs/nomadik/gpio.c83
-rw-r--r--arch/arm/cpu/arm926ejs/nomadik/reset.S14
-rw-r--r--arch/arm/cpu/arm926ejs/nomadik/timer.c71
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/Kconfig16
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/Makefile18
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/cpu.c294
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/dram.c55
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S277
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/timer.c171
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/Makefile9
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/cpu.c85
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/dram.c117
-rw-r--r--arch/arm/cpu/arm926ejs/pantheon/timer.c201
-rw-r--r--arch/arm/cpu/arm926ejs/versatile/Kconfig15
-rw-r--r--arch/arm/cpu/arm926ejs/versatile/Makefile9
-rw-r--r--arch/arm/cpu/arm926ejs/versatile/reset.S29
-rw-r--r--arch/arm/cpu/arm926ejs/versatile/timer.c64
-rw-r--r--arch/arm/cpu/armv7/Makefile6
-rw-r--r--arch/arm/cpu/armv7/am33xx/clock_am43xx.c3
-rw-r--r--arch/arm/cpu/armv7/at91/Makefile16
-rw-r--r--arch/arm/cpu/armv7/at91/clock.c175
-rw-r--r--arch/arm/cpu/armv7/at91/config.mk8
-rw-r--r--arch/arm/cpu/armv7/at91/cpu.c76
-rw-r--r--arch/arm/cpu/armv7/at91/reset.c31
-rw-r--r--arch/arm/cpu/armv7/at91/sama5d3_devices.c218
-rw-r--r--arch/arm/cpu/armv7/at91/sama5d4_devices.c93
-rw-r--r--arch/arm/cpu/armv7/at91/timer.c124
-rw-r--r--arch/arm/cpu/armv7/bcm2835/Makefile13
-rw-r--r--arch/arm/cpu/armv7/exynos/Kconfig35
-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c621
-rw-r--r--arch/arm/cpu/armv7/exynos/power.c28
-rw-r--r--arch/arm/cpu/armv7/exynos/spl_boot.c1
-rw-r--r--arch/arm/cpu/armv7/highbank/Kconfig12
-rw-r--r--arch/arm/cpu/armv7/highbank/Makefile8
-rw-r--r--arch/arm/cpu/armv7/highbank/timer.c34
-rw-r--r--arch/arm/cpu/armv7/keystone/Kconfig22
-rw-r--r--arch/arm/cpu/armv7/keystone/Makefile18
-rw-r--r--arch/arm/cpu/armv7/keystone/clock-k2e.c117
-rw-r--r--arch/arm/cpu/armv7/keystone/clock-k2hk.c145
-rw-r--r--arch/arm/cpu/armv7/keystone/clock-k2l.c138
-rw-r--r--arch/arm/cpu/armv7/keystone/clock.c272
-rw-r--r--arch/arm/cpu/armv7/keystone/cmd_clock.c135
-rw-r--r--arch/arm/cpu/armv7/keystone/cmd_ddr3.c248
-rw-r--r--arch/arm/cpu/armv7/keystone/cmd_mon.c131
-rw-r--r--arch/arm/cpu/armv7/keystone/ddr3.c407
-rw-r--r--arch/arm/cpu/armv7/keystone/init.c151
-rw-r--r--arch/arm/cpu/armv7/keystone/keystone.c87
-rw-r--r--arch/arm/cpu/armv7/keystone/msmc.c94
-rw-r--r--arch/arm/cpu/armv7/keystone/psc.c227
-rw-r--r--arch/arm/cpu/armv7/ls102xa/cpu.c231
-rw-r--r--arch/arm/cpu/armv7/omap-common/emif-common.c4
-rw-r--r--arch/arm/cpu/armv7/omap-common/lowlevel_init.S2
-rw-r--r--arch/arm/cpu/armv7/omap3/Kconfig15
-rw-r--r--arch/arm/cpu/armv7/omap3/lowlevel_init.S2
-rw-r--r--arch/arm/cpu/armv7/omap5/sdram.c83
-rw-r--r--arch/arm/cpu/armv7/rmobile/Kconfig6
-rw-r--r--arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S12
-rw-r--r--arch/arm/cpu/armv7/s5pc1xx/Kconfig4
-rw-r--r--arch/arm/cpu/armv7/start.S7
-rw-r--r--arch/arm/cpu/armv7/sunxi/Makefile5
-rw-r--r--arch/arm/cpu/armv7/sunxi/board.c46
-rw-r--r--arch/arm/cpu/armv7/sunxi/config.mk2
-rw-r--r--arch/arm/cpu/armv7/sunxi/dram_helpers.c37
-rw-r--r--arch/arm/cpu/armv7/sunxi/fel_utils.S42
-rw-r--r--arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds82
-rw-r--r--arch/arm/cpu/armv7/tegra-common/Kconfig28
-rw-r--r--arch/arm/cpu/armv7/tegra-common/Makefile10
-rw-r--r--arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c51
-rw-r--r--arch/arm/cpu/armv7/tegra114/Kconfig16
-rw-r--r--arch/arm/cpu/armv7/tegra124/Kconfig30
-rw-r--r--arch/arm/cpu/armv7/tegra20/Kconfig52
-rw-r--r--arch/arm/cpu/armv7/tegra20/Makefile11
-rw-r--r--arch/arm/cpu/armv7/tegra20/display.c394
-rw-r--r--arch/arm/cpu/armv7/tegra20/pwm.c86
-rw-r--r--arch/arm/cpu/armv7/tegra30/Kconfig32
-rw-r--r--arch/arm/cpu/armv7/uniphier/Kconfig8
-rw-r--r--arch/arm/cpu/armv8/cache.S6
-rw-r--r--arch/arm/cpu/armv8/cache_v8.c18
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/cpu.c62
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/fdt.c28
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S132
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/mp.c8
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/mp.h1
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/speed.c16
-rw-r--r--arch/arm/cpu/at91-common/Makefile18
-rw-r--r--arch/arm/cpu/at91-common/mpddrc.c133
-rw-r--r--arch/arm/cpu/at91-common/phy.c57
-rw-r--r--arch/arm/cpu/at91-common/sdram.c77
-rw-r--r--arch/arm/cpu/at91-common/spl.c50
-rw-r--r--arch/arm/cpu/at91-common/spl_at91.c124
-rw-r--r--arch/arm/cpu/at91-common/spl_atmel.c96
-rw-r--r--arch/arm/cpu/at91-common/u-boot-spl.lds55
-rw-r--r--arch/arm/cpu/tegra-common/Makefile19
-rw-r--r--arch/arm/cpu/tegra-common/ap.c169
-rw-r--r--arch/arm/cpu/tegra-common/board.c159
-rw-r--r--arch/arm/cpu/tegra-common/cache.c46
-rw-r--r--arch/arm/cpu/tegra-common/clock.c669
-rw-r--r--arch/arm/cpu/tegra-common/lowlevel_init.S26
-rw-r--r--arch/arm/cpu/tegra-common/pinmux-common.c527
-rw-r--r--arch/arm/cpu/tegra-common/powergate.c102
-rw-r--r--arch/arm/cpu/tegra-common/sys_info.c31
-rw-r--r--arch/arm/cpu/tegra-common/vpr.c35
-rw-r--r--arch/arm/cpu/tegra-common/xusb-padctl.c39
-rw-r--r--arch/arm/cpu/tegra114-common/Makefile20
-rw-r--r--arch/arm/cpu/tegra114-common/clock.c669
-rw-r--r--arch/arm/cpu/tegra114-common/funcmux.c67
-rw-r--r--arch/arm/cpu/tegra114-common/pinmux.c293
-rw-r--r--arch/arm/cpu/tegra124-common/Makefile11
-rw-r--r--arch/arm/cpu/tegra124-common/clock.c935
-rw-r--r--arch/arm/cpu/tegra124-common/funcmux.c71
-rw-r--r--arch/arm/cpu/tegra124-common/pinmux.c306
-rw-r--r--arch/arm/cpu/tegra124-common/xusb-padctl.c716
-rw-r--r--arch/arm/cpu/tegra20-common/Makefile17
-rw-r--r--arch/arm/cpu/tegra20-common/clock.c687
-rw-r--r--arch/arm/cpu/tegra20-common/crypto.c137
-rw-r--r--arch/arm/cpu/tegra20-common/crypto.h20
-rw-r--r--arch/arm/cpu/tegra20-common/emc.c270
-rw-r--r--arch/arm/cpu/tegra20-common/funcmux.c296
-rw-r--r--arch/arm/cpu/tegra20-common/pinmux.c425
-rw-r--r--arch/arm/cpu/tegra20-common/pmu.c65
-rw-r--r--arch/arm/cpu/tegra20-common/warmboot.c372
-rw-r--r--arch/arm/cpu/tegra20-common/warmboot_avp.c236
-rw-r--r--arch/arm/cpu/tegra20-common/warmboot_avp.h65
-rw-r--r--arch/arm/cpu/tegra30-common/Makefile20
-rw-r--r--arch/arm/cpu/tegra30-common/clock.c744
-rw-r--r--arch/arm/cpu/tegra30-common/funcmux.c61
-rw-r--r--arch/arm/cpu/tegra30-common/pinmux.c276
217 files changed, 1019 insertions, 24699 deletions
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index 35d8d38..6bea3d3 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1,6 +1 @@
-obj-$(CONFIG_AT91FAMILY) += at91-common/
-obj-$(CONFIG_TEGRA20) += tegra20-common/
-obj-$(CONFIG_TEGRA30) += tegra30-common/
-obj-$(CONFIG_TEGRA114) += tegra114-common/
-obj-$(CONFIG_TEGRA124) += tegra124-common/
-obj-$(CONFIG_TEGRA) += tegra-common/
+obj- += dummy.o
diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile
index ead2303..480e130 100644
--- a/arch/arm/cpu/arm1176/Makefile
+++ b/arch/arm/cpu/arm1176/Makefile
@@ -12,4 +12,3 @@ extra-y = start.o
obj-y = cpu.o
obj-$(CONFIG_BCM2835) += bcm2835/
-obj-$(CONFIG_TNETV107X) += tnetv107x/
diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig
new file mode 100644
index 0000000..73cc72b
--- /dev/null
+++ b/arch/arm/cpu/arm1176/bcm2835/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_RPI || TARGET_RPI_2
+
+config DM
+ default y
+
+config DM_SERIAL
+ default y
+
+config DM_GPIO
+ default y
+
+endif
diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile
index 0ad3690..7e5dbe1 100644
--- a/arch/arm/cpu/arm1176/bcm2835/Makefile
+++ b/arch/arm/cpu/arm1176/bcm2835/Makefile
@@ -1,15 +1,7 @@
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# (C) Copyright 2012 Stephen Warren
#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
+# SPDX-License-Identifier: GPL-2.0
#
obj-y := lowlevel_init.o
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 0704bdd..ac937bf 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -96,28 +96,6 @@ mmu_disable:
mov pc, r2
mmu_disable_phys:
-#ifdef CONFIG_DISABLE_TCM
- /*
- * Disable the TCMs
- */
- mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
- cmp r0, #0
- beq skip_tcmdisable
- mov r1, #0
- mov r2, #1
- tst r0, r2
- mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
- tst r0, r2, LSL #16
- mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
-skip_tcmdisable:
-#endif
-#endif
-
-#ifdef CONFIG_PERIPORT_REMAP
- /* Peri port setup */
- ldr r0, =CONFIG_PERIPORT_BASE
- orr r0, r0, #CONFIG_PERIPORT_SIZE
- mcr p15,0,r0,c15,c2,4
#endif
/*
diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile
deleted file mode 100644
index a4c1edf..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += aemif.o clock.o init.o mux.o timer.o
-obj-y += lowlevel_init.o
diff --git a/arch/arm/cpu/arm1176/tnetv107x/aemif.c b/arch/arm/cpu/arm1176/tnetv107x/aemif.c
deleted file mode 100644
index a0f5728..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/aemif.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * TNETV107X: Asynchronous EMIF Configuration
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE
-#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4)
-#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c)
-#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60)
-#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4)
-
-#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0)
-#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0)
-#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26)
-#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20)
-#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17)
-#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13)
-#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7)
-#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4)
-#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2)
-#define CONFIG_WIDTH(v) (((v) & 0x03) << 0)
-
-#define NUM_CS 4
-
-#define set_config_field(reg, field, val) \
- do { \
- if (val != -1) { \
- reg &= ~CONFIG_##field(0xffffffff); \
- reg |= CONFIG_##field(val); \
- } \
- } while (0)
-
-void configure_async_emif(int cs, struct async_emif_config *cfg)
-{
- unsigned long tmp;
-
- if (cfg->mode == ASYNC_EMIF_MODE_NAND) {
- tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL);
- tmp |= (1 << cs);
- __raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL);
-
- } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) {
- tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL);
- tmp |= (1 << cs);
- __raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL);
- }
-
- tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs));
-
- set_config_field(tmp, SELECT_STROBE, cfg->select_strobe);
- set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait);
- set_config_field(tmp, WR_SETUP, cfg->wr_setup);
- set_config_field(tmp, WR_STROBE, cfg->wr_strobe);
- set_config_field(tmp, WR_HOLD, cfg->wr_hold);
- set_config_field(tmp, RD_SETUP, cfg->rd_setup);
- set_config_field(tmp, RD_STROBE, cfg->rd_strobe);
- set_config_field(tmp, RD_HOLD, cfg->rd_hold);
- set_config_field(tmp, TURN_AROUND, cfg->turn_around);
- set_config_field(tmp, WIDTH, cfg->width);
-
- __raw_writel(tmp, ASYNC_EMIF_CONFIG(cs));
-}
-
-void init_async_emif(int num_cs, struct async_emif_config *config)
-{
- int cs;
-
- clk_enable(TNETV107X_LPSC_AEMIF);
-
- for (cs = 0; cs < num_cs; cs++)
- configure_async_emif(cs, config + cs);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c
deleted file mode 100644
index 7ba28d3..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/clock.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * TNETV107X: Clock management APIs
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/clock.h>
-
-#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE
-#define PSC_BASE TNETV107X_PSC_BASE
-
-#define BIT(x) (1 << (x))
-
-#define MAX_PREDIV 64
-#define MAX_POSTDIV 8UL
-#define MAX_MULT 512
-#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV)
-
-/* LPSC registers */
-#define PSC_PTCMD 0x120
-#define PSC_PTSTAT 0x128
-#define PSC_MDSTAT(n) (0x800 + (n) * 4)
-#define PSC_MDCTL(n) (0xA00 + (n) * 4)
-
-#define PSC_MDCTL_LRSTZ BIT(8)
-
-#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg)))
-#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg)))
-
-/* SSPLL registers */
-struct sspll_regs {
- u32 modes;
- u32 postdiv;
- u32 prediv;
- u32 mult_factor;
- u32 divider_range;
- u32 bw_divider;
- u32 spr_amount;
- u32 spr_rate_div;
- u32 diag;
-};
-
-/* SSPLL base addresses */
-static struct sspll_regs *sspll_regs[] = {
- (struct sspll_regs *)(CLOCK_BASE + 0x040),
- (struct sspll_regs *)(CLOCK_BASE + 0x080),
- (struct sspll_regs *)(CLOCK_BASE + 0x0c0),
-};
-
-#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg))
-#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg))
-#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg))
-
-
-/* PLL Control Registers */
-struct pllctl_regs {
- u32 ctl; /* 00 */
- u32 ocsel; /* 04 */
- u32 secctl; /* 08 */
- u32 __pad0;
- u32 mult; /* 10 */
- u32 prediv; /* 14 */
- u32 div1; /* 18 */
- u32 div2; /* 1c */
- u32 div3; /* 20 */
- u32 oscdiv1; /* 24 */
- u32 postdiv; /* 28 */
- u32 bpdiv; /* 2c */
- u32 wakeup; /* 30 */
- u32 __pad1;
- u32 cmd; /* 38 */
- u32 stat; /* 3c */
- u32 alnctl; /* 40 */
- u32 dchange; /* 44 */
- u32 cken; /* 48 */
- u32 ckstat; /* 4c */
- u32 systat; /* 50 */
- u32 ckctl; /* 54 */
- u32 __pad2[2];
- u32 div4; /* 60 */
- u32 div5; /* 64 */
- u32 div6; /* 68 */
- u32 div7; /* 6c */
- u32 div8; /* 70 */
-};
-
-struct lpsc_map {
- int pll, div;
-};
-
-static struct pllctl_regs *pllctl_regs[] = {
- (struct pllctl_regs *)(CLOCK_BASE + 0x700),
- (struct pllctl_regs *)(CLOCK_BASE + 0x300),
- (struct pllctl_regs *)(CLOCK_BASE + 0x500),
-};
-
-#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
-#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
-#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
-
-#define pllctl_reg_rmw(pll, reg, mask, val) \
- pllctl_reg_write(pll, reg, \
- (pllctl_reg_read(pll, reg) & ~(mask)) | val)
-
-#define pllctl_reg_setbits(pll, reg, mask) \
- pllctl_reg_rmw(pll, reg, 0, mask)
-
-#define pllctl_reg_clrbits(pll, reg, mask) \
- pllctl_reg_rmw(pll, reg, mask, 0)
-
-/* PLLCTL Bits */
-#define PLLCTL_CLKMODE BIT(8)
-#define PLLCTL_PLLSELB BIT(7)
-#define PLLCTL_PLLENSRC BIT(5)
-#define PLLCTL_PLLDIS BIT(4)
-#define PLLCTL_PLLRST BIT(3)
-#define PLLCTL_PLLPWRDN BIT(1)
-#define PLLCTL_PLLEN BIT(0)
-
-#define PLLDIV_ENABLE BIT(15)
-
-static int pll_div_offset[] = {
-#define div_offset(reg) offsetof(struct pllctl_regs, reg)
- div_offset(div1), div_offset(div2), div_offset(div3),
- div_offset(div4), div_offset(div5), div_offset(div6),
- div_offset(div7), div_offset(div8),
-};
-
-static unsigned long pll_bypass_mask[] = { 1, 4, 2 };
-static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
-
-/* Mappings from PLL+DIV to subsystem clocks */
-#define sys_arm1176_clk {SYS_PLL, 0}
-#define sys_dsp_clk {SYS_PLL, 1}
-#define sys_ddr_clk {SYS_PLL, 2}
-#define sys_full_clk {SYS_PLL, 3}
-#define sys_lcd_clk {SYS_PLL, 4}
-#define sys_vlynq_ref_clk {SYS_PLL, 5}
-#define sys_tsc_clk {SYS_PLL, 6}
-#define sys_half_clk {SYS_PLL, 7}
-
-#define eth_clk_5 {ETH_PLL, 0}
-#define eth_clk_50 {ETH_PLL, 1}
-#define eth_clk_125 {ETH_PLL, 2}
-#define eth_clk_250 {ETH_PLL, 3}
-#define eth_clk_25 {ETH_PLL, 4}
-
-#define tdm_clk {TDM_PLL, 0}
-#define tdm_extra_clk {TDM_PLL, 1}
-#define tdm1_clk {TDM_PLL, 2}
-
-static const struct lpsc_map lpsc_clk_map[] = {
- [TNETV107X_LPSC_ARM] = sys_arm1176_clk,
- [TNETV107X_LPSC_GEM] = sys_dsp_clk,
- [TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk,
- [TNETV107X_LPSC_TPCC] = sys_full_clk,
- [TNETV107X_LPSC_TPTC0] = sys_full_clk,
- [TNETV107X_LPSC_TPTC1] = sys_full_clk,
- [TNETV107X_LPSC_RAM] = sys_full_clk,
- [TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk,
- [TNETV107X_LPSC_LCD] = sys_lcd_clk,
- [TNETV107X_LPSC_ETHSS] = eth_clk_125,
- [TNETV107X_LPSC_AEMIF] = sys_full_clk,
- [TNETV107X_LPSC_CHIP_CFG] = sys_half_clk,
- [TNETV107X_LPSC_TSC] = sys_tsc_clk,
- [TNETV107X_LPSC_ROM] = sys_half_clk,
- [TNETV107X_LPSC_UART2] = sys_half_clk,
- [TNETV107X_LPSC_PKTSEC] = sys_half_clk,
- [TNETV107X_LPSC_SECCTL] = sys_half_clk,
- [TNETV107X_LPSC_KEYMGR] = sys_half_clk,
- [TNETV107X_LPSC_KEYPAD] = sys_half_clk,
- [TNETV107X_LPSC_GPIO] = sys_half_clk,
- [TNETV107X_LPSC_MDIO] = sys_half_clk,
- [TNETV107X_LPSC_SDIO0] = sys_half_clk,
- [TNETV107X_LPSC_UART0] = sys_half_clk,
- [TNETV107X_LPSC_UART1] = sys_half_clk,
- [TNETV107X_LPSC_TIMER0] = sys_half_clk,
- [TNETV107X_LPSC_TIMER1] = sys_half_clk,
- [TNETV107X_LPSC_WDT_ARM] = sys_half_clk,
- [TNETV107X_LPSC_WDT_DSP] = sys_half_clk,
- [TNETV107X_LPSC_SSP] = sys_half_clk,
- [TNETV107X_LPSC_TDM0] = tdm_clk,
- [TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk,
- [TNETV107X_LPSC_MCDMA] = sys_half_clk,
- [TNETV107X_LPSC_USB0] = sys_half_clk,
- [TNETV107X_LPSC_TDM1] = tdm1_clk,
- [TNETV107X_LPSC_DEBUGSS] = sys_half_clk,
- [TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250,
- [TNETV107X_LPSC_SYSTEM] = sys_half_clk,
- [TNETV107X_LPSC_IMCOP] = sys_dsp_clk,
- [TNETV107X_LPSC_SPARE] = sys_half_clk,
- [TNETV107X_LPSC_SDIO1] = sys_half_clk,
- [TNETV107X_LPSC_USB1] = sys_half_clk,
- [TNETV107X_LPSC_USBSS] = sys_half_clk,
- [TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk,
- [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk,
-};
-
-static const unsigned long pll_ext_freq[] = {
- [SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ,
- [ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ,
- [TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ,
-};
-
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, postdiv = 1;
- unsigned long ref = CONFIG_SYS_INT_OSC_FREQ;
- unsigned long ret;
- u32 bypass;
-
- bypass = __raw_readl((u32 *)(CLOCK_BASE));
- if (!(bypass & pll_bypass_mask[pll])) {
- mult = sspll_reg_read(pll, mult_factor);
- prediv = sspll_reg_read(pll, prediv) + 1;
- postdiv = sspll_reg_read(pll, postdiv) + 1;
- }
-
- if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE)
- ref = pll_ext_freq[pll];
-
- if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN))
- return ref;
-
- ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256);
- ret /= (prediv * postdiv);
-
- return ret;
-}
-
-static unsigned long __pll_div_freq_get(int pll, unsigned int fpll,
- int div)
-{
- int divider = 1;
- unsigned long divreg;
-
- divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]);
-
- if (divreg & PLLDIV_ENABLE)
- divider = (divreg & pll_div_mask[pll]) + 1;
-
- return fpll / divider;
-}
-
-static unsigned long pll_div_freq_get(int pll, int div)
-{
- unsigned int fpll = pll_freq_get(pll);
-
- return __pll_div_freq_get(pll, fpll, div);
-}
-
-static void __pll_div_freq_set(int pll, unsigned int fpll, int div,
- unsigned long hz)
-{
- int divider = (fpll / hz - 1);
-
- divider &= pll_div_mask[pll];
- divider |= PLLDIV_ENABLE;
-
- __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]);
- pllctl_reg_setbits(pll, alnctl, (1 << div));
- pllctl_reg_setbits(pll, dchange, (1 << div));
-}
-
-static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz)
-{
- unsigned int fpll = pll_freq_get(pll);
-
- __pll_div_freq_set(pll, fpll, div, hz);
-
- pllctl_reg_write(pll, cmd, 1);
-
- /* Wait until new divider takes effect */
- while (pllctl_reg_read(pll, stat) & 0x01);
-
- return __pll_div_freq_get(pll, fpll, div);
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div);
-}
-
-unsigned long clk_round_rate(unsigned int clk, unsigned long hz)
-{
- unsigned long fpll, divider, pll;
-
- pll = lpsc_clk_map[clk].pll;
- fpll = pll_freq_get(pll);
- divider = (fpll / hz - 1);
- divider &= pll_div_mask[pll];
-
- return fpll / (divider + 1);
-}
-
-int clk_set_rate(unsigned int clk, unsigned long _hz)
-{
- unsigned long hz;
-
- hz = clk_round_rate(clk, _hz);
- if (hz != _hz)
- return -EINVAL; /* Cannot set to target freq */
-
- pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz);
- return 0;
-}
-
-void lpsc_control(int mod, unsigned long state, int lrstz)
-{
- u32 mdctl;
-
- mdctl = psc_reg_read(PSC_MDCTL(mod));
- mdctl &= ~0x1f;
- mdctl |= state;
-
- if (lrstz == 0)
- mdctl &= ~PSC_MDCTL_LRSTZ;
- else if (lrstz == 1)
- mdctl |= PSC_MDCTL_LRSTZ;
-
- psc_reg_write(PSC_MDCTL(mod), mdctl);
-
- psc_reg_write(PSC_PTCMD, 1);
-
- /* wait for power domain transition to end */
- while (psc_reg_read(PSC_PTSTAT) & 1);
-
- /* Wait for module state change */
- while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state);
-}
-
-int lpsc_status(unsigned int id)
-{
- return psc_reg_read(PSC_MDSTAT(id)) & 0x1f;
-}
-
-static void init_pll(const struct pll_init_data *data)
-{
- unsigned long fpll;
- unsigned long best_pre = 0, best_post = 0, best_mult = 0;
- unsigned long div, prediv, postdiv, mult;
- unsigned long delta, actual;
- long best_delta = -1;
- int i;
- u32 tmp;
-
- if (data->pll == SYS_PLL)
- return; /* cannot reconfigure system pll on the fly */
-
- tmp = pllctl_reg_read(data->pll, ctl);
- if (data->internal_osc) {
- tmp &= ~PLLCTL_CLKMODE;
- fpll = CONFIG_SYS_INT_OSC_FREQ;
- } else {
- tmp |= PLLCTL_CLKMODE;
- fpll = pll_ext_freq[data->pll];
- }
- pllctl_reg_write(data->pll, ctl, tmp);
-
- mult = data->pll_freq / fpll;
- for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) {
- div = (fpll * mult) / data->pll_freq;
- if (div < 1 || div > MAX_DIV)
- continue;
-
- for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) {
- prediv = div / postdiv;
- if (prediv < 1 || prediv > MAX_PREDIV)
- continue;
-
- actual = (fpll / prediv) * (mult / postdiv);
- delta = (actual - data->pll_freq);
- if (delta < 0)
- delta = -delta;
- if ((delta < best_delta) || (best_delta == -1)) {
- best_delta = delta;
- best_mult = mult;
- best_pre = prediv;
- best_post = postdiv;
- if (delta == 0)
- goto done;
- }
- }
- }
-done:
-
- if (best_delta == -1) {
- printf("pll cannot derive %lu from %lu\n",
- data->pll_freq, fpll);
- return;
- }
-
- fpll = fpll * best_mult;
- fpll /= best_pre * best_post;
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN);
-
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS);
-
- sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8);
- sspll_reg_write(data->pll, prediv, best_pre - 1);
- sspll_reg_write(data->pll, postdiv, best_post - 1);
-
- for (i = 0; i < 10; i++)
- if (data->div_freq[i])
- __pll_div_freq_set(data->pll, fpll, i,
- data->div_freq[i]);
-
- pllctl_reg_write(data->pll, cmd, 1);
-
- /* Wait until pll "go" operation completes */
- while (pllctl_reg_read(data->pll, stat) & 0x01);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
- int i;
-
- for (i = 0; i < num_pll; i++)
- init_pll(&config[i]);
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/init.c b/arch/arm/cpu/arm1176/tnetv107x/init.c
deleted file mode 100644
index d870826..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/init.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * TNETV107X: Architecture initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-void chip_configuration_unlock(void)
-{
- __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0);
- __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1);
-}
-
-int arch_cpu_init(void)
-{
- icache_enable();
- chip_configuration_unlock();
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
deleted file mode 100644
index a8bce47..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * TNETV107X: Low-level pre-relocation initialization
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.globl lowlevel_init
-lowlevel_init:
- /* nothing for now, maybe needed for more exotic boot modes */
- mov pc, lr
diff --git a/arch/arm/cpu/arm1176/tnetv107x/mux.c b/arch/arm/cpu/arm1176/tnetv107x/mux.c
deleted file mode 100644
index 310d84d..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/mux.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * TNETV107X: Pinmux configuration
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/mux.h>
-
-#define MUX_MODE_1 0x00
-#define MUX_MODE_2 0x04
-#define MUX_MODE_3 0x0c
-#define MUX_MODE_4 0x1c
-
-#define MUX_DEBUG 0
-
-static const struct pin_config pin_table[] = {
- /* reg shift mode */
- TNETV107X_MUX_CFG(0, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(0, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(0, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(1, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(1, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(2, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(2, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(3, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(4, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(4, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 20, MUX_MODE_3),
- TNETV107X_MUX_CFG(4, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(4, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(5, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(5, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(6, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(6, 25, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(7, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(7, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(7, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(7, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(8, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(8, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(8, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 0, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 5, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 10, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(9, 20, MUX_MODE_4),
- TNETV107X_MUX_CFG(10, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(10, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(10, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(11, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(11, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(12, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(13, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(14, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(15, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(15, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(15, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(16, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(16, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(16, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(17, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(18, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(19, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(19, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(20, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(20, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(21, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(22, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 20, MUX_MODE_3),
- TNETV107X_MUX_CFG(22, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(22, 25, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(23, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(23, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(24, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(24, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(24, 25, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 0, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 5, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 10, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_3),
- TNETV107X_MUX_CFG(25, 15, MUX_MODE_4),
- TNETV107X_MUX_CFG(26, 0, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 5, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 10, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 10, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 15, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 15, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 20, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 20, MUX_MODE_2),
- TNETV107X_MUX_CFG(26, 25, MUX_MODE_1),
- TNETV107X_MUX_CFG(26, 25, MUX_MODE_2),
-};
-
-const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]);
-
-int mux_select_pin(short index)
-{
- const struct pin_config *cfg;
- unsigned long mask, mode, reg;
-
- if (index >= pin_table_size)
- return 0;
-
- cfg = &pin_table[index];
-
- mask = 0x1f << cfg->mask_offset;
- mode = cfg->mode << cfg->mask_offset;
-
- reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index));
- reg = (reg & ~mask) | mode;
- __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index));
-
- return 1;
-}
-
-int mux_select_pins(const short *pins)
-{
- int i, ret = 1;
-
- for (i = 0; pins[i] >= 0; i++)
- ret &= mux_select_pin(pins[i]);
-
- return ret;
-}
diff --git a/arch/arm/cpu/arm1176/tnetv107x/timer.c b/arch/arm/cpu/arm1176/tnetv107x/timer.c
deleted file mode 100644
index 6e0dd0d..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/timer.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * TNETV107X: Timer implementation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-struct timer_regs {
- u_int32_t pid12;
- u_int32_t pad[3];
- u_int32_t tim12;
- u_int32_t tim34;
- u_int32_t prd12;
- u_int32_t prd34;
- u_int32_t tcr;
- u_int32_t tgcr;
- u_int32_t wdtcr;
-};
-
-#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE)
-
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
-#define TIM_CLK_DIV 16
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init(void)
-{
- clk_enable(TNETV107X_LPSC_TIMER0);
-
- lastinc = timestamp = 0;
-
- /* We are using timer34 in unchained 32-bit mode, full speed */
- __raw_writel(0x0, &regs->tcr);
- __raw_writel(0x0, &regs->tgcr);
- __raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr);
- __raw_writel(0x0, &regs->tim34);
- __raw_writel(TIMER_LOAD_VAL, &regs->prd34);
- __raw_writel(2 << 22, &regs->tcr);
-
- return 0;
-}
-
-static ulong get_timer_raw(void)
-{
- ulong now = __raw_readl(&regs->tim34);
-
- if (now >= lastinc)
- timestamp += now - lastinc;
- else
- timestamp += now + TIMER_LOAD_VAL - lastinc;
-
- lastinc = now;
-
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- tmo = CONFIG_SYS_HZ_CLOCK / 1000;
- tmo *= usec;
- tmo /= (1000 * TIM_CLK_DIV);
-
- endtime = get_timer_raw() + tmo;
-
- do {
- ulong now = get_timer_raw();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm720t/Makefile b/arch/arm/cpu/arm720t/Makefile
index 9f61ea2..243a123 100644
--- a/arch/arm/cpu/arm720t/Makefile
+++ b/arch/arm/cpu/arm720t/Makefile
@@ -7,9 +7,3 @@
extra-y = start.o
obj-y = interrupts.o cpu.o
-
-obj-$(CONFIG_TEGRA) += tegra-common/
-obj-$(CONFIG_TEGRA20) += tegra20/
-obj-$(CONFIG_TEGRA30) += tegra30/
-obj-$(CONFIG_TEGRA114) += tegra114/
-obj-$(CONFIG_TEGRA124) += tegra124/
diff --git a/arch/arm/cpu/arm720t/tegra-common/Makefile b/arch/arm/cpu/arm720t/tegra-common/Makefile
deleted file mode 100644
index a9c2b67..0000000
--- a/arch/arm/cpu/arm720t/tegra-common/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_SPL_BUILD) += spl.o
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
deleted file mode 100644
index c6f3b02..0000000
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/scu.h>
-#include "cpu.h"
-
-int get_num_cpus(void)
-{
- struct apb_misc_gp_ctlr *gp;
- uint rev;
-
- gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
- rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
-
- switch (rev) {
- case CHIPID_TEGRA20:
- return 2;
- break;
- case CHIPID_TEGRA30:
- case CHIPID_TEGRA114:
- default:
- return 4;
- break;
- }
-}
-
-/*
- * Timing tables for each SOC for all four oscillator options.
- */
-struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
- /*
- * T20: 1 GHz
- *
- * Register Field Bits Width
- * ------------------------------
- * PLLX_BASE p 22:20 3
- * PLLX_BASE n 17: 8 10
- * PLLX_BASE m 4: 0 5
- * PLLX_MISC cpcon 11: 8 4
- */
- {
- { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
- { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
- { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
- { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
- },
- /*
- * T25: 1.2 GHz
- *
- * Register Field Bits Width
- * ------------------------------
- * PLLX_BASE p 22:20 3
- * PLLX_BASE n 17: 8 10
- * PLLX_BASE m 4: 0 5
- * PLLX_MISC cpcon 11: 8 4
- */
- {
- { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
- { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
- { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
- { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
- },
- /*
- * T30: 600 MHz
- *
- * Register Field Bits Width
- * ------------------------------
- * PLLX_BASE p 22:20 3
- * PLLX_BASE n 17: 8 10
- * PLLX_BASE m 4: 0 5
- * PLLX_MISC cpcon 11: 8 4
- */
- {
- { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
- { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
- { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
- { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
- },
- /*
- * T114: 700 MHz
- *
- * Register Field Bits Width
- * ------------------------------
- * PLLX_BASE p 23:20 4
- * PLLX_BASE n 15: 8 8
- * PLLX_BASE m 7: 0 8
- */
- {
- { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
- { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
- { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
- { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
- },
-
- /*
- * T124: 700 MHz
- *
- * Register Field Bits Width
- * ------------------------------
- * PLLX_BASE p 23:20 4
- * PLLX_BASE n 15: 8 8
- * PLLX_BASE m 7: 0 8
- */
- {
- { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
- { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
- { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
- { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
- },
-};
-
-static inline void pllx_set_iddq(void)
-{
-#if defined(CONFIG_TEGRA124)
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- /* Disable IDDQ */
- reg = readl(&clkrst->crc_pllx_misc3);
- reg &= ~PLLX_IDDQ_MASK;
- writel(reg, &clkrst->crc_pllx_misc3);
- udelay(2);
- debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
- readl(&clkrst->crc_pllx_misc3));
-#endif
-}
-
-int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
- u32 divp, u32 cpcon)
-{
- int chip = tegra_get_chip();
- u32 reg;
-
- /* If PLLX is already enabled, just return */
- if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
- debug("pllx_set_rate: PLLX already enabled, returning\n");
- return 0;
- }
-
- debug(" pllx_set_rate entry\n");
-
- pllx_set_iddq();
-
- /* Set BYPASS, m, n and p to PLLX_BASE */
- reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
- reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
- writel(reg, &pll->pll_base);
-
- /* Set cpcon to PLLX_MISC */
- if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
- reg = (cpcon << PLL_CPCON_SHIFT);
- else
- reg = 0;
-
- /* Set dccon to PLLX_MISC if freq > 600MHz */
- if (divn > 600)
- reg |= (1 << PLL_DCCON_SHIFT);
- writel(reg, &pll->pll_misc);
-
- /* Disable BYPASS */
- reg = readl(&pll->pll_base);
- reg &= ~PLL_BYPASS_MASK;
- writel(reg, &pll->pll_base);
- debug("pllx_set_rate: base = 0x%08X\n", reg);
-
- /* Set lock_enable to PLLX_MISC */
- reg = readl(&pll->pll_misc);
- reg |= PLL_LOCK_ENABLE_MASK;
- writel(reg, &pll->pll_misc);
- debug("pllx_set_rate: misc = 0x%08X\n", reg);
-
- /* Enable PLLX last, once it's all configured */
- reg = readl(&pll->pll_base);
- reg |= PLL_ENABLE_MASK;
- writel(reg, &pll->pll_base);
- debug("pllx_set_rate: base final = 0x%08X\n", reg);
-
- return 0;
-}
-
-void init_pllx(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
- int soc_type, sku_info, chip_sku;
- enum clock_osc_freq osc;
- struct clk_pll_table *sel;
-
- debug("init_pllx entry\n");
-
- /* get SOC (chip) type */
- soc_type = tegra_get_chip();
- debug(" init_pllx: SoC = 0x%02X\n", soc_type);
-
- /* get SKU info */
- sku_info = tegra_get_sku_info();
- debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
-
- /* get chip SKU, combo of the above info */
- chip_sku = tegra_get_chip_sku();
- debug(" init_pllx: Chip SKU = %d\n", chip_sku);
-
- /* get osc freq */
- osc = clock_get_osc_freq();
- debug(" init_pllx: osc = %d\n", osc);
-
- /* set pllx */
- sel = &tegra_pll_x_table[chip_sku][osc];
- pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
-}
-
-void enable_cpu_clock(int enable)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 clk;
-
- /*
- * NOTE:
- * Regardless of whether the request is to enable or disable the CPU
- * clock, every processor in the CPU complex except the master (CPU 0)
- * will have it's clock stopped because the AVP only talks to the
- * master.
- */
-
- if (enable) {
- /* Initialize PLLX */
- init_pllx();
-
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
- }
-
- /*
- * Read the register containing the individual CPU clock enables and
- * always stop the clocks to CPUs > 0.
- */
- clk = readl(&clkrst->crc_clk_cpu_cmplx);
- clk |= 1 << CPU1_CLK_STP_SHIFT;
- if (get_num_cpus() == 4)
- clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
-
- /* Stop/Unstop the CPU clock */
- clk &= ~CPU0_CLK_STP_MASK;
- clk |= !enable << CPU0_CLK_STP_SHIFT;
- writel(clk, &clkrst->crc_clk_cpu_cmplx);
-
- clock_enable(PERIPH_ID_CPU);
-}
-
-static int is_cpu_powered(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
-}
-
-static void remove_cpu_io_clamps(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- /* Remove the clamps on the CPU I/O signals */
- reg = readl(&pmc->pmc_remove_clamping);
- reg |= CPU_CLMP;
- writel(reg, &pmc->pmc_remove_clamping);
-
- /* Give I/O signals time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
-}
-
-void powerup_cpu(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
- int timeout = IO_STABILIZATION_DELAY;
-
- if (!is_cpu_powered()) {
- /* Toggle the CPU power state (OFF -> ON) */
- reg = readl(&pmc->pmc_pwrgate_toggle);
- reg &= PARTID_CP;
- reg |= START_CP;
- writel(reg, &pmc->pmc_pwrgate_toggle);
-
- /* Wait for the power to come up */
- while (!is_cpu_powered()) {
- if (timeout-- == 0)
- printf("CPU failed to power up!\n");
- else
- udelay(10);
- }
-
- /*
- * Remove the I/O clamps from CPU power partition.
- * Recommended only on a Warm boot, if the CPU partition gets
- * power gated. Shouldn't cause any harm when called after a
- * cold boot according to HW, probably just redundant.
- */
- remove_cpu_io_clamps();
- }
-}
-
-void reset_A9_cpu(int reset)
-{
- /*
- * NOTE: Regardless of whether the request is to hold the CPU in reset
- * or take it out of reset, every processor in the CPU complex
- * except the master (CPU 0) will be held in reset because the
- * AVP only talks to the master. The AVP does not know that there
- * are multiple processors in the CPU complex.
- */
- int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
- int num_cpus = get_num_cpus();
- int cpu;
-
- debug("reset_a9_cpu entry\n");
- /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
- for (cpu = 1; cpu < num_cpus; cpu++)
- reset_cmplx_set_enable(cpu, mask, 1);
- reset_cmplx_set_enable(0, mask, reset);
-
- /* Enable/Disable master CPU reset */
- reset_set_enable(PERIPH_ID_CPU, reset);
-}
-
-void clock_enable_coresight(int enable)
-{
- u32 rst, src = 2;
-
- debug("clock_enable_coresight entry\n");
- clock_set_enable(PERIPH_ID_CORESIGHT, enable);
- reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
-
- if (enable) {
- /*
- * Put CoreSight on PLLP_OUT0 and divide it down as per
- * PLLP base frequency based on SoC type (T20/T30+).
- * Clock divider request would setup CSITE clock as 144MHz
- * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
- */
- src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
- clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
-
- /* Unlock the CPU CoreSight interfaces */
- rst = CORESIGHT_UNLOCK;
- writel(rst, CSITE_CPU_DBG0_LAR);
- writel(rst, CSITE_CPU_DBG1_LAR);
- if (get_num_cpus() == 4) {
- writel(rst, CSITE_CPU_DBG2_LAR);
- writel(rst, CSITE_CPU_DBG3_LAR);
- }
- }
-}
-
-void halt_avp(void)
-{
- for (;;) {
- writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
- FLOW_CTLR_HALT_COP_EVENTS);
- }
-}
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h
deleted file mode 100644
index b4ca44f..0000000
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2010-2014
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <asm/types.h>
-
-/* Stabilization delays, in usec */
-#define PLL_STABILIZATION_DELAY (300)
-#define IO_STABILIZATION_DELAY (1000)
-
-#if defined(CONFIG_TEGRA20)
-#define NVBL_PLLP_KHZ 216000
-#define CSITE_KHZ 144000
-#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
- defined(CONFIG_TEGRA124)
-#define NVBL_PLLP_KHZ 408000
-#define CSITE_KHZ 204000
-#else
-#error "Unknown Tegra chip!"
-#endif
-
-#define PLLX_ENABLED (1 << 30)
-#define CCLK_BURST_POLICY 0x20008888
-#define SUPER_CCLK_DIVIDER 0x80000000
-
-/* Calculate clock fractional divider value from ref and target frequencies */
-#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
-
-/* Calculate clock frequency value from reference and clock divider value */
-#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
-
-/* AVP/CPU ID */
-#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
-#define PG_UP_TAG_0 0x0
-
-#define CORESIGHT_UNLOCK 0xC5ACCE55;
-
-#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
-#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
-#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
-#define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
-#define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
-
-#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
-#define FLOW_MODE_STOP 2
-#define HALT_COP_EVENT_JTAG (1 << 28)
-#define HALT_COP_EVENT_IRQ_1 (1 << 11)
-#define HALT_COP_EVENT_FIQ_1 (1 << 9)
-
-#define FLOW_MODE_NONE 0
-
-#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
-
-struct clk_pll_table {
- u16 n;
- u16 m;
- u8 p;
- u8 cpcon;
-};
-
-void clock_enable_coresight(int enable);
-void enable_cpu_clock(int enable);
-void halt_avp(void) __attribute__ ((noreturn));
-void init_pllx(void);
-void powerup_cpu(void);
-void reset_A9_cpu(int reset);
-void start_cpu(u32 reset_vector);
-int tegra_get_chip(void);
-int tegra_get_sku_info(void);
-int tegra_get_chip_sku(void);
-void adjust_pllp_out_freqs(void);
-void pmic_enable_cpu_vdd(void);
diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c
deleted file mode 100644
index e0f9d5b..0000000
--- a/arch/arm/cpu/arm720t/tegra-common/spl.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * (C) Copyright 2012
- * NVIDIA Inc, <www.nvidia.com>
- *
- * Allen Martin <amartin@nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <spl.h>
-
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/apb_misc.h>
-#include <asm/arch-tegra/board.h>
-#include <asm/spl.h>
-#include "cpu.h"
-
-void spl_board_init(void)
-{
- struct apb_misc_pp_ctlr *apb_misc =
- (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
-
- /* enable JTAG */
- writel(0xC0, &apb_misc->cfg_ctl);
-
- board_init_uart_f();
-
- /* Initialize periph GPIOs */
- gpio_early_init_uart();
-
- clock_early_init();
- preloader_console_init();
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_RAM;
-}
-
-void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
-{
- debug("image entry point: 0x%X\n", spl_image->entry_point);
-
- start_cpu((u32)spl_image->entry_point);
- halt_avp();
-}
diff --git a/arch/arm/cpu/arm720t/tegra114/Makefile b/arch/arm/cpu/arm720t/tegra114/Makefile
deleted file mode 100644
index ea3e55e..0000000
--- a/arch/arm/cpu/arm720t/tegra114/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-#obj-y += cpu.o t11x.o
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
deleted file mode 100644
index 5ed3bb9..0000000
--- a/arch/arm/cpu/arm720t/tegra114/cpu.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/flow.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include "../tegra-common/cpu.h"
-
-/* Tegra114-specific CPU init code */
-static void enable_cpu_power_rail(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- debug("enable_cpu_power_rail entry\n");
-
- /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
- pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
- pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
-
- /*
- * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
- * set it for 25ms (102MHz * .025)
- */
- reg = 0x26E8F0;
- writel(reg, &pmc->pmc_cpupwrgood_timer);
-
- /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
- clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
- setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
-
- /*
- * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
- * to 408 to satisfy the requirement of having at least 16 CPU clock
- * cycles before clamp removal.
- */
-
- clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
- setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
-}
-
-static void enable_cpu_clocks(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- debug("enable_cpu_clocks entry\n");
-
- /* Wait for PLL-X to lock */
- do {
- reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
- } while ((reg & PLL_LOCK_MASK) == 0);
-
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
-
- /* Always enable the main CPU complex clocks */
- clock_enable(PERIPH_ID_CPU);
- clock_enable(PERIPH_ID_CPULP);
- clock_enable(PERIPH_ID_CPUG);
-}
-
-static void remove_cpu_resets(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- debug("remove_cpu_resets entry\n");
- /* Take the slow non-CPU partition out of reset */
- reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
- writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
-
- /* Take the fast non-CPU partition out of reset */
- reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
- writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
-
- /* Clear the SW-controlled reset of the slow cluster */
- reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
- reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
- writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
-
- /* Clear the SW-controlled reset of the fast cluster */
- reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
- reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
- reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
- reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
- reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
- writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
-}
-
-/**
- * The T114 requires some special clock initialization, including setting up
- * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
- */
-void t114_init_clocks(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
- u32 val;
-
- debug("t114_init_clocks entry\n");
-
- /* Set active CPU cluster to G */
- clrbits_le32(&flow->cluster_control, 1);
-
- writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
-
- debug("Setting up PLLX\n");
- init_pllx();
-
- val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
- writel(val, &clkrst->crc_clk_sys_rate);
-
- /* Enable clocks to required peripherals. TBD - minimize this list */
- debug("Enabling clocks\n");
-
- clock_set_enable(PERIPH_ID_CACHE2, 1);
- clock_set_enable(PERIPH_ID_GPIO, 1);
- clock_set_enable(PERIPH_ID_TMR, 1);
- clock_set_enable(PERIPH_ID_RTC, 1);
- clock_set_enable(PERIPH_ID_CPU, 1);
- clock_set_enable(PERIPH_ID_EMC, 1);
- clock_set_enable(PERIPH_ID_I2C5, 1);
- clock_set_enable(PERIPH_ID_FUSE, 1);
- clock_set_enable(PERIPH_ID_PMC, 1);
- clock_set_enable(PERIPH_ID_APBDMA, 1);
- clock_set_enable(PERIPH_ID_MEM, 1);
- clock_set_enable(PERIPH_ID_IRAMA, 1);
- clock_set_enable(PERIPH_ID_IRAMB, 1);
- clock_set_enable(PERIPH_ID_IRAMC, 1);
- clock_set_enable(PERIPH_ID_IRAMD, 1);
- clock_set_enable(PERIPH_ID_CORESIGHT, 1);
- clock_set_enable(PERIPH_ID_MSELECT, 1);
- clock_set_enable(PERIPH_ID_EMC1, 1);
- clock_set_enable(PERIPH_ID_MC1, 1);
- clock_set_enable(PERIPH_ID_DVFS, 1);
-
- /*
- * Set MSELECT clock source as PLLP (00), and ask for a clock
- * divider that would set the MSELECT clock at 102MHz for a
- * PLLP base of 408MHz.
- */
- clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
- CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
-
- /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
- clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
-
- /* Give clocks time to stabilize */
- udelay(1000);
-
- /* Take required peripherals out of reset */
- debug("Taking periphs out of reset\n");
- reset_set_enable(PERIPH_ID_CACHE2, 0);
- reset_set_enable(PERIPH_ID_GPIO, 0);
- reset_set_enable(PERIPH_ID_TMR, 0);
- reset_set_enable(PERIPH_ID_COP, 0);
- reset_set_enable(PERIPH_ID_EMC, 0);
- reset_set_enable(PERIPH_ID_I2C5, 0);
- reset_set_enable(PERIPH_ID_FUSE, 0);
- reset_set_enable(PERIPH_ID_APBDMA, 0);
- reset_set_enable(PERIPH_ID_MEM, 0);
- reset_set_enable(PERIPH_ID_CORESIGHT, 0);
- reset_set_enable(PERIPH_ID_MSELECT, 0);
- reset_set_enable(PERIPH_ID_EMC1, 0);
- reset_set_enable(PERIPH_ID_MC1, 0);
- reset_set_enable(PERIPH_ID_DVFS, 0);
-
- debug("t114_init_clocks exit\n");
-}
-
-static bool is_partition_powered(u32 partid)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- /* Get power gate status */
- reg = readl(&pmc->pmc_pwrgate_status);
- return !!(reg & (1 << partid));
-}
-
-static bool is_clamp_enabled(u32 partid)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- /* Get clamp status. */
- reg = readl(&pmc->pmc_clamp_status);
- return !!(reg & (1 << partid));
-}
-
-static void power_partition(u32 partid)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- debug("%s: part ID = %08X\n", __func__, partid);
- /* Is the partition already on? */
- if (!is_partition_powered(partid)) {
- /* No, toggle the partition power state (OFF -> ON) */
- debug("power_partition, toggling state\n");
- writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
-
- /* Wait for the power to come up */
- while (!is_partition_powered(partid))
- ;
-
- /* Wait for the clamp status to be cleared */
- while (is_clamp_enabled(partid))
- ;
-
- /* Give I/O signals time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
- }
-}
-
-void powerup_cpus(void)
-{
- debug("powerup_cpus entry\n");
-
- /* We boot to the fast cluster */
- debug("powerup_cpus entry: G cluster\n");
- /* Power up the fast cluster rail partition */
- power_partition(CRAIL);
-
- /* Power up the fast cluster non-CPU partition */
- power_partition(C0NC);
-
- /* Power up the fast cluster CPU0 partition */
- power_partition(CE0);
-}
-
-void start_cpu(u32 reset_vector)
-{
- u32 imme, inst;
-
- debug("start_cpu entry, reset_vector = %x\n", reset_vector);
-
- t114_init_clocks();
-
- /* Enable VDD_CPU */
- enable_cpu_power_rail();
-
- /* Get the CPU(s) running */
- enable_cpu_clocks();
-
- /* Enable CoreSight */
- clock_enable_coresight(1);
-
- /* Take CPU(s) out of reset */
- remove_cpu_resets();
-
- /* Set the entry point for CPU execution from reset */
-
- /*
- * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
- * See nvbug 1193357 for details.
- */
-
- /* mov r0, #lsb(reset_vector) */
- imme = reset_vector & 0xffff;
- inst = imme & 0xfff;
- inst |= ((imme >> 12) << 16);
- inst |= 0xe3000000;
- writel(inst, 0x4003fff0);
-
- /* movt r0, #msb(reset_vector) */
- imme = (reset_vector >> 16) & 0xffff;
- inst = imme & 0xfff;
- inst |= ((imme >> 12) << 16);
- inst |= 0xe3400000;
- writel(inst, 0x4003fff4);
-
- /* bx r0 */
- writel(0xe12fff10, 0x4003fff8);
-
- /* b -12 */
- imme = (u32)-20;
- inst = (imme >> 2) & 0xffffff;
- inst |= 0xea000000;
- writel(inst, 0x4003fffc);
-
- /* Write to orignal location for compatibility */
- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
- /* If the CPU(s) don't already have power, power 'em up */
- powerup_cpus();
-}
diff --git a/arch/arm/cpu/arm720t/tegra124/Makefile b/arch/arm/cpu/arm720t/tegra124/Makefile
deleted file mode 100644
index 61abf45..0000000
--- a/arch/arm/cpu/arm720t/tegra124/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2013-2014
-# NVIDIA Corporation <www.nvidia.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
deleted file mode 100644
index 6ff6aeb..0000000
--- a/arch/arm/cpu/arm720t/tegra124/cpu.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ahb.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/flow.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/ap.h>
-#include "../tegra-common/cpu.h"
-
-/* Tegra124-specific CPU init code */
-
-static void enable_cpu_power_rail(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- debug("enable_cpu_power_rail entry\n");
-
- /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
- pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
- pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
-
- pmic_enable_cpu_vdd();
-
- /*
- * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
- * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
- */
- writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
-
- /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
- clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
- setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
-}
-
-static void enable_cpu_clocks(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- debug("enable_cpu_clocks entry\n");
-
- /* Wait for PLL-X to lock */
- do {
- reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
- debug("%s: PLLX base = 0x%08X\n", __func__, reg);
- } while ((reg & PLL_LOCK_MASK) == 0);
-
- debug("%s: PLLX locked, delay for stable clocks\n", __func__);
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
-
- debug("%s: Enabling clock to all CPUs\n", __func__);
- /* Enable the clock to all CPUs */
- reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
- CLR_CPU0_CLK_STP;
- writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
-
- debug("%s: Enabling main CPU complex clocks\n", __func__);
- /* Always enable the main CPU complex clocks */
- clock_enable(PERIPH_ID_CPU);
- clock_enable(PERIPH_ID_CPULP);
- clock_enable(PERIPH_ID_CPUG);
-
- debug("%s: Done\n", __func__);
-}
-
-static void remove_cpu_resets(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- debug("remove_cpu_resets entry\n");
-
- /* Take the slow and fast partitions out of reset */
- reg = CLR_NONCPURESET;
- writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
- writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
-
- /* Clear the SW-controlled reset of the slow cluster */
- reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
- CLR_L2RESET | CLR_PRESETDBG;
- writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
-
- /* Clear the SW-controlled reset of the fast cluster */
- reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
- CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
- CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
- CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
- CLR_L2RESET | CLR_PRESETDBG;
- writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
-}
-
-/**
- * The Tegra124 requires some special clock initialization, including setting up
- * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
- */
-void tegra124_init_clocks(void)
-{
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 val;
-
- debug("tegra124_init_clocks entry\n");
-
- /* Set active CPU cluster to G */
- clrbits_le32(&flow->cluster_control, 1);
-
- /* Change the oscillator drive strength */
- val = readl(&clkrst->crc_osc_ctrl);
- val &= ~OSC_XOFS_MASK;
- val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
- writel(val, &clkrst->crc_osc_ctrl);
-
- /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
- val = readl(&pmc->pmc_osc_edpd_over);
- val &= ~PMC_XOFS_MASK;
- val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
- writel(val, &pmc->pmc_osc_edpd_over);
-
- /* Set HOLD_CKE_LOW_EN to 1 */
- setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
-
- debug("Setting up PLLX\n");
- init_pllx();
-
- val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
- writel(val, &clkrst->crc_clk_sys_rate);
-
- /* Enable clocks to required peripherals. TBD - minimize this list */
- debug("Enabling clocks\n");
-
- clock_set_enable(PERIPH_ID_CACHE2, 1);
- clock_set_enable(PERIPH_ID_GPIO, 1);
- clock_set_enable(PERIPH_ID_TMR, 1);
- clock_set_enable(PERIPH_ID_CPU, 1);
- clock_set_enable(PERIPH_ID_EMC, 1);
- clock_set_enable(PERIPH_ID_I2C5, 1);
- clock_set_enable(PERIPH_ID_APBDMA, 1);
- clock_set_enable(PERIPH_ID_MEM, 1);
- clock_set_enable(PERIPH_ID_CORESIGHT, 1);
- clock_set_enable(PERIPH_ID_MSELECT, 1);
- clock_set_enable(PERIPH_ID_DVFS, 1);
-
- /*
- * Set MSELECT clock source as PLLP (00), and ask for a clock
- * divider that would set the MSELECT clock at 102MHz for a
- * PLLP base of 408MHz.
- */
- clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
- CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
-
- /* Give clock time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
-
- /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
- clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
-
- /* Give clock time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
-
- /* Take required peripherals out of reset */
- debug("Taking periphs out of reset\n");
- reset_set_enable(PERIPH_ID_CACHE2, 0);
- reset_set_enable(PERIPH_ID_GPIO, 0);
- reset_set_enable(PERIPH_ID_TMR, 0);
- reset_set_enable(PERIPH_ID_COP, 0);
- reset_set_enable(PERIPH_ID_EMC, 0);
- reset_set_enable(PERIPH_ID_I2C5, 0);
- reset_set_enable(PERIPH_ID_APBDMA, 0);
- reset_set_enable(PERIPH_ID_MEM, 0);
- reset_set_enable(PERIPH_ID_CORESIGHT, 0);
- reset_set_enable(PERIPH_ID_MSELECT, 0);
- reset_set_enable(PERIPH_ID_DVFS, 0);
-
- debug("tegra124_init_clocks exit\n");
-}
-
-static bool is_partition_powered(u32 partid)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- /* Get power gate status */
- reg = readl(&pmc->pmc_pwrgate_status);
- return !!(reg & (1 << partid));
-}
-
-static void power_partition(u32 partid)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- debug("%s: part ID = %08X\n", __func__, partid);
- /* Is the partition already on? */
- if (!is_partition_powered(partid)) {
- /* No, toggle the partition power state (OFF -> ON) */
- debug("power_partition, toggling state\n");
- writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
-
- /* Wait for the power to come up */
- while (!is_partition_powered(partid))
- ;
-
- /* Give I/O signals time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
- }
-}
-
-void powerup_cpus(void)
-{
- debug("powerup_cpus entry\n");
-
- /* We boot to the fast cluster */
- debug("powerup_cpus entry: G cluster\n");
-
- /* Power up the fast cluster rail partition */
- debug("powerup_cpus: CRAIL\n");
- power_partition(CRAIL);
-
- /* Power up the fast cluster non-CPU partition */
- debug("powerup_cpus: C0NC\n");
- power_partition(C0NC);
-
- /* Power up the fast cluster CPU0 partition */
- debug("powerup_cpus: CE0\n");
- power_partition(CE0);
-
- debug("powerup_cpus: done\n");
-}
-
-void start_cpu(u32 reset_vector)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- debug("start_cpu entry, reset_vector = %x\n", reset_vector);
-
- tegra124_init_clocks();
-
- /* Set power-gating timer multiplier */
- writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
- &pmc->pmc_pwrgate_timer_mult);
-
- enable_cpu_power_rail();
- enable_cpu_clocks();
- clock_enable_coresight(1);
- remove_cpu_resets();
- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
- powerup_cpus();
- debug("start_cpu exit, should continue @ reset_vector\n");
-}
diff --git a/arch/arm/cpu/arm720t/tegra20/Makefile b/arch/arm/cpu/arm720t/tegra20/Makefile
deleted file mode 100644
index 12243fa..0000000
--- a/arch/arm/cpu/arm720t/tegra20/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.c b/arch/arm/cpu/arm720t/tegra20/cpu.c
deleted file mode 100644
index 2533899..0000000
--- a/arch/arm/cpu/arm720t/tegra20/cpu.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/pmc.h>
-#include "../tegra-common/cpu.h"
-
-static void enable_cpu_power_rail(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- reg = readl(&pmc->pmc_cntrl);
- reg |= CPUPWRREQ_OE;
- writel(reg, &pmc->pmc_cntrl);
-
- /*
- * The TI PMU65861C needs a 3.75ms delay between enabling
- * the power rail and enabling the CPU clock. This delay
- * between SM1EN and SM1 is for switching time + the ramp
- * up of the voltage to the CPU (VDD_CPU from PMU).
- */
- udelay(3750);
-}
-
-void start_cpu(u32 reset_vector)
-{
- /* Enable VDD_CPU */
- enable_cpu_power_rail();
-
- /* Hold the CPUs in reset */
- reset_A9_cpu(1);
-
- /* Disable the CPU clock */
- enable_cpu_clock(0);
-
- /* Enable CoreSight */
- clock_enable_coresight(1);
-
- /*
- * Set the entry point for CPU execution from reset,
- * if it's a non-zero value.
- */
- if (reset_vector)
- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
- /* Enable the CPU clock */
- enable_cpu_clock(1);
-
- /* If the CPU doesn't already have power, power it up */
- powerup_cpu();
-
- /* Take the CPU out of reset */
- reset_A9_cpu(0);
-}
diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/arm720t/tegra30/Makefile
deleted file mode 100644
index 6ff4c55..0000000
--- a/arch/arm/cpu/arm720t/tegra30/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-obj-y += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
deleted file mode 100644
index 9003902..0000000
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/flow.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/tegra_i2c.h>
-#include "../tegra-common/cpu.h"
-
-/* Tegra30-specific CPU init code */
-void tegra_i2c_ll_write_addr(uint addr, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
- writel(addr, &reg->cmd_addr0);
- writel(config, &reg->cnfg);
-}
-
-void tegra_i2c_ll_write_data(uint data, uint config)
-{
- struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
-
- writel(data, &reg->cmd_data1);
- writel(config, &reg->cnfg);
-}
-
-#define TPS62366A_I2C_ADDR 0xC0
-#define TPS62366A_SET1_REG 0x01
-#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
-
-#define TPS62361B_I2C_ADDR 0xC0
-#define TPS62361B_SET3_REG 0x03
-#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
-
-#define TPS65911_I2C_ADDR 0x5A
-#define TPS65911_VDDCTRL_OP_REG 0x28
-#define TPS65911_VDDCTRL_SR_REG 0x27
-#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
-#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
-#define I2C_SEND_2_BYTES 0x0A02
-
-static void enable_cpu_power_rail(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- debug("enable_cpu_power_rail entry\n");
- reg = readl(&pmc->pmc_cntrl);
- reg |= CPUPWRREQ_OE;
- writel(reg, &pmc->pmc_cntrl);
-
- /* Set VDD_CORE to 1.200V. */
-#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
- tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
-#endif
-#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
- tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
-#endif
- udelay(1000);
-
- /*
- * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
- * First set VDD to 1.0125V, then enable the VDD regulator.
- */
- tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
- tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
- udelay(1000);
- tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
- udelay(10 * 1000);
-}
-
-/**
- * The T30 requires some special clock initialization, including setting up
- * the dvc i2c, turning on mselect and selecting the G CPU cluster
- */
-void t30_init_clocks(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
- u32 val;
-
- debug("t30_init_clocks entry\n");
- /* Set active CPU cluster to G */
- clrbits_le32(flow->cluster_control, 1 << 0);
-
- writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
-
- val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
- (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
- (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
- (0 << CLK_SYS_RATE_APB_RATE_SHIFT);
- writel(val, &clkrst->crc_clk_sys_rate);
-
- /* Put i2c, mselect in reset and enable clocks */
- reset_set_enable(PERIPH_ID_DVC_I2C, 1);
- clock_set_enable(PERIPH_ID_DVC_I2C, 1);
- reset_set_enable(PERIPH_ID_MSELECT, 1);
- clock_set_enable(PERIPH_ID_MSELECT, 1);
-
- /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
- clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
-
- /*
- * Our high-level clock routines are not available prior to
- * relocation. We use the low-level functions which require a
- * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
- */
- clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
-
- /*
- * Give clocks time to stabilize, then take i2c and mselect out of
- * reset
- */
- udelay(1000);
- reset_set_enable(PERIPH_ID_DVC_I2C, 0);
- reset_set_enable(PERIPH_ID_MSELECT, 0);
-}
-
-static void set_cpu_running(int run)
-{
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
-
- debug("set_cpu_running entry, run = %d\n", run);
- writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
-}
-
-void start_cpu(u32 reset_vector)
-{
- debug("start_cpu entry, reset_vector = %x\n", reset_vector);
- t30_init_clocks();
-
- /* Enable VDD_CPU */
- enable_cpu_power_rail();
-
- set_cpu_running(0);
-
- /* Hold the CPUs in reset */
- reset_A9_cpu(1);
-
- /* Disable the CPU clock */
- enable_cpu_clock(0);
-
- /* Enable CoreSight */
- clock_enable_coresight(1);
-
- /*
- * Set the entry point for CPU execution from reset,
- * if it's a non-zero value.
- */
- if (reset_vector)
- writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
- /* Enable the CPU clock */
- enable_cpu_clock(1);
-
- /* If the CPU doesn't already have power, power it up */
- powerup_cpu();
-
- /* Take the CPU out of reset */
- reset_A9_cpu(0);
-
- set_cpu_running(1);
-}
diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile
index a72e5de..6582938 100644
--- a/arch/arm/cpu/arm920t/Makefile
+++ b/arch/arm/cpu/arm920t/Makefile
@@ -10,9 +10,6 @@ extra-y = start.o
obj-y += cpu.o
obj-$(CONFIG_USE_IRQ) += interrupts.o
-obj-$(if $(filter a320,$(SOC)),y) += a320/
-obj-$(CONFIG_AT91FAMILY) += at91/
obj-$(CONFIG_EP93XX) += ep93xx/
obj-$(CONFIG_IMX) += imx/
-obj-$(CONFIG_KS8695) += ks8695/
obj-$(CONFIG_S3C24X0) += s3c24x0/
diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile
deleted file mode 100644
index bbdab58..0000000
--- a/arch/arm/cpu/arm920t/a320/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += reset.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/arm920t/a320/reset.S b/arch/arm/cpu/arm920t/a320/reset.S
deleted file mode 100644
index 81f9dc9..0000000
--- a/arch/arm/cpu/arm920t/a320/reset.S
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-.global reset_cpu
-reset_cpu:
- b reset_cpu
diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c
deleted file mode 100644
index 1ac5b60..0000000
--- a/arch/arm/cpu/arm920t/a320/timer.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <div64.h>
-#include <asm/io.h>
-#include <faraday/ftpmu010.h>
-#include <faraday/fttmr010.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define TIMER_CLOCK 32768
-#define TIMER_LOAD_VAL 0xffffffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, gd->arch.timer_rate_hz);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= gd->arch.timer_rate_hz;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-int timer_init(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
- unsigned int cr;
-
- debug("%s()\n", __func__);
-
- /* disable timers */
- writel(0, &tmr->cr);
-
- /* use 32768Hz oscillator for RTC, WDT, TIMER */
- ftpmu010_32768osc_enable();
-
- /* setup timer */
- writel(TIMER_LOAD_VAL, &tmr->timer3_load);
- writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
- writel(0, &tmr->timer3_match1);
- writel(0, &tmr->timer3_match2);
-
- /* we don't want timer to issue interrupts */
- writel(FTTMR010_TM3_MATCH1 |
- FTTMR010_TM3_MATCH2 |
- FTTMR010_TM3_OVERFLOW,
- &tmr->interrupt_mask);
-
- cr = readl(&tmr->cr);
- cr |= FTTMR010_TM3_CLOCK; /* use external clock */
- cr |= FTTMR010_TM3_ENABLE;
- writel(cr, &tmr->cr);
-
- gd->arch.timer_rate_hz = TIMER_CLOCK;
- gd->arch.tbu = gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
- ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long start;
- ulong tmo;
-
- start = get_ticks(); /* get current timestamp */
- tmo = usec_to_tick(usec); /* convert usecs to ticks */
- while ((get_ticks() - start) < tmo)
- ; /* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
- return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gd->arch.timer_rate_hz;
-}
diff --git a/arch/arm/cpu/arm920t/at91/Makefile b/arch/arm/cpu/arm920t/at91/Makefile
deleted file mode 100644
index 561b4b4..0000000
--- a/arch/arm/cpu/arm920t/at91/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += lowlevel_init.o
-obj-y += reset.o
-obj-y += timer.o
-obj-y += clock.o
-obj-y += cpu.o
-obj-y += at91rm9200_devices.o
diff --git a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c b/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c
deleted file mode 100644
index fc54327..0000000
--- a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c]
- *
- * (C) Copyright 2011
- * Andreas Bießmann <andreas.devel@googlemail.com>
- *
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, PUP); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 20, PUP); /* RXD1 */
- at91_set_a_periph(AT91_PIO_PORTB, 21, 1); /* TXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* RXD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 23, 1); /* TXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTA, 30, PUP); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTA, 31, 1); /* DTXD */
- /* writing SYS to PCER has no effect on AT91RM9200 */
-}
diff --git a/arch/arm/cpu/arm920t/at91/clock.c b/arch/arm/cpu/arm920t/at91/clock.c
deleted file mode 100644
index 2813bf7..0000000
--- a/arch/arm/cpu/arm920t/at91/clock.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
- *
- * Copyright (C) 2011 Andreas Bießmann
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned long at91_css_to_rate(unsigned long css)
-{
- switch (css) {
- case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
- case AT91_PMC_MCKR_CSS_MAIN:
- return gd->arch.main_clk_rate_hz;
- case AT91_PMC_MCKR_CSS_PLLA:
- return gd->arch.plla_rate_hz;
- case AT91_PMC_MCKR_CSS_PLLB:
- return gd->arch.pllb_rate_hz;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_USB_ATMEL
-static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
- unsigned i, div = 0, mul = 0, diff = 1 << 30;
- unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
- /* PLL output max 240 MHz (or 180 MHz per errata) */
- if (out_freq > 240000000)
- goto fail;
-
- for (i = 1; i < 256; i++) {
- int diff1;
- unsigned input, mul1;
-
- /*
- * PLL input between 1MHz and 32MHz per spec, but lower
- * frequences seem necessary in some cases so allow 100K.
- * Warning: some newer products need 2MHz min.
- */
- input = main_freq / i;
- if (input < 100000)
- continue;
- if (input > 32000000)
- continue;
-
- mul1 = out_freq / input;
- if (mul1 > 2048)
- continue;
- if (mul1 < 2)
- goto fail;
-
- diff1 = out_freq - input * mul1;
- if (diff1 < 0)
- diff1 = -diff1;
- if (diff > diff1) {
- diff = diff1;
- div = i;
- mul = mul1;
- if (diff == 0)
- break;
- }
- }
- if (i == 256 && diff > (out_freq >> 5))
- goto fail;
- return ret | ((mul - 1) << 16) | div;
-fail:
- return 0;
-}
-#endif
-
-static u32 at91_pll_rate(u32 freq, u32 reg)
-{
- unsigned mul, div;
-
- div = reg & 0xff;
- mul = (reg >> 16) & 0x7ff;
- if (div && mul) {
- freq /= div;
- freq *= mul + 1;
- } else
- freq = 0;
-
- return freq;
-}
-
-int at91_clock_init(unsigned long main_clock)
-{
- unsigned freq, mckr;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
- unsigned tmp;
- /*
- * When the bootloader initialized the main oscillator correctly,
- * there's no problem using the cycle counter. But if it didn't,
- * or when using oscillator bypass mode, we must be told the speed
- * of the main clock.
- */
- if (!main_clock) {
- do {
- tmp = readl(&pmc->mcfr);
- } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
- tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
- }
-#endif
- gd->arch.main_clk_rate_hz = main_clock;
-
- /* report if PLLA is more than mildly overclocked */
- gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
-
-#ifdef CONFIG_USB_ATMEL
- /*
- * USB clock init: choose 48 MHz PLLB value,
- * disable 48MHz clock during usb peripheral suspend.
- *
- * REVISIT: assumes MCK doesn't derive from PLLB!
- */
- gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
- AT91_PMC_PLLBR_USBDIV_2;
- gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
- gd->arch.at91_pllb_usb_init);
-#endif
-
- /*
- * MCK and CPU derive from one of those primary clocks.
- * For now, assume this parentage won't change.
- */
- mckr = readl(&pmc->mckr);
- gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
- freq = gd->arch.mck_rate_hz;
-
- freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
- /* mdiv */
- gd->arch.mck_rate_hz = freq /
- (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
- gd->arch.cpu_clk_rate_hz = freq;
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm920t/at91/cpu.c b/arch/arm/cpu/arm920t/at91/cpu.c
deleted file mode 100644
index b0f411b..0000000
--- a/arch/arm/cpu/arm920t/at91/cpu.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * [origin: arch/arm/cpu/arm926ejs/at91/cpu.c]
- *
- * (C) Copyright 2011
- * Andreas Bießmann, andreas.devel@googlemail.com
- * (C) Copyright 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- * (C) Copyright 2009
- * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clk.h>
-
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
-#endif
-
-int arch_cpu_init(void)
-{
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-}
diff --git a/arch/arm/cpu/arm920t/at91/lowlevel_init.S b/arch/arm/cpu/arm920t/at91/lowlevel_init.S
deleted file mode 100644
index d2934a3..0000000
--- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_mc.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-
-#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
-
-_MTEXT_BASE:
-#undef START_FROM_MEM
-#ifdef START_FROM_MEM
- .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
-#else
- .word CONFIG_SYS_TEXT_BASE
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
- ldr r1, =AT91_ASM_PMC_MOR
- /* Main oscillator Enable register */
-#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
- ldr r0, =0x0000FF01 /* Enable main oscillator */
-#else
- ldr r0, =0x0000FF00 /* Disable main oscillator */
-#endif
- str r0, [r1] /*AT91C_CKGR_MOR] */
- /* Add loop to compensate Main Oscillator startup time */
- ldr r0, =0x00000010
-LoopOsc:
- subs r0, r0, #1
- bhi LoopOsc
-
- /* memory control configuration */
- /* this isn't very elegant, but what the heck */
- ldr r0, =SMRDATA
- ldr r1, _MTEXT_BASE
- sub r0, r0, r1
- ldr r2, =SMRDATAE
- sub r2, r2, r1
-pllloop:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne pllloop
- /* delay - this is all done by guess */
- ldr r0, =0x00010000
- /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
-lock:
- subs r0, r0, #1
- bhi lock
- ldr r0, =SMRDATA1
- ldr r1, _MTEXT_BASE
- sub r0, r0, r1
- ldr r2, =SMRDATA1E
- sub r2, r2, r1
-sdinit:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne sdinit
-
- /* switch from FastBus to Asynchronous clock mode */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #ARM920T_CONTROL
- mcr p15, 0, r0, c1, c0, 0
-
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-
-SMRDATA:
- .word AT91_ASM_MC_EBI_CFG
- .word CONFIG_SYS_EBI_CFGR_VAL
- .word AT91_ASM_MC_SMC_CSR0
- .word CONFIG_SYS_SMC_CSR0_VAL
- .word AT91_ASM_PMC_PLLAR
- .word CONFIG_SYS_PLLAR_VAL
- .word AT91_ASM_PMC_PLLBR
- .word CONFIG_SYS_PLLBR_VAL
- .word AT91_ASM_PMC_MCKR
- .word CONFIG_SYS_MCKR_VAL
-SMRDATAE:
- /* here there's a delay */
-SMRDATA1:
- .word AT91_ASM_PIOC_ASR
- .word CONFIG_SYS_PIOC_ASR_VAL
- .word AT91_ASM_PIOC_BSR
- .word CONFIG_SYS_PIOC_BSR_VAL
- .word AT91_ASM_PIOC_PDR
- .word CONFIG_SYS_PIOC_PDR_VAL
- .word AT91_ASM_MC_EBI_CSA
- .word CONFIG_SYS_EBI_CSA_VAL
- .word AT91_ASM_MC_SDRAMC_CR
- .word CONFIG_SYS_SDRC_CR_VAL
- .word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL1
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL2
- .word CONFIG_SYS_SDRAM1
- .word CONFIG_SYS_SDRAM_VAL
- .word AT91_ASM_MC_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
- .word AT91_ASM_MC_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL3
- .word CONFIG_SYS_SDRAM
- .word CONFIG_SYS_SDRAM_VAL
-SMRDATA1E:
- /* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/at91/reset.c b/arch/arm/cpu/arm920t/at91/reset.c
deleted file mode 100644
index d47777a..0000000
--- a/arch/arm/cpu/arm920t/at91/reset.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_st.h>
-
-void __attribute__((weak)) board_reset(void)
-{
- /* true empty function for defining weak symbol */
-}
-
-void reset_cpu(ulong ignored)
-{
- at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST;
-
- board_reset();
-
- /* Reset the cpu by setting up the watchdog timer */
- writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2),
- &st->wdmr);
- writel(AT91_ST_CR_WDRST, &st->cr);
- /* and let it timeout */
- while (1)
- ;
- /* Never reached */
-}
diff --git a/arch/arm/cpu/arm920t/at91/timer.c b/arch/arm/cpu/arm920t/at91/timer.c
deleted file mode 100644
index 6aa2994..0000000
--- a/arch/arm/cpu/arm920t/at91/timer.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_tc.h>
-#include <asm/arch/at91_pmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
-
-int timer_init(void)
-{
- at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- /* enables TC1.0 clock */
- writel(1 << ATMEL_ID_TC0, &pmc->pcer); /* enable clock */
-
- writel(0, &tc->bcr);
- writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
- AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr);
-
- writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
- /* set to MCLK/2 and restart the timer
- when the value in TC_RC is reached */
- writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
-
- writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
- writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
-
- writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
- gd->arch.lastinc = 0;
- gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
- udelay_masked(usec);
-}
-
-ulong get_timer_raw(void)
-{
- at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
- u32 now;
-
- now = readl(&tc->tc[0].cv) & 0x0000ffff;
-
- if (now >= gd->arch.lastinc) {
- /* normal mode */
- gd->arch.tbl += now - gd->arch.lastinc;
- } else {
- /* we have an overflow ... */
- gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
- }
- gd->arch.lastinc = now;
-
- return gd->arch.tbl;
-}
-
-ulong get_timer_masked(void)
-{
- return get_timer_raw()/TIMER_LOAD_VAL;
-}
-
-void udelay_masked(unsigned long usec)
-{
- u32 tmo;
- u32 endtime;
- signed long diff;
-
- tmo = CONFIG_SYS_HZ_CLOCK / 1000;
- tmo *= usec;
- tmo /= 1000;
-
- endtime = get_timer_raw() + tmo;
-
- do {
- u32 now = get_timer_raw();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile
deleted file mode 100644
index 400aa89..0000000
--- a/arch/arm/cpu/arm920t/ks8695/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = lowlevel_init.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
deleted file mode 100644
index a2a07f2..0000000
--- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * lowlevel_init.S - basic hardware initialization for the KS8695 CPU
- *
- * Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/platform.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-
-/*
- *************************************************************************
- *
- * Handy dandy macros
- *
- *************************************************************************
- */
-
-/* Delay a bit */
-.macro DELAY_FOR cycles, reg0
- ldr \reg0, =\cycles
- subs \reg0, \reg0, #1
- subne pc, pc, #0xc
-.endm
-
-/*
- *************************************************************************
- *
- * Some local storage.
- *
- *************************************************************************
- */
-
-/* Should we boot with an interactive console or not */
-.globl serial_console
-
-/*
- *************************************************************************
- *
- * Raw hardware initialization code. The important thing is to get
- * SDRAM setup and running. We do some other basic things here too,
- * like getting the PLL set for high speed, and init the LEDs.
- *
- *************************************************************************
- */
-
-.globl lowlevel_init
-lowlevel_init:
-
-#if DEBUG
- /*
- * enable UART for early debug trace
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
- mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
- str r2, [r1]
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
- mov r2, #KS8695_UART_LINEC_WLEN8
- str r2, [r1] /* 8 data bits, no parity, 1 stop */
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
- mov r2, #0x41
- str r2, [r1] /* write 'A' */
-#endif
-#if DEBUG
- ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
- mov r2, #0x42
- str r2, [r1]
-#endif
-
- /*
- * remap the memory and flash regions. we want to end up with
- * ram from address 0, and flash at 32MB.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
- ldr r2, =0xbfc00040
- str r2, [r1] /* large flash map */
- ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
-highflash:
- ldr r2, =0x8fe00040
- str r2, [r1] /* remap flash range */
-
- /*
- * remap the second select region to the 4MB immediately after
- * the first region. This way if you have a larger flash (say 8Mb)
- * then you can have it all mapped nicely. Has no effect if you
- * only have a 4Mb or smaller flash.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
- ldr r2, =0x9fe40040
- str r2, [r1] /* remap flash2 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
- ldr r2, =0x30000005
- str r2, [r1] /* enable both flash selects */
-
-#ifdef CONFIG_CM41xx
- /*
- * map the second flash chip, using the external IO lines.
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
- ldr r2, =0xafe80b6d
- str r2, [r1] /* remap io0 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
- ldr r2, =0xbfec0b6d
- str r2, [r1] /* remap io1 region, contiguous */
- ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
- ldr r2, =0x30050005
- str r2, [r1] /* enable second flash */
-#endif
-
- /*
- * before relocating, we have to setup RAM timing
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
-#if (PHYS_SDRAM_1_SIZE == 0x02000000)
- ldr r2, =0x7fc0000e /* 32MB */
-#else
- ldr r2, =0x3fc0000e /* 16MB */
-#endif
- str r2, [r1] /* configure sdram bank0 setup */
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
- mov r2, #0
- str r2, [r1] /* configure sdram bank1 setup */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
- ldr r2, =0x0000000a
- str r2, [r1] /* set RAS/CAS timing */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
- ldr r2, =0x00030000
- str r2, [r1] /* send NOP command */
- DELAY_FOR 0x100, r0
- ldr r2, =0x00010000
- str r2, [r1] /* send PRECHARGE-ALL */
- DELAY_FOR 0x100, r0
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
- ldr r2, =0x00000020
- str r2, [r1] /* set for fast refresh */
- DELAY_FOR 0x100, r0
- ldr r2, =0x00000190
- str r2, [r1] /* set normal refresh timing */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
- ldr r2, =0x00020033
- str r2, [r1] /* send mode command */
- DELAY_FOR 0x100, r0
- ldr r2, =0x01f00000
- str r2, [r1] /* enable sdram fifos */
-
- /*
- * set pll to top speed
- */
- ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
- mov r2, #0
- str r2, [r1] /* set pll clock to 166MHz */
-
- ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
- ldr r2, [r1] /* Get switch ctrl0 register */
- and r2, r2, #0x0fc00000 /* Mask out LED control bits */
- orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
- str r2, [r1]
-
-#ifdef CONFIG_CM4008
- ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
- ldr r2, =0x0000fe30
- str r2, [r1] /* enable LED's as outputs */
- ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
- ldr r2, =0x0000fe20
- str r2, [r1] /* turn on power LED */
-#endif
-#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
- ldr r2, [r1] /* get current GPIO input data */
- tst r2, #0x8 /* check if "erase" depressed */
- beq nobutton
- mov r2, #0 /* be quiet on boot, no console */
- ldr r1, =serial_console
- str r2, [r1]
-nobutton:
-#endif
-
- add lr, lr, #0x02000000 /* flash is now mapped high */
- add ip, ip, #0x02000000 /* this is a hack */
- mov pc, lr /* all done, return */
-
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
diff --git a/arch/arm/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c
deleted file mode 100644
index 23db557..0000000
--- a/arch/arm/cpu/arm920t/ks8695/timer.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-
-/*
- * Initial timer set constants. Nothing complicated, just set for a 1ms
- * tick.
- */
-#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1)
-#define TIMER_COUNT (TIMER_INTERVAL / 2)
-#define TIMER_PULSE TIMER_COUNT
-
-/*
- * Handy KS8695 register access functions.
- */
-#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a)))
-#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
-
-ulong timer_ticks;
-
-int timer_init (void)
-{
- /* Set the hadware timer for 1ms */
- ks8695_write(KS8695_TIMER1, TIMER_COUNT);
- ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
- ks8695_write(KS8695_TIMER_CTRL, 0x2);
- timer_ticks = 0;
-
- return 0;
-}
-
-ulong get_timer_masked(void)
-{
- /* Check for timer wrap */
- if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
- /* Clear interrupt condition */
- ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
- timer_ticks++;
- }
- return timer_ticks;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_timer_masked() - base);
-}
-
-void __udelay(ulong usec)
-{
- ulong start = get_timer_masked();
- ulong end;
-
- /* Only 1ms resolution :-( */
- end = usec / 1000;
- while (get_timer(start) < end)
- ;
-}
-
-void reset_cpu (ulong ignored)
-{
- ulong tc;
-
- /* Set timer0 to watchdog, and let it timeout */
- tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
- ks8695_write(KS8695_TIMER_CTRL, tc);
- ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
- ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
-
- /* Should only wait here till watchdog resets */
- for (;;)
- ;
-}
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index adcea9f..63fa159 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -15,16 +15,8 @@ endif
endif
obj-$(CONFIG_ARMADA100) += armada100/
-obj-$(CONFIG_AT91FAMILY) += at91/
-obj-$(CONFIG_ARCH_DAVINCI) += davinci/
-obj-$(CONFIG_KIRKWOOD) += kirkwood/
obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
-obj-$(CONFIG_MB86R0x) += mb86r0x/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
-obj-$(CONFIG_ARCH_NOMADIK) += nomadik/
-obj-$(CONFIG_ORION5X) += orion5x/
-obj-$(CONFIG_PANTHEON) += pantheon/
obj-$(if $(filter spear,$(SOC)),y) += spear/
-obj-$(CONFIG_ARCH_VERSATILE) += versatile/
diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile
deleted file mode 100644
index ddc323f..0000000
--- a/arch/arm/cpu/arm926ejs/at91/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o
-obj-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o
-obj-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o
-obj-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o
-obj-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o
-obj-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o
-obj-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o
-obj-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
-obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
-obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o
-obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
-obj-$(CONFIG_AT91_EFLASH) += eflash.o
-obj-$(CONFIG_AT91_LED) += led.o
-obj-y += clock.o
-obj-y += cpu.o
-obj-y += reset.o
-obj-y += timer.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y += lowlevel_init.o
-endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
deleted file mode 100644
index efb53d6..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <asm/io.h>
-#include <asm/arch/at91sam9260_matrix.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91sam9_sdramc.h>
-#include <asm/arch/gpio.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
- }
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTC, 3, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
- }
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- /* Enable EMAC clock */
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
-
- at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* EMDC */
-
-#ifndef CONFIG_RMII
- at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ECRS */
- at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECOL */
- at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */
- at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */
- at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */
-#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
- /*
- * use PA10, PA11 for ETX2, ETX3.
- * PA23 and PA24 are for TWI EEPROM
- */
- at91_set_b_periph(AT91_PIO_PORTA, 10, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTA, 11, 0); /* ETX3 */
-#else
- at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */
-#if defined(CONFIG_AT91SAM9G20)
- /* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
- at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
- at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
-#endif
-#endif
- at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */
-#endif
-}
-#endif
-
-#if defined(CONFIG_GENERIC_ATMEL_MCI)
-void at91_mci_hw_init(void)
-{
- /* Enable mci clock */
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- writel(1 << ATMEL_ID_MCI, &pmc->pcer);
-
- at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */
-#if defined(CONFIG_ATMEL_MCI_PORTB)
- at91_set_b_periph(AT91_PIO_PORTA, 1, 1); /* MCCDB */
- at91_set_b_periph(AT91_PIO_PORTA, 0, 1); /* MCDB0 */
- at91_set_b_periph(AT91_PIO_PORTA, 5, 1); /* MCDB1 */
- at91_set_b_periph(AT91_PIO_PORTA, 4, 1); /* MCDB2 */
- at91_set_b_periph(AT91_PIO_PORTA, 3, 1); /* MCDB3 */
-#else
- at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* MCCDA */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* MCDA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 9, 1); /* MCDA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* MCDA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* MCDA3 */
-#endif
-}
-#endif
-
-void at91_sdram_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTC, 16, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 17, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 18, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 19, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 20, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 21, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 22, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 23, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 24, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 25, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 26, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 27, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 28, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 29, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 30, 0);
- at91_set_a_periph(AT91_PIO_PORTC, 31, 0);
-}
-
-/* Platform data for the GPIOs */
-static const struct at91_port_platdata at91sam9260_plat[] = {
- { ATMEL_BASE_PIOA, "PA" },
- { ATMEL_BASE_PIOB, "PB" },
- { ATMEL_BASE_PIOC, "PC" },
-};
-
-U_BOOT_DEVICES(at91sam9260_gpios) = {
- { "gpio_at91", &at91sam9260_plat[0] },
- { "gpio_at91", &at91sam9260_plat[1] },
- { "gpio_at91", &at91sam9260_plat[2] },
-};
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
deleted file mode 100644
index a445c75..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_a_periph(AT91_PIO_PORTA, 4, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_a_periph(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_a_periph(AT91_PIO_PORTA, 6, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTA, 6, 1);
- }
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 30, PUP); /* SPI1_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 31, PUP); /* SPI1_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 29, PUP); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTA, 24, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTA, 25, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_a_periph(AT91_PIO_PORTA, 26, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 28, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTA, 24, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTA, 25, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTA, 26, 1);
- }
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
deleted file mode 100644
index 6b51d5f..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2009-2011
- * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
- * esd electronic system design gmbh <www.esd.eu>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTD, 1, PUP); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTD, 3, PUP); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 30, PUP); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
- at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
- at91_set_b_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
- }
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 12, PUP); /* SPI1_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 13, PUP); /* SPI1_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
- }
-}
-#endif
-
-#if defined(CONFIG_GENERIC_ATMEL_MCI)
-void at91_mci_hw_init(void)
-{
- /* Enable mci clock */
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
-
- at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */
-
-#if defined(CONFIG_ATMEL_MCI_PORTB)
- at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */
- at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */
- at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */
- at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */
- at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */
-#else
- at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */
- at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */
-#endif
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTE, 21, 0); /* ETXCK_EREFCK */
- at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTE, 25, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTE, 26, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTE, 27, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTE, 28, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTE, 23, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTE, 24, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTE, 30, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTE, 29, 0); /* EMDC */
-
-#ifndef CONFIG_RMII
- at91_set_a_periph(AT91_PIO_PORTE, 22, 0); /* ECRS */
- at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */
- at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */
- at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */
- at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */
- at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */
- at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_USB_OHCI_NEW
-void at91_uhp_hw_init(void)
-{
- /* Enable VBus on UHP ports */
- at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
- at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
-}
-#endif
-
-#ifdef CONFIG_AT91_CAN
-void at91_can_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_CAN, &pmc->pcer);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
deleted file mode 100644
index 0e6c0da..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTB, 18, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_b_periph(AT91_PIO_PORTB, 19, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTD, 27, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTB, 19, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTD, 27, 1);
- }
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */
- at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */
- at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTD, 28, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_a_periph(AT91_PIO_PORTD, 18, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_a_periph(AT91_PIO_PORTD, 19, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTD, 28, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTD, 18, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTD, 19, 1);
- }
-
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */
-#ifndef CONFIG_RMII
- at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */
- at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */
- at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */
- at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */
- at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */
- at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */
- at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */
-#endif
-}
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-void at91_mci_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */
- at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_MCI0, &pmc->pcer);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
deleted file mode 100644
index 39f17a1..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * (C) Copyright 2013 Atmel Corporation
- * Josh Wu <josh.wu@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-
-unsigned int has_lcdc()
-{
- return 1;
-}
-
-void at91_serial0_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_serial3_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
- at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
- writel(1 << ATMEL_ID_USART3, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#ifdef CONFIG_ATMEL_SPI
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0))
- at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
- if (cs_mask & (1 << 1))
- at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
- if (cs_mask & (1 << 2))
- at91_set_pio_output(AT91_PIO_PORTA, 1, 1);
- if (cs_mask & (1 << 3))
- at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
- at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
- at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0))
- at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
- if (cs_mask & (1 << 1))
- at91_set_pio_output(AT91_PIO_PORTA, 0, 1);
- if (cs_mask & (1 << 2))
- at91_set_pio_output(AT91_PIO_PORTA, 31, 1);
- if (cs_mask & (1 << 3))
- at91_set_pio_output(AT91_PIO_PORTA, 30, 1);
-}
-#endif
-
-void at91_mci_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
- at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
-
- writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
-}
-
-#ifdef CONFIG_LCD
-void at91_lcd_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
- at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */
- at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */
-
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */
- at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */
- at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */
- at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */
- at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */
- at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */
- at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */
- at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */
- at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */
- at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
- at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
-
- writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
deleted file mode 100644
index 0ec32c3..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-
-/*
- * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
- * peripheral pins. Good to have if hardware is soldered optionally
- * or in case of SPI no slave is selected. Avoid lines to float
- * needlessly. Use a short local PUP define.
- *
- * Due to errata "TXD floats when CTS is inactive" pullups are always
- * on for TXD pins.
- */
-#ifdef CONFIG_AT91_GPIO_PULLUP
-# define PUP CONFIG_AT91_GPIO_PULLUP
-#else
-# define PUP 0
-#endif
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* RXD0 */
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTA, 12, PUP); /* RXD1 */
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 14, PUP); /* RXD2 */
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 26, PUP); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI, &pmc->pcer);
-
- if (cs_mask & (1 << 0)) {
- at91_set_a_periph(AT91_PIO_PORTA, 28, 1);
- }
- if (cs_mask & (1 << 1)) {
- at91_set_b_periph(AT91_PIO_PORTB, 7, 1);
- }
- if (cs_mask & (1 << 2)) {
- at91_set_a_periph(AT91_PIO_PORTD, 8, 1);
- }
- if (cs_mask & (1 << 3)) {
- at91_set_b_periph(AT91_PIO_PORTD, 9, 1);
- }
- if (cs_mask & (1 << 4)) {
- at91_set_pio_output(AT91_PIO_PORTA, 28, 1);
- }
- if (cs_mask & (1 << 5)) {
- at91_set_pio_output(AT91_PIO_PORTB, 7, 1);
- }
- if (cs_mask & (1 << 6)) {
- at91_set_pio_output(AT91_PIO_PORTD, 8, 1);
- }
- if (cs_mask & (1 << 7)) {
- at91_set_pio_output(AT91_PIO_PORTD, 9, 1);
- }
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
deleted file mode 100644
index 6d94572..0000000
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * Copyright (C) 2012 Atmel Corporation
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-
-unsigned int get_chip_id(void)
-{
- /* The 0x40 is the offset of cidr in DBGU */
- return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
-}
-
-unsigned int get_extension_chip_id(void)
-{
- /* The 0x44 is the offset of exid in DBGU */
- return readl(ATMEL_BASE_DBGU + 0x44);
-}
-
-unsigned int has_emac1()
-{
- return cpu_is_at91sam9x25();
-}
-
-unsigned int has_emac0()
-{
- return !(cpu_is_at91sam9g15());
-}
-
-unsigned int has_lcdc()
-{
- return cpu_is_at91sam9g15() || cpu_is_at91sam9g35()
- || cpu_is_at91sam9x35();
-}
-
-char *get_cpu_name()
-{
- unsigned int extension_id = get_extension_chip_id();
-
- if (cpu_is_at91sam9x5()) {
- switch (extension_id) {
- case ARCH_EXID_AT91SAM9G15:
- return "AT91SAM9G15";
- case ARCH_EXID_AT91SAM9G25:
- return "AT91SAM9G25";
- case ARCH_EXID_AT91SAM9G35:
- return "AT91SAM9G35";
- case ARCH_EXID_AT91SAM9X25:
- return "AT91SAM9X25";
- case ARCH_EXID_AT91SAM9X35:
- return "AT91SAM9X35";
- default:
- return "Unknown CPU type";
- }
- } else {
- return "Unknown CPU type";
- }
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
-
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-}
-
-void at91_serial0_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
-
- writel(1 << ATMEL_ID_USART0, &pmc->pcer);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
-
- writel(1 << ATMEL_ID_USART1, &pmc->pcer);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
- at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
-
- writel(1 << ATMEL_ID_USART2, &pmc->pcer);
-}
-
-void at91_mci_hw_init(void)
-{
- /* Initialize the MCI0 */
- at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */
- at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */
- at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */
- at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */
- at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */
-
- /* Enable clock for MCI0 */
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
-}
-
-#ifdef CONFIG_ATMEL_SPI
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
-
- if (cs_mask & (1 << 0))
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
- if (cs_mask & (1 << 1))
- at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
- if (cs_mask & (1 << 2))
- at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
- if (cs_mask & (1 << 3))
- at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
- if (cs_mask & (1 << 4))
- at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
- if (cs_mask & (1 << 5))
- at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
- if (cs_mask & (1 << 6))
- at91_set_pio_output(AT91_PIO_PORTA, 1, 0);
- if (cs_mask & (1 << 7))
- at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
-}
-
-void at91_spi1_hw_init(unsigned long cs_mask)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
- at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
- at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
-
- /* Enable clock */
- writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
-
- if (cs_mask & (1 << 0))
- at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
- if (cs_mask & (1 << 1))
- at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
- if (cs_mask & (1 << 2))
- at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
- if (cs_mask & (1 << 3))
- at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
- if (cs_mask & (1 << 4))
- at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
- if (cs_mask & (1 << 5))
- at91_set_pio_output(AT91_PIO_PORTA, 0, 0);
- if (cs_mask & (1 << 6))
- at91_set_pio_output(AT91_PIO_PORTA, 31, 0);
- if (cs_mask & (1 << 7))
- at91_set_pio_output(AT91_PIO_PORTA, 30, 0);
-}
-#endif
-
-#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
-void at91_uhp_hw_init(void)
-{
- /* Enable VBus on UHP ports */
- at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */
- at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */
-#if defined(CONFIG_USB_OHCI_NEW)
- /* port C is OHCI only */
- at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */
-#endif
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
- if (has_emac0()) {
- /* Enable EMAC0 clock */
- writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
- /* EMAC0 pins setup */
- at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
- }
-
- if (has_emac1()) {
- /* Enable EMAC1 clock */
- writel(1 << ATMEL_ID_EMAC1, &pmc->pcer);
- /* EMAC1 pins setup */
- at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
- at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
- at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
- at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
- at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
- at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
- at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
- at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
- at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
- at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
- }
-
-#ifndef CONFIG_RMII
- /* Only emac0 support MII */
- if (has_emac0()) {
- at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
- at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
- }
-#endif
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
deleted file mode 100644
index f363982..0000000
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
- *
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned long at91_css_to_rate(unsigned long css)
-{
- switch (css) {
- case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
- case AT91_PMC_MCKR_CSS_MAIN:
- return gd->arch.main_clk_rate_hz;
- case AT91_PMC_MCKR_CSS_PLLA:
- return gd->arch.plla_rate_hz;
- case AT91_PMC_MCKR_CSS_PLLB:
- return gd->arch.pllb_rate_hz;
- }
-
- return 0;
-}
-
-#ifdef CONFIG_USB_ATMEL
-static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
-{
- unsigned i, div = 0, mul = 0, diff = 1 << 30;
- unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
- /* PLL output max 240 MHz (or 180 MHz per errata) */
- if (out_freq > 240000000)
- goto fail;
-
- for (i = 1; i < 256; i++) {
- int diff1;
- unsigned input, mul1;
-
- /*
- * PLL input between 1MHz and 32MHz per spec, but lower
- * frequences seem necessary in some cases so allow 100K.
- * Warning: some newer products need 2MHz min.
- */
- input = main_freq / i;
-#if defined(CONFIG_AT91SAM9G20)
- if (input < 2000000)
- continue;
-#endif
- if (input < 100000)
- continue;
- if (input > 32000000)
- continue;
-
- mul1 = out_freq / input;
-#if defined(CONFIG_AT91SAM9G20)
- if (mul > 63)
- continue;
-#endif
- if (mul1 > 2048)
- continue;
- if (mul1 < 2)
- goto fail;
-
- diff1 = out_freq - input * mul1;
- if (diff1 < 0)
- diff1 = -diff1;
- if (diff > diff1) {
- diff = diff1;
- div = i;
- mul = mul1;
- if (diff == 0)
- break;
- }
- }
- if (i == 256 && diff > (out_freq >> 5))
- goto fail;
- return ret | ((mul - 1) << 16) | div;
-fail:
- return 0;
-}
-#endif
-
-static u32 at91_pll_rate(u32 freq, u32 reg)
-{
- unsigned mul, div;
-
- div = reg & 0xff;
- mul = (reg >> 16) & 0x7ff;
- if (div && mul) {
- freq /= div;
- freq *= mul + 1;
- } else
- freq = 0;
-
- return freq;
-}
-
-int at91_clock_init(unsigned long main_clock)
-{
- unsigned freq, mckr;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
- unsigned tmp;
- /*
- * When the bootloader initialized the main oscillator correctly,
- * there's no problem using the cycle counter. But if it didn't,
- * or when using oscillator bypass mode, we must be told the speed
- * of the main clock.
- */
- if (!main_clock) {
- do {
- tmp = readl(&pmc->mcfr);
- } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
- tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
- }
-#endif
- gd->arch.main_clk_rate_hz = main_clock;
-
- /* report if PLLA is more than mildly overclocked */
- gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
-
-#ifdef CONFIG_USB_ATMEL
- /*
- * USB clock init: choose 48 MHz PLLB value,
- * disable 48MHz clock during usb peripheral suspend.
- *
- * REVISIT: assumes MCK doesn't derive from PLLB!
- */
- gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
- AT91_PMC_PLLBR_USBDIV_2;
- gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
- gd->arch.at91_pllb_usb_init);
-#endif
-
- /*
- * MCK and CPU derive from one of those primary clocks.
- * For now, assume this parentage won't change.
- */
- mckr = readl(&pmc->mckr);
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
- || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
- /* plla divisor by 2 */
- gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
-#endif
- gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
- freq = gd->arch.mck_rate_hz;
-
- freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
-#if defined(CONFIG_AT91SAM9G20)
- /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
- gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
- freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
- if (mckr & AT91_PMC_MCKR_MDIV_MASK)
- freq /= 2; /* processor clock division */
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
- || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
- /* mdiv <==> divisor
- * 0 <==> 1
- * 1 <==> 2
- * 2 <==> 4
- * 3 <==> 3
- */
- gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
- (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
- ? freq / 3
- : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-#else
- gd->arch.mck_rate_hz = freq /
- (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-#endif
- gd->arch.cpu_clk_rate_hz = freq;
-
- return 0;
-}
-
-#if !defined(AT91_PLL_LOCK_TIMEOUT)
-#define AT91_PLL_LOCK_TIMEOUT 1000000
-#endif
-
-void at91_plla_init(u32 pllar)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
-
- writel(pllar, &pmc->pllar);
- while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
- timeout--;
- if (timeout == 0)
- break;
- }
-}
-void at91_pllb_init(u32 pllbr)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
-
- writel(pllbr, &pmc->pllbr);
- while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
- timeout--;
- if (timeout == 0)
- break;
- }
-}
-
-void at91_mck_init(u32 mckr)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- int timeout = AT91_PLL_LOCK_TIMEOUT;
- u32 tmp;
-
- tmp = readl(&pmc->mckr);
- tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_MASK |
- AT91_PMC_MCKR_CSS_MASK);
- tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_MASK |
- AT91_PMC_MCKR_CSS_MASK);
- writel(tmp, &pmc->mckr);
-
- while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) {
- timeout--;
- if (timeout == 0)
- break;
- }
-}
-
-void at91_periph_clk_enable(int id)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- writel(1 << id, &pmc->pcer);
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/config.mk b/arch/arm/cpu/arm926ejs/at91/config.mk
deleted file mode 100644
index 370630d..0000000
--- a/arch/arm/cpu/arm926ejs/at91/config.mk
+++ /dev/null
@@ -1,2 +0,0 @@
-PF_CPPFLAGS_TUNE := $(call cc-option,-mtune=arm926ejs,)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_TUNE)
diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c
deleted file mode 100644
index da1d359..0000000
--- a/arch/arm/cpu/arm926ejs/at91/cpu.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- * (C) Copyright 2009
- * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_gpbr.h>
-#include <asm/arch/clk.h>
-
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
-#endif
-
-int arch_cpu_init(void)
-{
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-}
-
-void arch_preboot_os(void)
-{
- ulong cpiv;
- at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
-
- cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
-
- /*
- * Disable PITC
- * Add 0x1000 to current counter to stop it faster
- * without waiting for wrapping back to 0
- */
- writel(cpiv + 0x1000, &pit->mr);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- char buf[32];
-
- printf("CPU: %s\n", ATMEL_CPU_NAME);
- printf("Crystal frequency: %8s MHz\n",
- strmhz(buf, get_main_clk_rate()));
- printf("CPU clock : %8s MHz\n",
- strmhz(buf, get_cpu_clk_rate()));
- printf("Master clock : %8s MHz\n",
- strmhz(buf, get_mck_clk_rate()));
-
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c
deleted file mode 100644
index 3f39264..0000000
--- a/arch/arm/cpu/arm926ejs/at91/eflash.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * this driver supports the enhanced embedded flash in the Atmel
- * AT91SAM9XE devices with the following geometry:
- *
- * AT91SAM9XE128: 1 plane of 8 regions of 32 pages (total 256 pages)
- * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total 512 pages)
- * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages)
- * (the exact geometry is read from the flash at runtime, so any
- * future devices should already be covered)
- *
- * Regions can be write/erase protected.
- * Whole (!) pages can be individually written with erase on the fly.
- * Writing partial pages will corrupt the rest of the page.
- *
- * The flash is presented to u-boot with each region being a sector,
- * having the following effects:
- * Each sector can be hardware protected (protect on/off).
- * Each page in a sector can be rewritten anytime.
- * Since pages are erased when written, the "erase" does nothing.
- * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected
- * by u-Boot commands.
- *
- * Note: Redundant environment will not work in this flash since
- * it does use partial page writes. Make sure the environment spans
- * whole pages!
- */
-
-/*
- * optional TODOs (nice to have features):
- *
- * make the driver coexist with other NOR flash drivers
- * (use an index into flash_info[], requires work
- * in those other drivers, too)
- * Make the erase command fill the sectors with 0xff
- * (if the flashes grow larger in the future and
- * someone puts a jffs2 into them)
- * do a read-modify-write for partially programmed pages
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_eefc.h>
-#include <asm/arch/at91_dbu.h>
-
-/* checks to detect configuration errors */
-#if CONFIG_SYS_MAX_FLASH_BANKS!=1
-#error eflash: this driver can only handle 1 bank
-#endif
-
-/* global structure */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-static u32 pagesize;
-
-unsigned long flash_init (void)
-{
- at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
- at91_dbu_t *dbu = (at91_dbu_t *) ATMEL_BASE_DBGU;
- u32 id, size, nplanes, planesize, nlocks;
- u32 addr, i, tmp=0;
-
- debug("eflash: init\n");
-
- flash_info[0].flash_id = FLASH_UNKNOWN;
-
- /* check if its an AT91ARM9XE SoC */
- if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) {
- puts("eflash: not an AT91SAM9XE\n");
- return 0;
- }
-
- /* now query the eflash for its structure */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- id = readl(&eefc->frr); /* word 0 */
- size = readl(&eefc->frr); /* word 1 */
- pagesize = readl(&eefc->frr); /* word 2 */
- nplanes = readl(&eefc->frr); /* word 3 */
- planesize = readl(&eefc->frr); /* word 4 */
- debug("id=%08x size=%u pagesize=%u planes=%u planesize=%u\n",
- id, size, pagesize, nplanes, planesize);
- for (i=1; i<nplanes; i++) {
- tmp = readl(&eefc->frr); /* words 5..4+nplanes-1 */
- };
- nlocks = readl(&eefc->frr); /* word 4+nplanes */
- debug("nlocks=%u\n", nlocks);
- /* since we are going to use the lock regions as sectors, check count */
- if (nlocks > CONFIG_SYS_MAX_FLASH_SECT) {
- printf("eflash: number of lock regions(%u) "\
- "> CONFIG_SYS_MAX_FLASH_SECT. reducing...\n",
- nlocks);
- nlocks = CONFIG_SYS_MAX_FLASH_SECT;
- }
- flash_info[0].size = size;
- flash_info[0].sector_count = nlocks;
- flash_info[0].flash_id = id;
-
- addr = ATMEL_BASE_FLASH;
- for (i=0; i<nlocks; i++) {
- tmp = readl(&eefc->frr); /* words 4+nplanes+1.. */
- flash_info[0].start[i] = addr;
- flash_info[0].protect[i] = 0;
- addr += tmp;
- };
-
- /* now read the protection information for all regions */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- for (i=0; i<flash_info[0].sector_count; i++) {
- if (i%32 == 0)
- tmp = readl(&eefc->frr);
- flash_info[0].protect[i] = (tmp >> (i%32)) & 1;
-#if defined(CONFIG_EFLASH_PROTSECTORS)
- if (i < CONFIG_EFLASH_PROTSECTORS)
- flash_info[0].protect[i] = 1;
-#endif
- }
-
- return size;
-}
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- puts("AT91SAM9XE embedded flash\n Size: ");
- print_size(info->size, " in ");
- printf("%d Sectors\n", info->sector_count);
-
- printf(" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf("\n ");
- printf(" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-int flash_real_protect (flash_info_t *info, long sector, int prot)
-{
- at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
- u32 pagenum = (info->start[sector]-ATMEL_BASE_FLASH)/pagesize;
- u32 i, tmp=0;
-
- debug("protect sector=%ld prot=%d\n", sector, prot);
-
-#if defined(CONFIG_EFLASH_PROTSECTORS)
- if (sector < CONFIG_EFLASH_PROTSECTORS) {
- if (!prot) {
- printf("eflash: sector %lu cannot be unprotected\n",
- sector);
- }
- return 1; /* return anyway, caller does not care for result */
- }
-#endif
- if (prot) {
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_SLB |
- (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
- } else {
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_CLB |
- (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
- }
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- /* now re-read the protection information for all regions */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- for (i=0; i<info->sector_count; i++) {
- if (i%32 == 0)
- tmp = readl(&eefc->frr);
- info->protect[i] = (tmp >> (i%32)) & 1;
- }
- return 0;
-}
-
-static u32 erase_write_page (u32 pagenum)
-{
- at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC;
-
- debug("erase+write page=%u\n", pagenum);
-
- /* give erase and write page command */
- writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_EWP |
- (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr);
- while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0)
- ;
- /* return status */
- return readl(&eefc->fsr)
- & (AT91_EEFC_FSR_FCMDE | AT91_EEFC_FSR_FLOCKE);
-}
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- debug("erase first=%d last=%d\n", s_first, s_last);
- puts("this flash does not need and support erasing!\n");
- return 0;
-}
-
-/*
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- u32 pagenum;
- u32 *src32, *dst32;
- u32 i;
-
- debug("write src=%08lx addr=%08lx cnt=%lx\n",
- (ulong)src, addr, cnt);
-
- /* REQUIRE addr to be on a page start, abort if not */
- if (addr % pagesize) {
- printf ("eflash: start %08lx is not on page start\n"\
- " write aborted\n", addr);
- return 1;
- }
-
- /* now start copying data */
- pagenum = (addr-ATMEL_BASE_FLASH)/pagesize;
- src32 = (u32 *) src;
- dst32 = (u32 *) addr;
- while (cnt > 0) {
- i = pagesize / 4;
- /* fill page buffer */
- while (i--)
- *dst32++ = *src32++;
- /* write page */
- if (erase_write_page(pagenum))
- return 1;
- pagenum++;
- if (cnt > pagesize)
- cnt -= pagesize;
- else
- cnt = 0;
- }
- return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c
deleted file mode 100644
index b8d5c78..0000000
--- a/arch/arm/cpu/arm926ejs/at91/led.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/gpio.h>
-#include <asm/arch/gpio.h>
-#include <status_led.h>
-
-#ifdef CONFIG_RED_LED
-void red_led_on(void)
-{
- gpio_set_value(CONFIG_RED_LED, 1);
-}
-
-void red_led_off(void)
-{
- gpio_set_value(CONFIG_RED_LED, 0);
-}
-#endif
-
-#ifdef CONFIG_GREEN_LED
-void green_led_on(void)
-{
- gpio_set_value(CONFIG_GREEN_LED, 0);
-}
-
-void green_led_off(void)
-{
- gpio_set_value(CONFIG_GREEN_LED, 1);
-}
-#endif
-
-#ifdef CONFIG_YELLOW_LED
-void yellow_led_on(void)
-{
- gpio_set_value(CONFIG_YELLOW_LED, 0);
-}
-
-void yellow_led_off(void)
-{
- gpio_set_value(CONFIG_YELLOW_LED, 1);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
deleted file mode 100644
index a9ec81a..0000000
--- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_wdt.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_matrix.h>
-#include <asm/arch/at91sam9_sdramc.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91_rstc.h>
-#ifdef CONFIG_ATMEL_LEGACY
-#include <asm/arch/at91sam9_matrix.h>
-#endif
-#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
-#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
-#endif
-
-.globl lowlevel_init
-.type lowlevel_init,function
-lowlevel_init:
-
-POS1:
- adr r5, POS1 /* r5 = POS1 run time */
- ldr r0, =POS1 /* r0 = POS1 compile */
- sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */
-
- /* memory control configuration 1 */
- ldr r0, =SMRDATA
- ldr r2, =SMRDATA1
- add r0, r0, r5
- add r2, r2, r5
-0:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne 0b
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 1.
- * ----------------------------------------------------------------------------
- * - Check if the PLL is already initialized
- * ----------------------------------------------------------------------------
- */
- ldr r1, =(AT91_ASM_PMC_MCKR)
- ldr r0, [r1]
- and r0, r0, #3
- cmp r0, #0
- bne PLL_setup_end
-
-/* ---------------------------------------------------------------------------
- * - Enable the Main Oscillator
- * ---------------------------------------------------------------------------
- */
- ldr r1, =(AT91_ASM_PMC_MOR)
- ldr r2, =(AT91_ASM_PMC_SR)
- /* Main oscillator Enable register PMC_MOR: */
- ldr r0, =CONFIG_SYS_MOR_VAL
- str r0, [r1]
-
- /* Reading the PMC Status to detect when the Main Oscillator is enabled */
- mov r4, #AT91_PMC_IXR_MOSCS
-MOSCS_Loop:
- ldr r3, [r2]
- and r3, r4, r3
- cmp r3, #AT91_PMC_IXR_MOSCS
- bne MOSCS_Loop
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 2.
- * ----------------------------------------------------------------------------
- * Setup PLLA
- * ----------------------------------------------------------------------------
- */
- ldr r1, =(AT91_ASM_PMC_PLLAR)
- ldr r0, =CONFIG_SYS_PLLAR_VAL
- str r0, [r1]
-
- /* Reading the PMC Status register to detect when the PLLA is locked */
- mov r4, #AT91_PMC_IXR_LOCKA
-MOSCS_Loop1:
- ldr r3, [r2]
- and r3, r4, r3
- cmp r3, #AT91_PMC_IXR_LOCKA
- bne MOSCS_Loop1
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 3.
- * ----------------------------------------------------------------------------
- * - Switch on the Main Oscillator
- * ----------------------------------------------------------------------------
- */
- ldr r1, =(AT91_ASM_PMC_MCKR)
-
- /* -Master Clock Controller register PMC_MCKR */
- ldr r0, =CONFIG_SYS_MCKR1_VAL
- str r0, [r1]
-
- /* Reading the PMC Status to detect when the Master clock is ready */
- mov r4, #AT91_PMC_IXR_MCKRDY
-MCKRDY_Loop:
- ldr r3, [r2]
- and r3, r4, r3
- cmp r3, #AT91_PMC_IXR_MCKRDY
- bne MCKRDY_Loop
-
- ldr r0, =CONFIG_SYS_MCKR2_VAL
- str r0, [r1]
-
- /* Reading the PMC Status to detect when the Master clock is ready */
- mov r4, #AT91_PMC_IXR_MCKRDY
-MCKRDY_Loop1:
- ldr r3, [r2]
- and r3, r4, r3
- cmp r3, #AT91_PMC_IXR_MCKRDY
- bne MCKRDY_Loop1
-PLL_setup_end:
-
-/* ----------------------------------------------------------------------------
- * - memory control configuration 2
- * ----------------------------------------------------------------------------
- */
- ldr r0, =(AT91_ASM_SDRAMC_TR)
- ldr r1, [r0]
- cmp r1, #0
- bne SDRAM_setup_end
-
- ldr r0, =SMRDATA1
- ldr r2, =SMRDATA2
- add r0, r0, r5
- add r2, r2, r5
-2:
- /* the address */
- ldr r1, [r0], #4
- /* the value */
- ldr r3, [r0], #4
- str r3, [r1]
- cmp r2, r0
- bne 2b
-
-SDRAM_setup_end:
- /* everything is fine now */
- mov pc, lr
-
- .ltorg
-
-SMRDATA:
- .word AT91_ASM_WDT_MR
- .word CONFIG_SYS_WDTC_WDMR_VAL
- /* configure PIOx as EBI0 D[16-31] */
-#if defined(CONFIG_AT91SAM9263)
- .word AT91_ASM_PIOD_PDR
- .word CONFIG_SYS_PIOD_PDR_VAL1
- .word AT91_ASM_PIOD_PUDR
- .word CONFIG_SYS_PIOD_PPUDR_VAL
- .word AT91_ASM_PIOD_ASR
- .word CONFIG_SYS_PIOD_PPUDR_VAL
-#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
- || defined(CONFIG_AT91SAM9G20)
- .word AT91_ASM_PIOC_PDR
- .word CONFIG_SYS_PIOC_PDR_VAL1
- .word AT91_ASM_PIOC_PUDR
- .word CONFIG_SYS_PIOC_PPUDR_VAL
-#endif
- .word AT91_ASM_MATRIX_CSA0
- .word CONFIG_SYS_MATRIX_EBICSA_VAL
-
- /* flash */
- .word AT91_ASM_SMC_MODE0
- .word CONFIG_SYS_SMC0_MODE0_VAL
-
- .word AT91_ASM_SMC_CYCLE0
- .word CONFIG_SYS_SMC0_CYCLE0_VAL
-
- .word AT91_ASM_SMC_PULSE0
- .word CONFIG_SYS_SMC0_PULSE0_VAL
-
- .word AT91_ASM_SMC_SETUP0
- .word CONFIG_SYS_SMC0_SETUP0_VAL
-
-SMRDATA1:
- .word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL1
- .word AT91_ASM_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL1
- .word AT91_ASM_SDRAMC_CR
- .word CONFIG_SYS_SDRC_CR_VAL
- .word AT91_ASM_SDRAMC_MDR
- .word CONFIG_SYS_SDRC_MDR_VAL
- .word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL1
- .word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL3
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL3
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL4
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL5
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL6
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL7
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL8
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL9
- .word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL4
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL10
- .word AT91_ASM_SDRAMC_MR
- .word CONFIG_SYS_SDRC_MR_VAL5
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL11
- .word AT91_ASM_SDRAMC_TR
- .word CONFIG_SYS_SDRC_TR_VAL2
- .word CONFIG_SYS_SDRAM_BASE
- .word CONFIG_SYS_SDRAM_VAL12
- /* User reset enable*/
- .word AT91_ASM_RSTC_MR
- .word CONFIG_SYS_RSTC_RMR_VAL
-#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
- /* MATRIX_MCFG - REMAP all masters */
- .word AT91_ASM_MATRIX_MCFG
- .word 0x1FF
-#endif
-SMRDATA2:
- .word 0
diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c
deleted file mode 100644
index e67f47b..0000000
--- a/arch/arm/cpu/arm926ejs/at91/reset.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_rstc.h>
-
-/* Reset the cpu by telling the reset controller to do so */
-void reset_cpu(ulong ignored)
-{
- at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
-
- writel(AT91_RSTC_KEY
- | AT91_RSTC_CR_PROCRST /* Processor Reset */
- | AT91_RSTC_CR_PERRST /* Peripheral Reset */
-#ifdef CONFIG_AT91RESET_EXTRST
- | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */
-#endif
- , &rstc->cr);
- /* never reached */
- while (1)
- ;
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c
deleted file mode 100644
index b0b7fb9..0000000
--- a/arch/arm/cpu/arm926ejs/at91/timer.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <div64.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
- * setting the 20 bit counter period to its maximum (0xfffff).
- * (See the relevant data sheets to understand that this really works)
- *
- * We do also mimic the typical powerpc way of incrementing
- * two 32 bit registers called tbl and tbu.
- *
- * Those registers increment at 1/16 the main clock rate.
- */
-
-#define TIMER_LOAD_VAL 0xfffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, gd->arch.timer_rate_hz);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= gd->arch.timer_rate_hz;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-/*
- * Use the PITC in full 32 bit incrementing mode
- */
-int timer_init(void)
-{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
-
- /* Enable PITC Clock */
- writel(1 << ATMEL_ID_SYS, &pmc->pcer);
-
- /* Enable PITC */
- writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
-
- gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
- gd->arch.tbu = gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
- at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT;
-
- ulong now = readl(&pit->piir);
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long start;
- ulong tmo;
-
- start = get_ticks(); /* get current timestamp */
- tmo = usec_to_tick(usec); /* convert usecs to ticks */
- while ((get_ticks() - start) < tmo)
- ; /* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
- return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gd->arch.timer_rate_hz;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/Kconfig b/arch/arm/cpu/arm926ejs/davinci/Kconfig
deleted file mode 100644
index 613f04d..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/Kconfig
+++ /dev/null
@@ -1,78 +0,0 @@
-if ARCH_DAVINCI
-
-choice
- prompt "DaVinci board select"
-
-config TARGET_ENBW_CMC
- bool "EnBW CMC board"
-
-config TARGET_IPAM390
- bool "IPAM390 board"
- select SUPPORT_SPL
-
-config TARGET_DA830EVM
- bool "DA830 EVM board"
-
-config TARGET_DA850EVM
- bool "DA850 EVM board"
- select SUPPORT_SPL
-
-config TARGET_CAM_ENC_4XX
- bool "CAM ENC 4xx board"
- select SUPPORT_SPL
-
-config TARGET_HAWKBOARD
- bool "Hawkboard"
- select SUPPORT_SPL
-
-config TARGET_DAVINCI_DM355EVM
- bool "DM355 EVM board"
-
-config TARGET_DAVINCI_DM355LEOPARD
- bool "DM355 Leopard board"
-
-config TARGET_DAVINCI_DM365EVM
- bool "DM365 EVM board"
-
-config TARGET_DAVINCI_DM6467EVM
- bool "DM6467 EVM board"
-
-config TARGET_DAVINCI_DVEVM
- bool "DVEVM board"
-
-config TARGET_EA20
- bool "EA20 board"
-
-config TARGET_DAVINCI_SCHMOOGIE
- bool "Schmoogie board"
-
-config TARGET_DAVINCI_SFFSDR
- bool "SFFSDR board"
-
-config TARGET_DAVINCI_SONATA
- bool "Sonata board"
-
-config TARGET_CALIMAIN
- bool "Calimain board"
-
-endchoice
-
-config SYS_SOC
- default "davinci"
-
-source "board/enbw/enbw_cmc/Kconfig"
-source "board/ait/cam_enc_4xx/Kconfig"
-source "board/Barix/ipam390/Kconfig"
-source "board/davinci/da8xxevm/Kconfig"
-source "board/davinci/dm355evm/Kconfig"
-source "board/davinci/dm355leopard/Kconfig"
-source "board/davinci/dm365evm/Kconfig"
-source "board/davinci/dm6467evm/Kconfig"
-source "board/davinci/dvevm/Kconfig"
-source "board/davinci/ea20/Kconfig"
-source "board/davinci/schmoogie/Kconfig"
-source "board/davinci/sffsdr/Kconfig"
-source "board/davinci/sonata/Kconfig"
-source "board/omicron/calimain/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
deleted file mode 100644
index 7d67191..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu.o misc.o timer.o psc.o pinmux.o reset.o
-obj-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
-obj-$(CONFIG_SOC_DM355) += dm355.o
-obj-$(CONFIG_SOC_DM365) += dm365.o
-obj-$(CONFIG_SOC_DM644X) += dm644x.o
-obj-$(CONFIG_SOC_DM646X) += dm646x.o
-obj-$(CONFIG_SOC_DA830) += da830_pinmux.o
-obj-$(CONFIG_SOC_DA850) += da850_pinmux.o
-obj-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
-obj-$(CONFIG_SOC_DM365) += dm365_lowlevel.o
-obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
-endif
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y += lowlevel_init.o
-endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/config.mk b/arch/arm/cpu/arm926ejs/davinci/config.mk
deleted file mode 100644
index 69e9d5a..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2012, Texas Instruments, Incorporated - http://www.ti.com/
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifndef CONFIG_SPL_BUILD
-ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais
-endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c
deleted file mode 100644
index ff61147..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/cpu.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2004 Texas Instruments.
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* offsets from PLL controller base */
-#define PLLC_PLLCTL 0x100
-#define PLLC_PLLM 0x110
-#define PLLC_PREDIV 0x114
-#define PLLC_PLLDIV1 0x118
-#define PLLC_PLLDIV2 0x11c
-#define PLLC_PLLDIV3 0x120
-#define PLLC_POSTDIV 0x128
-#define PLLC_BPDIV 0x12c
-#define PLLC_PLLDIV4 0x160
-#define PLLC_PLLDIV5 0x164
-#define PLLC_PLLDIV6 0x168
-#define PLLC_PLLDIV7 0x16c
-#define PLLC_PLLDIV8 0x170
-#define PLLC_PLLDIV9 0x174
-
-#define BIT(x) (1 << (x))
-
-/* SOC-specific pll info */
-#ifdef CONFIG_SOC_DM355
-#define ARM_PLLDIV PLLC_PLLDIV1
-#define DDR_PLLDIV PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DM644X
-#define ARM_PLLDIV PLLC_PLLDIV2
-#define DSP_PLLDIV PLLC_PLLDIV1
-#define DDR_PLLDIV PLLC_PLLDIV2
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DSP_PLLDIV PLLC_PLLDIV1
-#define ARM_PLLDIV PLLC_PLLDIV2
-#define DDR_PLLDIV PLLC_PLLDIV1
-#endif
-
-#ifdef CONFIG_SOC_DA8XX
-unsigned int sysdiv[9] = {
- PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
- PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
-};
-
-int clk_get(enum davinci_clk_ids id)
-{
- int pre_div;
- int pllm;
- int post_div;
- int pll_out;
- unsigned int pll_base;
-
- pll_out = CONFIG_SYS_OSCIN_FREQ;
-
- if (id == DAVINCI_AUXCLK_CLKID)
- goto out;
-
- if ((id >> 16) == 1)
- pll_base = (unsigned int)davinci_pllc1_regs;
- else
- pll_base = (unsigned int)davinci_pllc0_regs;
-
- id &= 0xFFFF;
-
- /*
- * Lets keep this simple. Combining operations can result in
- * unexpected approximations
- */
- pre_div = (readl(pll_base + PLLC_PREDIV) &
- DAVINCI_PLLC_DIV_MASK) + 1;
- pllm = readl(pll_base + PLLC_PLLM) + 1;
-
- pll_out /= pre_div;
- pll_out *= pllm;
-
- if (id == DAVINCI_PLLM_CLKID)
- goto out;
-
- post_div = (readl(pll_base + PLLC_POSTDIV) &
- DAVINCI_PLLC_DIV_MASK) + 1;
-
- pll_out /= post_div;
-
- if (id == DAVINCI_PLLC_CLKID)
- goto out;
-
- pll_out /= (readl(pll_base + sysdiv[id - 1]) &
- DAVINCI_PLLC_DIV_MASK) + 1;
-
-out:
- return pll_out;
-}
-
-int set_cpu_clk_info(void)
-{
- gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
- /* DDR PHY uses an x2 input clock */
- gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
- (clk_get(DAVINCI_DDR_CLKID) / 1000000);
- gd->bd->bi_dsp_freq = 0;
- return 0;
-}
-
-#else /* CONFIG_SOC_DA8XX */
-
-static unsigned pll_div(volatile void *pllbase, unsigned offset)
-{
- u32 div;
-
- div = REG(pllbase + offset);
- return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
-}
-
-static inline unsigned pll_prediv(volatile void *pllbase)
-{
-#ifdef CONFIG_SOC_DM355
- /* this register read seems to fail on pll0 */
- if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
- return 8;
- else
- return pll_div(pllbase, PLLC_PREDIV);
-#elif defined(CONFIG_SOC_DM365)
- return pll_div(pllbase, PLLC_PREDIV);
-#endif
- return 1;
-}
-
-static inline unsigned pll_postdiv(volatile void *pllbase)
-{
-#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365)
- return pll_div(pllbase, PLLC_POSTDIV);
-#elif defined(CONFIG_SOC_DM6446)
- if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
- return pll_div(pllbase, PLLC_POSTDIV);
-#endif
- return 1;
-}
-
-static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
-{
- volatile void *pllbase = (volatile void *) pll_addr;
-#ifdef CONFIG_SOC_DM646X
- unsigned base = CONFIG_REFCLK_FREQ / 1000;
-#else
- unsigned base = CONFIG_SYS_HZ_CLOCK / 1000;
-#endif
-
- /* the PLL might be bypassed */
- if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) {
- base /= pll_prediv(pllbase);
-#if defined(CONFIG_SOC_DM365)
- base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff);
-#else
- base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
-#endif
- base /= pll_postdiv(pllbase);
- }
- return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
-}
-
-#ifdef DAVINCI_DM6467EVM
-unsigned int davinci_arm_clk_get()
-{
- return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000;
-}
-#endif
-
-#if defined(CONFIG_SOC_DM365)
-unsigned int davinci_clk_get(unsigned int div)
-{
- return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
-}
-#endif
-
-int set_cpu_clk_info(void)
-{
- unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
-#if defined(CONFIG_SOC_DM365)
- pllbase = DAVINCI_PLL_CNTRL1_BASE;
-#endif
- gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV);
-
-#ifdef DSP_PLLDIV
- gd->bd->bi_dsp_freq =
- pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV);
-#else
- gd->bd->bi_dsp_freq = 0;
-#endif
-
- pllbase = DAVINCI_PLL_CNTRL1_BASE;
-#if defined(CONFIG_SOC_DM365)
- pllbase = DAVINCI_PLL_CNTRL0_BASE;
-#endif
- gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
-
- return 0;
-}
-
-#endif /* !CONFIG_SOC_DA8XX */
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
-#if defined(CONFIG_DRIVER_TI_EMAC)
- davinci_emac_initialize();
-#endif
- return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
deleted file mode 100644
index edaab45..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/da830_pinmux.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Pinmux configurations for the DA830 SoCs
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pinmux_defs.h>
-
-/* SPI0 pin muxer settings */
-const struct pinmux_config spi0_pins_base[] = {
- { pinmux(7), 1, 3 }, /* SPI0_SOMI */
- { pinmux(7), 1, 4 }, /* SPI0_SIMO */
- { pinmux(7), 1, 6 } /* SPI0_CLK */
-};
-
-const struct pinmux_config spi0_pins_scs0[] = {
- { pinmux(7), 1, 7 } /* SPI0_SCS[0] */
-};
-
-const struct pinmux_config spi0_pins_ena[] = {
- { pinmux(7), 1, 5 } /* SPI0_ENA */
-};
-
-/* NAND pin muxer settings */
-const struct pinmux_config emifa_pins_cs0[] = {
- { pinmux(18), 1, 2 } /* EMA_CS[0] */
-};
-
-const struct pinmux_config emifa_pins_cs2[] = {
- { pinmux(18), 1, 3 } /* EMA_CS[2] */
-};
-
-const struct pinmux_config emifa_pins_cs3[] = {
- { pinmux(18), 1, 4 } /* EMA_CS[3] */
-};
-
-#ifdef CONFIG_USE_NAND
-const struct pinmux_config emifa_pins[] = {
- { pinmux(13), 1, 6 }, /* EMA_D[0] */
- { pinmux(13), 1, 7 }, /* EMA_D[1] */
- { pinmux(14), 1, 0 }, /* EMA_D[2] */
- { pinmux(14), 1, 1 }, /* EMA_D[3] */
- { pinmux(14), 1, 2 }, /* EMA_D[4] */
- { pinmux(14), 1, 3 }, /* EMA_D[5] */
- { pinmux(14), 1, 4 }, /* EMA_D[6] */
- { pinmux(14), 1, 5 }, /* EMA_D[7] */
- { pinmux(14), 1, 6 }, /* EMA_D[8] */
- { pinmux(14), 1, 7 }, /* EMA_D[9] */
- { pinmux(15), 1, 0 }, /* EMA_D[10] */
- { pinmux(15), 1, 1 }, /* EMA_D[11] */
- { pinmux(15), 1, 2 }, /* EMA_D[12] */
- { pinmux(15), 1, 3 }, /* EMA_D[13] */
- { pinmux(15), 1, 4 }, /* EMA_D[14] */
- { pinmux(15), 1, 5 }, /* EMA_D[15] */
- { pinmux(15), 1, 6 }, /* EMA_A[0] */
- { pinmux(15), 1, 7 }, /* EMA_A[1] */
- { pinmux(16), 1, 0 }, /* EMA_A[2] */
- { pinmux(16), 1, 1 }, /* EMA_A[3] */
- { pinmux(16), 1, 2 }, /* EMA_A[4] */
- { pinmux(16), 1, 3 }, /* EMA_A[5] */
- { pinmux(16), 1, 4 }, /* EMA_A[6] */
- { pinmux(16), 1, 5 }, /* EMA_A[7] */
- { pinmux(16), 1, 6 }, /* EMA_A[8] */
- { pinmux(16), 1, 7 }, /* EMA_A[9] */
- { pinmux(17), 1, 0 }, /* EMA_A[10] */
- { pinmux(17), 1, 1 }, /* EMA_A[11] */
- { pinmux(17), 1, 2 }, /* EMA_A[12] */
- { pinmux(17), 1, 3 }, /* EMA_BA[1] */
- { pinmux(17), 1, 4 }, /* EMA_BA[0] */
- { pinmux(17), 1, 5 }, /* EMA_CLK */
- { pinmux(17), 1, 6 }, /* EMA_SDCKE */
- { pinmux(17), 1, 7 }, /* EMA_CAS */
- { pinmux(18), 1, 0 }, /* EMA_CAS */
- { pinmux(18), 1, 1 }, /* EMA_WE */
- { pinmux(18), 1, 5 }, /* EMA_OE */
- { pinmux(18), 1, 6 }, /* EMA_WE_DQM[1] */
- { pinmux(18), 1, 7 }, /* EMA_WE_DQM[0] */
- { pinmux(10), 1, 0 } /* Tristate */
-};
-#endif
-
-/* EMAC PHY interface pins */
-const struct pinmux_config emac_pins_rmii[] = {
- { pinmux(10), 2, 1 }, /* RMII_TXD[0] */
- { pinmux(10), 2, 2 }, /* RMII_TXD[1] */
- { pinmux(10), 2, 3 }, /* RMII_TXEN */
- { pinmux(10), 2, 4 }, /* RMII_CRS_DV */
- { pinmux(10), 2, 5 }, /* RMII_RXD[0] */
- { pinmux(10), 2, 6 }, /* RMII_RXD[1] */
- { pinmux(10), 2, 7 } /* RMII_RXER */
-};
-
-const struct pinmux_config emac_pins_mdio[] = {
- { pinmux(11), 2, 0 }, /* MDIO_CLK */
- { pinmux(11), 2, 1 } /* MDIO_D */
-};
-
-const struct pinmux_config emac_pins_rmii_clk_source[] = {
- { pinmux(9), 0, 5 } /* ref.clk from external source */
-};
-
-/* UART2 pin muxer settings */
-const struct pinmux_config uart2_pins_txrx[] = {
- { pinmux(8), 2, 7 }, /* UART2_RXD */
- { pinmux(9), 2, 0 } /* UART2_TXD */
-};
-
-/* I2C0 pin muxer settings */
-const struct pinmux_config i2c0_pins[] = {
- { pinmux(8), 2, 3 }, /* I2C0_SDA */
- { pinmux(8), 2, 4 } /* I2C0_SCL */
-};
-
-/* USB0_DRVVBUS pin muxer settings */
-const struct pinmux_config usb_pins[] = {
- { pinmux(9), 1, 1 } /* USB0_DRVVBUS */
-};
-
-#ifdef CONFIG_DAVINCI_MMC
-/* MMC0 pin muxer settings */
-const struct pinmux_config mmc0_pins_8bit[] = {
- { pinmux(15), 2, 7 }, /* MMCSD0_CLK */
- { pinmux(16), 2, 0 }, /* MMCSD0_CMD */
- { pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */
- { pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */
- { pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */
- { pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */
- { pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */
- { pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */
- { pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */
- { pinmux(14), 2, 5 } /* MMCSD0_DAT_7 */
- /* DA830 supports 8-bit mode */
-};
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
deleted file mode 100644
index 19730ce..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * SoC-specific lowlevel code for DA850
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <nand.h>
-#include <ns16550.h>
-#include <post.h>
-#include <asm/arch/da850_lowlevel.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/ddr2_defs.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/pll_defs.h>
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_LPSC_UART0);
-
- /* Bringup UART0 out of reset */
- REG(UART0_PWREMU_MGMT) = 0x00006001;
-}
-
-#if defined(CONFIG_SYS_DA850_PLL_INIT)
-static void da850_waitloop(unsigned long loopcnt)
-{
- unsigned long i;
-
- for (i = 0; i < loopcnt; i++)
- asm(" NOP");
-}
-
-static int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
-{
- if (reg == davinci_pllc0_regs)
- /* Unlock PLL registers. */
- clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
-
- /*
- * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
- * through MMR
- */
- clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
- /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
- clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
-
- /* Set PLLEN=0 => PLL BYPASS MODE */
- clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
-
- da850_waitloop(150);
-
- if (reg == davinci_pllc0_regs) {
- /*
- * Select the Clock Mode bit 8 as External Clock or On Chip
- * Oscilator
- */
- dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
- setbits_le32(&reg->pllctl,
- (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
- }
-
- /* Clear PLLRST bit to reset the PLL */
- clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
-
- /* Disable the PLL output */
- setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
-
- /* PLL initialization sequence */
- /*
- * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
- * power down bit
- */
- clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
-
- /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
- clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
-
-#if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
- /* program the prediv */
- if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
- writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
- &reg->prediv);
-#endif
-
- /* Program the required multiplier value in PLLM */
- writel(pllmult, &reg->pllm);
-
- /* program the postdiv */
- if (reg == davinci_pllc0_regs)
- writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
- &reg->postdiv);
- else
- writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
- &reg->postdiv);
-
- /*
- * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
- * no GO operation is currently in progress
- */
- while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
- ;
-
- if (reg == davinci_pllc0_regs) {
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
- writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
- } else {
- writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
- writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
- writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
- }
-
- /*
- * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
- * transition.
- */
- setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
-
- /*
- * Wait for the GOSTAT bit in PLLSTAT to clear to 0
- * (completion of phase alignment).
- */
- while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
- ;
-
- /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
- da850_waitloop(200);
-
- /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
- setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
-
- /* Wait for PLL to lock. See PLL spec for PLL lock time */
- da850_waitloop(2400);
-
- /*
- * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
- * mode
- */
- setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
-
-
- /*
- * clear EMIFA and EMIFB clock source settings, let them
- * run off SYSCLK
- */
- if (reg == davinci_pllc0_regs)
- dv_maskbits(&davinci_syscfg_regs->cfgchip3,
- ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
-
- return 0;
-}
-#endif /* CONFIG_SYS_DA850_PLL_INIT */
-
-#if defined(CONFIG_SYS_DA850_DDR_INIT)
-static int da850_ddr_setup(void)
-{
- unsigned long tmp;
-
- /* Enable the Clock to DDR2/mDDR */
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
- tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
- if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
- /* Begin VTP Calibration */
- clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
- clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
- clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
-
- /* Polling READY bit to see when VTP calibration is done */
- tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
- while ((tmp & VTP_READY) != VTP_READY)
- tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
-
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
- }
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
- writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
-
- if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
- /* DDR2 */
- clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
- (1 << DDR_SLEW_DDR_PDENA_BIT) |
- (1 << DDR_SLEW_CMOSEN_BIT));
- } else {
- /* MOBILE DDR */
- setbits_le32(&davinci_syscfg1_regs->ddr_slew,
- (1 << DDR_SLEW_DDR_PDENA_BIT) |
- (1 << DDR_SLEW_CMOSEN_BIT));
- }
-
- /*
- * SDRAM Configuration Register (SDCR):
- * First set the BOOTUNLOCK bit to make configuration bits
- * writeable.
- */
- setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
-
- /*
- * Write the new value of these bits and clear BOOTUNLOCK.
- * At the same time, set the TIMUNLOCK bit to allow changing
- * the timing registers
- */
- tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
- tmp &= ~DV_DDR_BOOTUNLOCK;
- tmp |= DV_DDR_TIMUNLOCK;
- writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
-
- /* write memory configuration and timing */
- if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
- /* MOBILE DDR only*/
- writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
- &dv_ddr2_regs_ctrl->sdbcr2);
- }
- writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
- writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
-
- /* clear the TIMUNLOCK bit and write the value of the CL field */
- tmp &= ~DV_DDR_TIMUNLOCK;
- writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
-
- /*
- * LPMODEN and MCLKSTOPEN must be set!
- * Without this bits set, PSC don;t switch states !!
- */
- writel(CONFIG_SYS_DA850_DDR2_SDRCR |
- (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
- (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
- &dv_ddr2_regs_ctrl->sdrcr);
-
- /* SyncReset the Clock to EMIF3A SDRAM */
- lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
- /* Enable the Clock to EMIF3A SDRAM */
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
- /* disable self refresh */
- clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
- DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
- writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
-
- return 0;
-}
-#endif /* CONFIG_SYS_DA850_DDR_INIT */
-
-__attribute__((weak))
-void board_gpio_init(void)
-{
- return;
-}
-
-int arch_cpu_init(void)
-{
- /* Unlock kick registers */
- writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
- writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
-
- dv_maskbits(&davinci_syscfg_regs->suspsrc,
- CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
-
- /* configure pinmux settings */
- if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
- return 1;
-
-#if defined(CONFIG_SYS_DA850_PLL_INIT)
- /* PLL setup */
- da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
- da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
-#endif
- /* setup CSn config */
-#if defined(CONFIG_SYS_DA850_CS2CFG)
- writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
-#endif
-#if defined(CONFIG_SYS_DA850_CS3CFG)
- writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
-#endif
-
- da8xx_configure_lpsc_items(lpsc, lpsc_size);
-
- /* GPIO setup */
- board_gpio_init();
-
-
- NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
- /*
- * Fix Power and Emulation Management Register
- * see sprufw3a.pdf page 37 Table 24
- */
- writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
- DAVINCI_UART_PWREMU_MGMT_UTRST),
-#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
- &davinci_uart0_ctrl_regs->pwremu_mgmt);
-#else
- &davinci_uart2_ctrl_regs->pwremu_mgmt);
-#endif
-
-#if defined(CONFIG_SYS_DA850_DDR_INIT)
- da850_ddr_setup();
-#endif
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
deleted file mode 100644
index 6105f63..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Pinmux configurations for the DA850 SoCs
- *
- * Copyright (C) 2011 OMICRON electronics GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/davinci_misc.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/pinmux_defs.h>
-
-/* SPI pin muxer settings */
-const struct pinmux_config spi1_pins_base[] = {
- { pinmux(5), 1, 2 }, /* SPI1_CLK */
- { pinmux(5), 1, 4 }, /* SPI1_SOMI */
- { pinmux(5), 1, 5 }, /* SPI1_SIMO */
-};
-
-const struct pinmux_config spi1_pins_scs0[] = {
- { pinmux(5), 1, 1 }, /* SPI1_SCS[0] */
-};
-
-/* UART pin muxer settings */
-const struct pinmux_config uart0_pins_txrx[] = {
- { pinmux(3), 2, 4 }, /* UART0_RXD */
- { pinmux(3), 2, 5 }, /* UART0_TXD */
-};
-
-const struct pinmux_config uart0_pins_rtscts[] = {
- { pinmux(3), 2, 6 },
- { pinmux(3), 2, 7 },
-};
-
-const struct pinmux_config uart1_pins_txrx[] = {
- { pinmux(4), 2, 6 }, /* UART1_RXD */
- { pinmux(4), 2, 7 }, /* UART1_TXD */
-};
-
-const struct pinmux_config uart2_pins_txrx[] = {
- { pinmux(4), 2, 4 }, /* UART2_RXD */
- { pinmux(4), 2, 5 }, /* UART2_TXD */
-};
-
-const struct pinmux_config uart2_pins_rtscts[] = {
- { pinmux(0), 4, 6 }, /* UART2_RTS */
- { pinmux(0), 4, 7 }, /* UART2_CTS */
-};
-
-/* EMAC pin muxer settings*/
-const struct pinmux_config emac_pins_rmii[] = {
- { pinmux(14), 8, 2 }, /* RMII_TXD[1] */
- { pinmux(14), 8, 3 }, /* RMII_TXD[0] */
- { pinmux(14), 8, 4 }, /* RMII_TXEN */
- { pinmux(14), 8, 5 }, /* RMII_RXD[1] */
- { pinmux(14), 8, 6 }, /* RMII_RXD[0] */
- { pinmux(14), 8, 7 }, /* RMII_RXER */
- { pinmux(15), 0, 0 }, /* RMII_MHz_50_CLK */
- { pinmux(15), 8, 1 }, /* RMII_CRS_DV */
-};
-
-const struct pinmux_config emac_pins_mii[] = {
- { pinmux(2), 8, 1 }, /* MII_TXEN */
- { pinmux(2), 8, 2 }, /* MII_TXCLK */
- { pinmux(2), 8, 3 }, /* MII_COL */
- { pinmux(2), 8, 4 }, /* MII_TXD[3] */
- { pinmux(2), 8, 5 }, /* MII_TXD[2] */
- { pinmux(2), 8, 6 }, /* MII_TXD[1] */
- { pinmux(2), 8, 7 }, /* MII_TXD[0] */
- { pinmux(3), 8, 0 }, /* MII_RXCLK */
- { pinmux(3), 8, 1 }, /* MII_RXDV */
- { pinmux(3), 8, 2 }, /* MII_RXER */
- { pinmux(3), 8, 3 }, /* MII_CRS */
- { pinmux(3), 8, 4 }, /* MII_RXD[3] */
- { pinmux(3), 8, 5 }, /* MII_RXD[2] */
- { pinmux(3), 8, 6 }, /* MII_RXD[1] */
- { pinmux(3), 8, 7 }, /* MII_RXD[0] */
-};
-
-const struct pinmux_config emac_pins_mdio[] = {
- { pinmux(4), 8, 0 }, /* MDIO_CLK */
- { pinmux(4), 8, 1 }, /* MDIO_D */
-};
-
-/* I2C pin muxer settings */
-const struct pinmux_config i2c0_pins[] = {
- { pinmux(4), 2, 2 }, /* I2C0_SCL */
- { pinmux(4), 2, 3 }, /* I2C0_SDA */
-};
-
-const struct pinmux_config i2c1_pins[] = {
- { pinmux(4), 4, 4 }, /* I2C1_SCL */
- { pinmux(4), 4, 5 }, /* I2C1_SDA */
-};
-
-/* EMIFA pin muxer settings */
-const struct pinmux_config emifa_pins_cs2[] = {
- { pinmux(7), 1, 0 }, /* EMA_CS2 */
-};
-
-const struct pinmux_config emifa_pins_cs3[] = {
- { pinmux(7), 1, 1 }, /* EMA_CS[3] */
-};
-
-const struct pinmux_config emifa_pins_cs4[] = {
- { pinmux(7), 1, 2 }, /* EMA_CS[4] */
-};
-
-const struct pinmux_config emifa_pins_nand[] = {
- { pinmux(7), 1, 4 }, /* EMA_WE */
- { pinmux(7), 1, 5 }, /* EMA_OE */
- { pinmux(9), 1, 0 }, /* EMA_D[7] */
- { pinmux(9), 1, 1 }, /* EMA_D[6] */
- { pinmux(9), 1, 2 }, /* EMA_D[5] */
- { pinmux(9), 1, 3 }, /* EMA_D[4] */
- { pinmux(9), 1, 4 }, /* EMA_D[3] */
- { pinmux(9), 1, 5 }, /* EMA_D[2] */
- { pinmux(9), 1, 6 }, /* EMA_D[1] */
- { pinmux(9), 1, 7 }, /* EMA_D[0] */
- { pinmux(12), 1, 5 }, /* EMA_A[2] */
- { pinmux(12), 1, 6 }, /* EMA_A[1] */
-};
-
-/* NOR pin muxer settings */
-const struct pinmux_config emifa_pins_nor[] = {
- { pinmux(5), 1, 6 }, /* EMA_BA[1] */
- { pinmux(6), 1, 6 }, /* EMA_WAIT[1] */
- { pinmux(7), 1, 4 }, /* EMA_WE */
- { pinmux(7), 1, 5 }, /* EMA_OE */
- { pinmux(8), 1, 0 }, /* EMA_D[15] */
- { pinmux(8), 1, 1 }, /* EMA_D[14] */
- { pinmux(8), 1, 2 }, /* EMA_D[13] */
- { pinmux(8), 1, 3 }, /* EMA_D[12] */
- { pinmux(8), 1, 4 }, /* EMA_D[11] */
- { pinmux(8), 1, 5 }, /* EMA_D[10] */
- { pinmux(8), 1, 6 }, /* EMA_D[9] */
- { pinmux(8), 1, 7 }, /* EMA_D[8] */
- { pinmux(9), 1, 0 }, /* EMA_D[7] */
- { pinmux(9), 1, 1 }, /* EMA_D[6] */
- { pinmux(9), 1, 2 }, /* EMA_D[5] */
- { pinmux(9), 1, 3 }, /* EMA_D[4] */
- { pinmux(9), 1, 4 }, /* EMA_D[3] */
- { pinmux(9), 1, 5 }, /* EMA_D[2] */
- { pinmux(9), 1, 6 }, /* EMA_D[1] */
- { pinmux(9), 1, 7 }, /* EMA_D[0] */
- { pinmux(10), 1, 1 }, /* EMA_A[22] */
- { pinmux(10), 1, 2 }, /* EMA_A[21] */
- { pinmux(10), 1, 3 }, /* EMA_A[20] */
- { pinmux(10), 1, 4 }, /* EMA_A[19] */
- { pinmux(10), 1, 5 }, /* EMA_A[18] */
- { pinmux(10), 1, 6 }, /* EMA_A[17] */
- { pinmux(10), 1, 7 }, /* EMA_A[16] */
- { pinmux(11), 1, 0 }, /* EMA_A[15] */
- { pinmux(11), 1, 1 }, /* EMA_A[14] */
- { pinmux(11), 1, 2 }, /* EMA_A[13] */
- { pinmux(11), 1, 3 }, /* EMA_A[12] */
- { pinmux(11), 1, 4 }, /* EMA_A[11] */
- { pinmux(11), 1, 5 }, /* EMA_A[10] */
- { pinmux(11), 1, 6 }, /* EMA_A[9] */
- { pinmux(11), 1, 7 }, /* EMA_A[8] */
- { pinmux(12), 1, 0 }, /* EMA_A[7] */
- { pinmux(12), 1, 1 }, /* EMA_A[6] */
- { pinmux(12), 1, 2 }, /* EMA_A[5] */
- { pinmux(12), 1, 3 }, /* EMA_A[4] */
- { pinmux(12), 1, 4 }, /* EMA_A[3] */
- { pinmux(12), 1, 5 }, /* EMA_A[2] */
- { pinmux(12), 1, 6 }, /* EMA_A[1] */
- { pinmux(12), 1, 7 }, /* EMA_A[0] */
-};
-
-/* MMC0 pin muxer settings */
-const struct pinmux_config mmc0_pins[] = {
- { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
- { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
- { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
- { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
- { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
- { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
- /* DA850 supports only 4-bit mode, remaining pins are not configured */
-};
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm355.c b/arch/arm/cpu/arm926ejs/davinci/dm355.c
deleted file mode 100644
index f9550a1..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm355.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * SoC-specific code for tms320dm355 and similar chips
- *
- * Copyright (C) 2009 David Brownell
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_LPSC_UART0);
-
- /* Bringup UART0 out of reset */
- REG(UART0_PWREMU_MGMT) = 0x00006001;
-}
-
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_LPSC_I2C);
-
- /* Enable I2C pin Mux */
- REG(PINMUX3) |= (1 << 20) | (1 << 19);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365.c b/arch/arm/cpu/arm926ejs/davinci/dm365.c
deleted file mode 100644
index f6ca527..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm365.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * SoC-specific code for tms320dm365 and similar chips
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_LPSC_UART0);
-}
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_LPSC_I2C);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
deleted file mode 100644
index c8b4498..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- * SoC-specific lowlevel code for tms320dm365 and similar chips
- * Actually used for booting from NAND with nand_spl.
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <nand.h>
-#include <ns16550.h>
-#include <post.h>
-#include <asm/ti-common/davinci_nand.h>
-#include <asm/arch/dm365_lowlevel.h>
-#include <asm/arch/hardware.h>
-
-void dm365_waitloop(unsigned long loopcnt)
-{
- unsigned long i;
-
- for (i = 0; i < loopcnt; i++)
- asm(" NOP");
-}
-
-int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
-{
- unsigned int clksrc = 0x0;
-
- /* Power up the PLL */
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
-
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
- setbits_le32(&dv_pll0_regs->pllctl,
- clksrc << PLLCTL_CLOCK_MODE_SHIFT);
-
- /*
- * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
- * through MMR
- */
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
-
- /* Set PLLEN=0 => PLL BYPASS MODE */
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
-
- dm365_waitloop(150);
-
- /* PLLRST=1(reset assert) */
- setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
-
- dm365_waitloop(300);
-
- /*Bring PLL out of Reset*/
- clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
-
- /* Program the Multiper and Pre-Divider for PLL1 */
- writel(pllmult, &dv_pll0_regs->pllm);
- writel(prediv, &dv_pll0_regs->prediv);
-
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
- PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
- &dv_pll0_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
-
- /* Program the PostDiv for PLL1 */
- writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
-
- /* Post divider setting for PLL1 */
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
- writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
-
- dm365_waitloop(300);
-
- /* Set the GOSET bit */
- writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
-
- dm365_waitloop(300);
-
- /* Wait for PLL to LOCK */
- while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
- == PLL0_LOCK))
- ;
-
- /* Enable the PLL Bit of PLLCTL*/
- setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
-
- return 0;
-}
-
-int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
-{
- unsigned int clksrc = 0x0;
-
- /* Power up the PLL*/
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
-
- /*
- * Select the Clock Mode as Onchip Oscilator or External Clock on
- * MXI pin
- * VDB has input on MXI pin
- */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
- setbits_le32(&dv_pll1_regs->pllctl,
- clksrc << PLLCTL_CLOCK_MODE_SHIFT);
-
- /*
- * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
- * through MMR
- */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
-
- /* Set PLLEN=0 => PLL BYPASS MODE */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
-
- dm365_waitloop(50);
-
- /* PLLRST=1(reset assert) */
- setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
-
- dm365_waitloop(300);
-
- /* Bring PLL out of Reset */
- clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
-
- /* Program the Multiper and Pre-Divider for PLL2 */
- writel(pllm, &dv_pll1_regs->pllm);
- writel(prediv, &dv_pll1_regs->prediv);
-
- writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
-
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
- PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
- /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
- &dv_pll1_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
- writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
- /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
- writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
-
- /* Post divider setting for PLL2 */
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
- writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
-
- /* GoCmd for PostDivider to take effect */
- writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
-
- dm365_waitloop(150);
-
- /* Wait for PLL to LOCK */
- while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
- == PLL1_LOCK))
- ;
-
- dm365_waitloop(4100);
-
- /* Enable the PLL2 */
- setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
-
- /* do this after PLL's have been set up */
- writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
- &dv_sys_module_regs->peri_clkctl);
-
- return 0;
-}
-
-int dm365_ddr_setup(void)
-{
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
- clrbits_le32(&dv_sys_module_regs->vtpiocr,
- VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
-
- /* Set bit CLRZ (bit 13) */
- setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
-
- /* Check VTP READY Status */
- while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
- ;
-
- /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
- setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
-
- /* Set bit LOCK(bit7) */
- setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
-
- /*
- * Powerdown VTP as it is locked (bit 6)
- * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
- */
- setbits_le32(&dv_sys_module_regs->vtpiocr,
- VPTIO_IOPWRDN | VPTIO_PWRDN);
-
- /* Wait for calibration to complete */
- dm365_waitloop(150);
-
- /* Set the DDR2 to synreset, then enable it again */
- lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
- writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
-
- /* Program SDRAM Bank Config Register */
- writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
- &dv_ddr2_regs_ctrl->sdbcr);
- writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
- &dv_ddr2_regs_ctrl->sdbcr);
-
- /* Program SDRAM Timing Control Register1 */
- writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
- /* Program SDRAM Timing Control Register2 */
- writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
-
- writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
-
- writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
-
- /* Program SDRAM Refresh Control Register */
- writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
-
- lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
- lpsc_on(DAVINCI_LPSC_DDR_EMIF);
-
- return 0;
-}
-
-static void dm365_vpss_sync_reset(void)
-{
- unsigned int PdNum = 0;
-
- /* VPSS_CLKMD 1:1 */
- setbits_le32(&dv_sys_module_regs->vpss_clkctl,
- VPSS_CLK_CTL_VPSS_CLKMD);
-
- /* LPSC SyncReset DDR Clock Enable */
- writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
- ~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
- &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
-
- writel((1 << PdNum), &dv_psc_regs->ptcmd);
-
- while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
- ;
- while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
- PSC_MD_STATE_MSK) == PSC_SYNCRESET))
- ;
-}
-
-static void dm365_por_reset(void)
-{
- struct davinci_timer *wdog =
- (struct davinci_timer *)DAVINCI_WDOG_BASE;
-
- if (readl(&dv_pll0_regs->rstype) &
- (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
- dm365_vpss_sync_reset();
-
- writel(DV_TMPBUF_VAL, TMPBUF);
- setbits_le32(TMPSTATUS, FLAG_PORRST);
- writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
- writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
-
- while (1);
- }
-}
-
-static void dm365_wdt_reset(void)
-{
- struct davinci_timer *wdog =
- (struct davinci_timer *)DAVINCI_WDOG_BASE;
-
- if (readl(TMPBUF) != DV_TMPBUF_VAL) {
- writel(DV_TMPBUF_VAL, TMPBUF);
- setbits_le32(TMPSTATUS, FLAG_PORRST);
- setbits_le32(TMPSTATUS, FLAG_FLGOFF);
-
- dm365_waitloop(100);
-
- dm365_vpss_sync_reset();
-
- writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
- writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
-
- while (1);
- }
-}
-
-static void dm365_wdt_flag_on(void)
-{
- /* VPSS_CLKMD 1:2 */
- clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
- VPSS_CLK_CTL_VPSS_CLKMD);
- writel(0, TMPBUF);
- setbits_le32(TMPSTATUS, FLAG_FLGON);
-}
-
-void dm365_psc_init(void)
-{
- unsigned char i = 0;
- unsigned char lpsc_start;
- unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
- unsigned int PdNum = 0;
-
- lpscmin = 0;
- lpscmax = 2;
-
- for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
- if (lpscgroup == 0) {
- /* Enabling LPSC 3 to 28 SCR first */
- lpsc_start = DAVINCI_LPSC_VPSSMSTR;
- lpsc_end = DAVINCI_LPSC_TIMER1;
- } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
- lpsc_start = DAVINCI_LPSC_CFG5;
- lpsc_end = DAVINCI_LPSC_VPSSMASTER;
- } else {
- lpsc_start = DAVINCI_LPSC_MJCP;
- lpsc_end = DAVINCI_LPSC_HDVICP;
- }
-
- /* NEXT=0x3, Enable LPSC's */
- for (i = lpsc_start; i <= lpsc_end; i++)
- setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
-
- /*
- * Program goctl to start transition sequence for LPSCs
- * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
- * Domain 0 Modules
- */
- writel((1 << PdNum), &dv_psc_regs->ptcmd);
-
- /*
- * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
- */
- while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
- == 0))
- ;
-
- /* Wait for MODSTAT = ENABLE from LPSC's */
- for (i = lpsc_start; i <= lpsc_end; i++)
- while (!((readl(&dv_psc_regs->mdstat[i]) &
- PSC_MD_STATE_MSK) == PSC_ENABLE))
- ;
- }
-}
-
-static void dm365_emif_init(void)
-{
- writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
- writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
-
- setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
-
- writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
-
- return;
-}
-
-void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
- unsigned long value)
-{
- clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
- setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
-}
-
-__attribute__((weak))
-void board_gpio_init(void)
-{
- return;
-}
-
-#if defined(CONFIG_POST)
-int post_log(char *format, ...)
-{
- return 0;
-}
-#endif
-
-void dm36x_lowlevel_init(ulong bootflag)
-{
- struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
- (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
- DAVINCI_UART_CTRL_BASE);
-
- /* Mask all interrupts */
- writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
- writel(0x0, &dv_aintc_regs->eabase);
- writel(0x0, &dv_aintc_regs->eint0);
- writel(0x0, &dv_aintc_regs->eint1);
-
- /* Clear all interrupts */
- writel(0xffffffff, &dv_aintc_regs->fiq0);
- writel(0xffffffff, &dv_aintc_regs->fiq1);
- writel(0xffffffff, &dv_aintc_regs->irq0);
- writel(0xffffffff, &dv_aintc_regs->irq1);
-
- dm365_por_reset();
- dm365_wdt_reset();
-
- /* System PSC setup - enable all */
- dm365_psc_init();
-
- /* Setup Pinmux */
- dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
- dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
- dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
- dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
- dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
-
- /* PLL setup */
- dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
- CONFIG_SYS_DM36x_PLL1_PREDIV);
- dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
- CONFIG_SYS_DM36x_PLL2_PREDIV);
-
- /* GPIO setup */
- board_gpio_init();
-
- NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
- /*
- * Fix Power and Emulation Management Register
- * see sprufh2.pdf page 38 Table 22
- */
- writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
- DAVINCI_UART_PWREMU_MGMT_UTRST),
- &davinci_uart_ctrl_regs->pwremu_mgmt);
-
- puts("ddr init\n");
- dm365_ddr_setup();
-
- puts("emif init\n");
- dm365_emif_init();
-
- dm365_wdt_flag_on();
-
-#if defined(CONFIG_POST)
- /*
- * Do memory tests, calls arch_memory_failure_handle()
- * if error detected.
- */
- memory_post_test(0);
-#endif
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm644x.c b/arch/arm/cpu/arm926ejs/davinci/dm644x.c
deleted file mode 100644
index c58e271..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm644x.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * SoC-specific code for tms320dm644x chips
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-
-#define PINMUX0_EMACEN (1 << 31)
-#define PINMUX0_AECS5 (1 << 11)
-#define PINMUX0_AECS4 (1 << 10)
-
-#define PINMUX1_I2C (1 << 7)
-#define PINMUX1_UART1 (1 << 1)
-#define PINMUX1_UART0 (1 << 0)
-
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_LPSC_UART0);
-
- /* Bringup UART0 out of reset */
- REG(UART0_PWREMU_MGMT) = 0x00006001;
-
- /* Enable UART0 MUX lines */
- REG(PINMUX1) |= PINMUX1_UART0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
- lpsc_on(DAVINCI_LPSC_EMAC);
- lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
- lpsc_on(DAVINCI_LPSC_MDIO);
-
- /* Enable GIO3.3V cells used for EMAC */
- REG(VDD3P3V_PWDN) = 0;
-
- /* Enable EMAC. */
- REG(PINMUX0) |= PINMUX0_EMACEN;
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_LPSC_I2C);
-
- /* Enable I2C pin Mux */
- REG(PINMUX1) |= PINMUX1_I2C;
-}
-#endif
-
-void davinci_errata_workarounds(void)
-{
- /*
- * Workaround for TMS320DM6446 errata 1.3.22:
- * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
- * Revision(s) Affected: 1.3 and earlier
- */
- REG(PSC_SILVER_BULLET) = 0;
-
- /*
- * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
- * as suggested in TMS320DM6446 errata 2.1.2:
- *
- * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
- * low priority modules can occupy the bus and prevent high priority
- * modules like the VPSS from getting the required DDR2 throughput.
- * A hex value of 0x20 should provide a good ARM (cache enabled)
- * performance and still allow good utilization by the VPSS or other
- * modules.
- */
- REG(VBPR) = 0x20;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/dm646x.c b/arch/arm/cpu/arm926ejs/davinci/dm646x.c
deleted file mode 100644
index cfea830..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dm646x.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * SoC-specific code for TMS320DM646x chips
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/hardware.h>
-
-void davinci_enable_uart0(void)
-{
- lpsc_on(DAVINCI_DM646X_LPSC_UART0);
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
- lpsc_on(DAVINCI_DM646X_LPSC_EMAC);
-}
-#endif
-
-#ifdef CONFIG_SYS_I2C_DAVINCI
-void davinci_enable_i2c(void)
-{
- lpsc_on(DAVINCI_DM646X_LPSC_I2C);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/dp83848.c b/arch/arm/cpu/arm926ejs/davinci/dp83848.c
deleted file mode 100644
index 603d507..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/dp83848.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * National Semiconductor DP83848 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <dp83848.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int dp83848_is_phy_connected(int phy_addr)
-{
- u_int16_t id1, id2;
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1))
- return(0);
- if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2))
- return(0);
-
- if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI))
- return(1);
-
- return(0);
-}
-
-int dp83848_get_link_speed(int phy_addr)
-{
- u_int16_t tmp;
- volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR;
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
- return(0);
-
- if (!(tmp & DP83848_LINK_STATUS)) /* link up? */
- return(0);
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp))
- return(0);
-
- /* Speed doesn't matter, there is no setting for it in EMAC... */
- if (tmp & DP83848_DUPLEX) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
- EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
-}
-
-
-int dp83848_init_phy(int phy_addr)
-{
- int ret = 1;
-
- if (!dp83848_get_link_speed(phy_addr)) {
- /* Try another time */
- udelay(100000);
- ret = dp83848_get_link_speed(phy_addr);
- }
-
- /* Disable PHY Interrupts */
- davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
-
- return(ret);
-}
-
-
-int dp83848_auto_negotiate(int phy_addr)
-{
- u_int16_t tmp;
-
-
- if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
- return(0);
-
- /* Restart Auto_negotiation */
- tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */
- tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */
- davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
- /* Set the Auto_negotiation Advertisement Register
- * MII advertising for Next page, 100BaseTxFD and HD,
- * 10BaseTFD and HD, IEEE 802.3
- */
- tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
- DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
- davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
-
-
- /* Read Control Register */
- if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
- return(0);
-
- tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
- davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
- /* Restart Auto_negotiation */
- tmp |= DP83848_RESTART_AUTONEG;
- davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
-
- /*check AutoNegotiate complete */
- udelay(10000);
- if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
- return(0);
-
- if (!(tmp & DP83848_AUTONEG_COMP))
- return(0);
-
- return (dp83848_get_link_speed(phy_addr));
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/et1011c.c b/arch/arm/cpu/arm926ejs/davinci/et1011c.c
deleted file mode 100644
index 9d53875..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/et1011c.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
- *
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
-
-#define MII_PHY_CONFIG_REG 22
-
-/* PHY Config bits */
-#define PHY_SYS_CLK_EN (1 << 4)
-
-int et1011c_get_link_speed(int phy_addr)
-{
- u_int16_t data;
-
- if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
- davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
- /* Enable 125MHz clock sourced from PHY */
- davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
- data | PHY_SYS_CLK_EN);
- return (1);
- }
- return (0);
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c b/arch/arm/cpu/arm926ejs/davinci/ksz8873.c
deleted file mode 100644
index 4af5dd2..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/ksz8873.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Micrel KSZ8873 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2011 Heiko Schocher <hsdenx.de>
- *
- * based on:
- * National Semiconductor DP83848 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <net.h>
-#include <asm/arch/emac_defs.h>
-#include <asm/io.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-int ksz8873_is_phy_connected(int phy_addr)
-{
- u_int16_t dummy;
-
- return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
-}
-
-int ksz8873_get_link_speed(int phy_addr)
-{
- emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
-
- /* we always have a link to the switch, 100 FD */
- writel((EMAC_MACCONTROL_MIIEN_ENABLE |
- EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
- &emac->MACCONTROL);
- return 1;
-}
-
-
-int ksz8873_init_phy(int phy_addr)
-{
- return 1;
-}
-
-
-int ksz8873_auto_negotiate(int phy_addr)
-{
- return dp83848_get_link_speed(phy_addr);
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
deleted file mode 100644
index e916234..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
+++ /dev/null
@@ -1,693 +0,0 @@
-/*
- * Low-level board setup code for TI DaVinci SoC based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Partially based on TI sources, original copyrights follow:
- */
-
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
- *
- * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
- *
- * Modified for DV-EVM board by Swaminathan S, Nov 2005
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-
-#define MDSTAT_STATE 0x3f
-
-.globl lowlevel_init
-lowlevel_init:
-#ifdef CONFIG_SOC_DM644X
-
- /*-------------------------------------------------------*
- * Mask all IRQs by setting all bits in the EINT default *
- *-------------------------------------------------------*/
- mov r1, $0
- ldr r0, =EINT_ENABLE0
- str r1, [r0]
- ldr r0, =EINT_ENABLE1
- str r1, [r0]
-
- /*------------------------------------------------------*
- * Put the GEM in reset *
- *------------------------------------------------------*/
-
- /* Put the GEM in reset */
- ldr r8, PSC_GEM_FLAG_CLEAR
- ldr r6, MDCTL_GEM
- ldr r7, [r6]
- and r7, r7, r8
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x02
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStopGem:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x02
- bne checkStatClkStopGem
-
- /* Check for GEM Reset Completion */
-checkGemStatClkStop:
- ldr r6, MDSTAT_GEM
- ldr r7, [r6]
- ands r7, r7, $0x100
- bne checkGemStatClkStop
-
- /* Do this for enabling a WDT initiated reset this is a workaround
- for a chip bug. Not required under normal situations */
- ldr r6, P1394
- mov r10, $0
- str r10, [r6]
-
- /*------------------------------------------------------*
- * Enable L1 & L2 Memories in Fast mode *
- *------------------------------------------------------*/
- ldr r6, DFT_ENABLE
- mov r10, $0x01
- str r10, [r6]
-
- ldr r6, MMARG_BRF0
- ldr r10, MMARG_BRF0_VAL
- str r10, [r6]
-
- ldr r6, DFT_ENABLE
- mov r10, $0
- str r10, [r6]
-
- /*------------------------------------------------------*
- * DDR2 PLL Initialization *
- *------------------------------------------------------*/
-
- /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
- mov r10, $0
- ldr r6, PLL2_CTL
- ldr r7, PLL_CLKSRC_MASK
- ldr r8, [r6]
- and r8, r8, r7
- mov r9, r10, lsl $8
- orr r8, r8, r9
- str r8, [r6]
-
- /* Select the PLLEN source */
- ldr r7, PLL_ENSRC_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Bypass the PLL */
- ldr r7, PLL_BYPASS_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
- mov r10, $0x20
-WaitPPL2Loop:
- subs r10, r10, $1
- bne WaitPPL2Loop
-
- /* Reset the PLL */
- ldr r7, PLL_RESET_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Power up the PLL */
- ldr r7, PLL_PWRUP_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Enable the PLL from Disable Mode */
- ldr r7, PLL_DISABLE_ENABLE_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Program the PLL Multiplier */
- ldr r6, PLL2_PLLM
- mov r2, $0x17 /* 162 MHz */
- str r2, [r6]
-
- /* Program the PLL2 Divisor Value */
- ldr r6, PLL2_DIV2
- mov r3, $0x01
- str r3, [r6]
-
- /* Program the PLL2 Divisor Value */
- ldr r6, PLL2_DIV1
- mov r4, $0x0b /* 54 MHz */
- str r4, [r6]
-
- /* PLL2 DIV2 MMR */
- ldr r8, PLL2_DIV_MASK
- ldr r6, PLL2_DIV2
- ldr r9, [r6]
- and r8, r8, r9
- mov r9, $0x01
- mov r9, r9, lsl $15
- orr r8, r8, r9
- str r8, [r6]
-
- /* Program the GOSET bit to take new divider values */
- ldr r6, PLL2_PLLCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Wait for Done */
- ldr r6, PLL2_PLLSTAT
-doneLoop_0:
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne doneLoop_0
-
- /* PLL2 DIV1 MMR */
- ldr r8, PLL2_DIV_MASK
- ldr r6, PLL2_DIV1
- ldr r9, [r6]
- and r8, r8, r9
- mov r9, $0x01
- mov r9, r9, lsl $15
- orr r8, r8, r9
- str r8, [r6]
-
- /* Program the GOSET bit to take new divider values */
- ldr r6, PLL2_PLLCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Wait for Done */
- ldr r6, PLL2_PLLSTAT
-doneLoop:
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne doneLoop
-
- /* Wait for PLL to Reset Properly */
- mov r10, $0x218
-ResetPPL2Loop:
- subs r10, r10, $1
- bne ResetPPL2Loop
-
- /* Bring PLL out of Reset */
- ldr r6, PLL2_CTL
- ldr r8, [r6]
- orr r8, r8, $0x08
- str r8, [r6]
-
- /* Wait for PLL to Lock */
- ldr r10, PLL_LOCK_COUNT
-PLL2Lock:
- subs r10, r10, $1
- bne PLL2Lock
-
- /* Enable the PLL */
- ldr r6, PLL2_CTL
- ldr r8, [r6]
- orr r8, r8, $0x01
- str r8, [r6]
-
- /*------------------------------------------------------*
- * Issue Soft Reset to DDR Module *
- *------------------------------------------------------*/
-
- /* Shut down the DDR2 LPSC Module */
- ldr r8, PSC_FLAG_CLEAR
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- and r7, r7, r8
- orr r7, r7, $0x03
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkStop
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x03
- bne checkDDRStatClkStop
-
- /*------------------------------------------------------*
- * Program DDR2 MMRs for 162MHz Setting *
- *------------------------------------------------------*/
-
- /* Program PHY Control Register */
- ldr r6, DDRCTL
- ldr r7, DDRCTL_VAL
- str r7, [r6]
-
- /* Program SDRAM Bank Config Register */
- ldr r6, SDCFG
- ldr r7, SDCFG_VAL
- str r7, [r6]
-
- /* Program SDRAM TIM-0 Config Register */
- ldr r6, SDTIM0
- ldr r7, SDTIM0_VAL_162MHz
- str r7, [r6]
-
- /* Program SDRAM TIM-1 Config Register */
- ldr r6, SDTIM1
- ldr r7, SDTIM1_VAL_162MHz
- str r7, [r6]
-
- /* Program the SDRAM Bank Config Control Register */
- ldr r10, MASK_VAL
- ldr r8, SDCFG
- ldr r9, SDCFG_VAL
- and r9, r9, r10
- str r9, [r8]
-
- /* Program SDRAM SDREF Config Register */
- ldr r6, SDREF
- ldr r7, SDREF_VAL
- str r7, [r6]
-
- /*------------------------------------------------------*
- * Issue Soft Reset to DDR Module *
- *------------------------------------------------------*/
-
- /* Issue a Dummy DDR2 read/write */
- ldr r8, DDR2_START_ADDR
- ldr r7, DUMMY_VAL
- str r7, [r8]
- ldr r7, [r8]
-
- /* Shut down the DDR2 LPSC Module */
- ldr r8, PSC_FLAG_CLEAR
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- and r7, r7, r8
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkStop2:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkStop2
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkStop2:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x01
- bne checkDDRStatClkStop2
-
- /*------------------------------------------------------*
- * Turn DDR2 Controller Clocks On *
- *------------------------------------------------------*/
-
- /* Enable the DDR2 LPSC Module */
- ldr r6, MDCTL_DDR2
- ldr r7, [r6]
- orr r7, r7, $0x03
- str r7, [r6]
-
- /* Enable the Power Domain Transition Command */
- ldr r6, PTCMD
- ldr r7, [r6]
- orr r7, r7, $0x01
- str r7, [r6]
-
- /* Check for Transition Complete(PTSTAT) */
-checkStatClkEn2:
- ldr r6, PTSTAT
- ldr r7, [r6]
- ands r7, r7, $0x01
- bne checkStatClkEn2
-
- /* Check for DDR2 Controller Enable Completion */
-checkDDRStatClkEn2:
- ldr r6, MDSTAT_DDR2
- ldr r7, [r6]
- and r7, r7, $MDSTAT_STATE
- cmp r7, $0x03
- bne checkDDRStatClkEn2
-
- /* DDR Writes and Reads */
- ldr r6, CFGTEST
- mov r3, $0x01
- str r3, [r6]
-
- /*------------------------------------------------------*
- * System PLL Initialization *
- *------------------------------------------------------*/
-
- /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
- mov r2, $0
- ldr r6, PLL1_CTL
- ldr r7, PLL_CLKSRC_MASK
- ldr r8, [r6]
- and r8, r8, r7
- mov r9, r2, lsl $8
- orr r8, r8, r9
- str r8, [r6]
-
- /* Select the PLLEN source */
- ldr r7, PLL_ENSRC_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Bypass the PLL */
- ldr r7, PLL_BYPASS_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
- mov r10, $0x20
-
-WaitLoop:
- subs r10, r10, $1
- bne WaitLoop
-
- /* Reset the PLL */
- ldr r7, PLL_RESET_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Disable the PLL */
- orr r8, r8, $0x10
- str r8, [r6]
-
- /* Power up the PLL */
- ldr r7, PLL_PWRUP_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Enable the PLL from Disable Mode */
- ldr r7, PLL_DISABLE_ENABLE_MASK
- and r8, r8, r7
- str r8, [r6]
-
- /* Program the PLL Multiplier */
- ldr r6, PLL1_PLLM
- mov r3, $0x15 /* For 594MHz */
- str r3, [r6]
-
- /* Wait for PLL to Reset Properly */
- mov r10, $0xff
-
-ResetLoop:
- subs r10, r10, $1
- bne ResetLoop
-
- /* Bring PLL out of Reset */
- ldr r6, PLL1_CTL
- orr r8, r8, $0x08
- str r8, [r6]
-
- /* Wait for PLL to Lock */
- ldr r10, PLL_LOCK_COUNT
-
-PLL1Lock:
- subs r10, r10, $1
- bne PLL1Lock
-
- /* Enable the PLL */
- orr r8, r8, $0x01
- str r8, [r6]
-
- nop
- nop
- nop
- nop
-
- /*------------------------------------------------------*
- * AEMIF configuration for NOR Flash (double check) *
- *------------------------------------------------------*/
- ldr r0, _PINMUX0
- ldr r1, _DEV_SETTING
- str r1, [r0]
-
- ldr r0, WAITCFG
- ldr r1, WAITCFG_VAL
- ldr r2, [r0]
- orr r2, r2, r1
- str r2, [r0]
-
- ldr r0, ACFG3
- ldr r1, ACFG3_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- ldr r0, ACFG4
- ldr r1, ACFG4_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- ldr r0, ACFG5
- ldr r1, ACFG5_VAL
- ldr r2, [r0]
- and r1, r2, r1
- str r1, [r0]
-
- /*--------------------------------------*
- * VTP manual Calibration *
- *--------------------------------------*/
- ldr r0, VTPIOCR
- ldr r1, VTP_MMR0
- str r1, [r0]
-
- ldr r0, VTPIOCR
- ldr r1, VTP_MMR1
- str r1, [r0]
-
- /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
- ldr r10, VTP_LOCK_COUNT
-VTPLock:
- subs r10, r10, $1
- bne VTPLock
-
- ldr r6, DFT_ENABLE
- mov r10, $0x01
- str r10, [r6]
-
- ldr r6, DDRVTPR
- ldr r7, [r6]
- mov r8, r7, LSL #32-10
- mov r8, r8, LSR #32-10 /* grab low 10 bits */
- ldr r7, VTP_RECAL
- orr r8, r7, r8
- ldr r7, VTP_EN
- orr r8, r7, r8
- str r8, [r0]
-
-
- /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
- ldr r10, VTP_LOCK_COUNT
-VTP1Lock:
- subs r10, r10, $1
- bne VTP1Lock
-
- ldr r1, [r0]
- ldr r2, VTP_MASK
- and r2, r1, r2
- str r2, [r0]
-
- ldr r6, DFT_ENABLE
- mov r10, $0
- str r10, [r6]
-
- /*
- * Call board-specific lowlevel init.
- * That MUST be present and THAT returns
- * back to arch calling code with "mov pc, lr."
- */
- b dv_board_init
-
-.ltorg
-
-_PINMUX0:
- .word 0x01c40000 /* Device Configuration Registers */
-_PINMUX1:
- .word 0x01c40004 /* Device Configuration Registers */
-
-_DEV_SETTING:
- .word 0x00000c1f
-
-WAITCFG:
- .word 0x01e00004
-WAITCFG_VAL:
- .word 0
-ACFG3:
- .word 0x01e00014
-ACFG3_VAL:
- .word 0x3ffffffd
-ACFG4:
- .word 0x01e00018
-ACFG4_VAL:
- .word 0x3ffffffd
-ACFG5:
- .word 0x01e0001c
-ACFG5_VAL:
- .word 0x3ffffffd
-
-MDCTL_DDR2:
- .word 0x01c41a34
-MDSTAT_DDR2:
- .word 0x01c41834
-
-PTCMD:
- .word 0x01c41120
-PTSTAT:
- .word 0x01c41128
-
-EINT_ENABLE0:
- .word 0x01c48018
-EINT_ENABLE1:
- .word 0x01c4801c
-
-PSC_FLAG_CLEAR:
- .word 0xffffffe0
-PSC_GEM_FLAG_CLEAR:
- .word 0xfffffeff
-
-/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
-DDRCTL:
- .word 0x200000e4
-DDRCTL_VAL:
- .word 0x50006405
-SDREF:
- .word 0x2000000c
-SDREF_VAL:
- .word 0x000005c3
-SDCFG:
- .word 0x20000008
-SDCFG_VAL:
-#ifdef DDR_4BANKS
- .word 0x00178622
-#elif defined DDR_8BANKS
- .word 0x00178632
-#else
-#error "Unknown DDR configuration!!!"
-#endif
-SDTIM0:
- .word 0x20000010
-SDTIM0_VAL_162MHz:
- .word 0x28923211
-SDTIM1:
- .word 0x20000014
-SDTIM1_VAL_162MHz:
- .word 0x0016c722
-VTPIOCR:
- .word 0x200000f0 /* VTP IO Control register */
-DDRVTPR:
- .word 0x01c42030 /* DDR VPTR MMR */
-VTP_MMR0:
- .word 0x201f
-VTP_MMR1:
- .word 0xa01f
-DFT_ENABLE:
- .word 0x01c4004c
-VTP_LOCK_COUNT:
- .word 0x5b0
-VTP_MASK:
- .word 0xffffdfff
-VTP_RECAL:
- .word 0x08000
-VTP_EN:
- .word 0x02000
-CFGTEST:
- .word 0x80010000
-MASK_VAL:
- .word 0x00000fff
-
-/* GEM Power Up & LPSC Control Register */
-MDCTL_GEM:
- .word 0x01c41a9c
-MDSTAT_GEM:
- .word 0x01c4189c
-
-/* For WDT reset chip bug */
-P1394:
- .word 0x01c41a20
-
-PLL_CLKSRC_MASK:
- .word 0xfffffeff /* Mask the Clock Mode bit */
-PLL_ENSRC_MASK:
- .word 0xffffffdf /* Select the PLLEN source */
-PLL_BYPASS_MASK:
- .word 0xfffffffe /* Put the PLL in BYPASS */
-PLL_RESET_MASK:
- .word 0xfffffff7 /* Put the PLL in Reset Mode */
-PLL_PWRUP_MASK:
- .word 0xfffffffd /* PLL Power up Mask Bit */
-PLL_DISABLE_ENABLE_MASK:
- .word 0xffffffef /* Enable the PLL from Disable */
-PLL_LOCK_COUNT:
- .word 0x2000
-
-/* PLL1-SYSTEM PLL MMRs */
-PLL1_CTL:
- .word 0x01c40900
-PLL1_PLLM:
- .word 0x01c40910
-
-/* PLL2-SYSTEM PLL MMRs */
-PLL2_CTL:
- .word 0x01c40d00
-PLL2_PLLM:
- .word 0x01c40d10
-PLL2_DIV1:
- .word 0x01c40d18
-PLL2_DIV2:
- .word 0x01c40d1c
-PLL2_PLLCMD:
- .word 0x01c40d38
-PLL2_PLLSTAT:
- .word 0x01c40d3c
-PLL2_DIV_MASK:
- .word 0xffff7fff
-
-MMARG_BRF0:
- .word 0x01c42010 /* BRF margin mode 0 (R/W)*/
-MMARG_BRF0_VAL:
- .word 0x00444400
-
-DDR2_START_ADDR:
- .word 0x80000000
-DUMMY_VAL:
- .word 0xa55aa55a
-#else /* CONFIG_SOC_DM644X */
- mov pc, lr
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/lxt972.c b/arch/arm/cpu/arm926ejs/davinci/lxt972.c
deleted file mode 100644
index c482fd9..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/lxt972.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Intel LXT971/LXT972 PHY Driver for TI DaVinci
- * (TMS320DM644x) based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <net.h>
-#include <miiphy.h>
-#include <lxt971a.h>
-#include <asm/arch/emac_defs.h>
-#include "../../../../../drivers/net/davinci_emac.h"
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-
-#ifdef CONFIG_CMD_NET
-
-int lxt972_is_phy_connected(int phy_addr)
-{
- u_int16_t id1, id2;
-
- if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1))
- return(0);
- if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2))
- return(0);
-
- if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0))
- return(1);
-
- return(0);
-}
-
-int lxt972_get_link_speed(int phy_addr)
-{
- u_int16_t stat1, tmp;
- volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
-
- if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
- return(0);
-
- if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */
- return(0);
-
- if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
- return(0);
-
- tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
-
- davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
- /* Read back */
- if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
- return(0);
-
- /* Speed doesn't matter, there is no setting for it in EMAC... */
- if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
- /* set DM644x EMAC for Full Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
- EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
-}
-
-
-int lxt972_init_phy(int phy_addr)
-{
- int ret = 1;
-
- if (!lxt972_get_link_speed(phy_addr)) {
- /* Try another time */
- ret = lxt972_get_link_speed(phy_addr);
- }
-
- /* Disable PHY Interrupts */
- davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
-
- return(ret);
-}
-
-
-int lxt972_auto_negotiate(int phy_addr)
-{
- u_int16_t tmp;
-
- if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
- return(0);
-
- /* Restart Auto_negotiation */
- tmp |= BMCR_ANRESTART;
- davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
-
- /*check AutoNegotiate complete */
- udelay (10000);
- if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
- return(0);
-
- if (!(tmp & BMSR_ANEGCOMPLETE))
- return(0);
-
- return (lxt972_get_link_speed(phy_addr));
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */
diff --git a/arch/arm/cpu/arm926ejs/davinci/misc.c b/arch/arm/cpu/arm926ejs/davinci/misc.c
deleted file mode 100644
index e18bdfc..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/misc.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Miscelaneous DaVinci functions.
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <net.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SPL_BUILD
-int dram_init(void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size(
- (void *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_MAX_RAM_BANK_SIZE);
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
-}
-#endif
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-/*
- * Read ethernet MAC address from EEPROM for DVEVM compatible boards.
- * Returns 1 if found, 0 otherwise.
- */
-int dvevm_read_mac_address(uint8_t *buf)
-{
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
- /* Read MAC address. */
- if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00,
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6))
- goto i2cerr;
-
- /* Check that MAC address is valid. */
- if (!is_valid_ether_addr(buf))
- goto err;
-
- return 1; /* Found */
-
-i2cerr:
- printf("Read from EEPROM @ 0x%02x failed\n",
- CONFIG_SYS_I2C_EEPROM_ADDR);
-err:
-#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
-
- return 0;
-}
-
-/*
- * Set the mii mode as MII or RMII
- */
-#if defined(CONFIG_SOC_DA8XX)
-void davinci_emac_mii_mode_sel(int mode_sel)
-{
- int val;
-
- val = readl(&davinci_syscfg_regs->cfgchip3);
- if (mode_sel == 0)
- val &= ~(1 << 8);
- else
- val |= (1 << 8);
- writel(val, &davinci_syscfg_regs->cfgchip3);
-}
-#endif
-/*
- * If there is no MAC address in the environment, then it will be initialized
- * (silently) from the value in the EEPROM.
- */
-void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr)
-{
- uint8_t env_enetaddr[6];
- int ret;
-
- ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
- if (!ret) {
- /*
- * There is no MAC address in the environment, so we
- * initialize it from the value in the EEPROM.
- */
- debug("### Setting environment from EEPROM MAC address = "
- "\"%pM\"\n",
- env_enetaddr);
- ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
- }
- if (!ret)
- printf("Failed to set mac address from EEPROM: %d\n", ret);
-}
-#endif /* CONFIG_DRIVER_TI_EMAC */
-
-#if defined(CONFIG_SOC_DA8XX)
-#ifndef CONFIG_USE_IRQ
-void irq_init(void)
-{
- /*
- * Mask all IRQs by clearing the global enable and setting
- * the enable clear for all the 90 interrupts.
- */
- writel(0, &davinci_aintc_regs->ger);
-
- writel(0, &davinci_aintc_regs->hier);
-
- writel(0xffffffff, &davinci_aintc_regs->ecr1);
- writel(0xffffffff, &davinci_aintc_regs->ecr2);
- writel(0xffffffff, &davinci_aintc_regs->ecr3);
-}
-#endif
-
-/*
- * Enable PSC for various peripherals.
- */
-int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
- const int n_items)
-{
- int i;
-
- for (i = 0; i < n_items; i++)
- lpsc_on(item[i].lpsc_no);
-
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/davinci/pinmux.c b/arch/arm/cpu/arm926ejs/davinci/pinmux.c
deleted file mode 100644
index e9d8c87..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/pinmux.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * DaVinci pinmux functions.
- *
- * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/arch/davinci_misc.h>
-
-/*
- * Change the setting of a pin multiplexer field.
- *
- * Takes an array of pinmux settings similar to:
- *
- * struct pinmux_config uart_pins[] = {
- * { &davinci_syscfg_regs->pinmux[8], 2, 7 },
- * { &davinci_syscfg_regs->pinmux[9], 2, 0 }
- * };
- *
- * Stepping through the array, each pinmux[n] register has the given value
- * set in the pin mux field specified.
- *
- * The number of pins in the array must be passed (ARRAY_SIZE can provide
- * this value conveniently).
- *
- * Returns 0 if all field numbers and values are in the correct range,
- * else returns -1.
- */
-int davinci_configure_pin_mux(const struct pinmux_config *pins,
- const int n_pins)
-{
- int i;
-
- /* check for invalid pinmux values */
- for (i = 0; i < n_pins; i++) {
- if (pins[i].field >= PIN_MUX_NUM_FIELDS ||
- (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0)
- return -1;
- }
-
- /* configure the pinmuxes */
- for (i = 0; i < n_pins; i++) {
- const int offset = pins[i].field * PIN_MUX_FIELD_SIZE;
- const unsigned int value = pins[i].value << offset;
- const unsigned int mask = PIN_MUX_FIELD_MASK << offset;
- const dv_reg *mux = pins[i].mux;
-
- writel(value | (readl(mux) & (~mask)), mux);
- }
-
- return 0;
-}
-
-/*
- * Configure multiple pinmux resources.
- *
- * Takes an pinmux_resource array of pinmux_config and pin counts:
- *
- * const struct pinmux_resource pinmuxes[] = {
- * PINMUX_ITEM(uart_pins),
- * PINMUX_ITEM(i2c_pins),
- * };
- *
- * The number of items in the array must be passed (ARRAY_SIZE can provide
- * this value conveniently).
- *
- * Each item entry is configured in the defined order. If configuration
- * of any item fails, -1 is returned and none of the following items are
- * configured. On success, 0 is returned.
- */
-int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
- const int n_items)
-{
- int i;
-
- for (i = 0; i < n_items; i++) {
- if (davinci_configure_pin_mux(item[i].pins,
- item[i].n_pins) != 0)
- return -1;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c
deleted file mode 100644
index 8d99e2e..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/psc.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Power and Sleep Controller (PSC) functions.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/*
- * The PSC manages three inputs to a "module" which may be a peripheral or
- * CPU. Those inputs are the module's: clock; reset signal; and sometimes
- * its power domain. For our purposes, we only care whether clock and power
- * are active, and the module is out of reset.
- *
- * DaVinci chips may include two separate power domains: "Always On" and "DSP".
- * Chips without a DSP generally have only one domain.
- *
- * The "Always On" power domain is always on when the chip is on, and is
- * powered by the VDD pins (on DM644X). The majority of DaVinci modules
- * lie within the "Always On" power domain.
- *
- * A separate domain called the "DSP" domain houses the C64x+ and other video
- * hardware such as VICP. In some chips, the "DSP" domain is not always on.
- * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
- */
-
-/* Works on Always On power domain only (no PD argument) */
-static void lpsc_transition(unsigned int id, unsigned int state)
-{
- dv_reg_p mdstat, mdctl, ptstat, ptcmd;
-#ifdef CONFIG_SOC_DA8XX
- struct davinci_psc_regs *psc_regs;
-#endif
-
-#ifndef CONFIG_SOC_DA8XX
- if (id >= DAVINCI_LPSC_GEM)
- return; /* Don't work on DSP Power Domain */
-
- mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
- mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
- ptstat = REG_P(PSC_PTSTAT);
- ptcmd = REG_P(PSC_PTCMD);
-#else
- if (id < DAVINCI_LPSC_PSC1_BASE) {
- if (id >= PSC_PSC0_MODULE_ID_CNT)
- return;
- psc_regs = davinci_psc0_regs;
- mdstat = &psc_regs->psc0.mdstat[id];
- mdctl = &psc_regs->psc0.mdctl[id];
- } else {
- id -= DAVINCI_LPSC_PSC1_BASE;
- if (id >= PSC_PSC1_MODULE_ID_CNT)
- return;
- psc_regs = davinci_psc1_regs;
- mdstat = &psc_regs->psc1.mdstat[id];
- mdctl = &psc_regs->psc1.mdctl[id];
- }
- ptstat = &psc_regs->ptstat;
- ptcmd = &psc_regs->ptcmd;
-#endif
-
- while (readl(ptstat) & 0x01)
- continue;
-
- if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
- return; /* Already in that state */
-
- writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
-
- switch (id) {
-#ifdef CONFIG_SOC_DM644X
- /* Special treatment for some modules as for sprue14 p.7.4.2 */
- case DAVINCI_LPSC_VPSSSLV:
- case DAVINCI_LPSC_EMAC:
- case DAVINCI_LPSC_EMAC_WRAPPER:
- case DAVINCI_LPSC_MDIO:
- case DAVINCI_LPSC_USB:
- case DAVINCI_LPSC_ATA:
- case DAVINCI_LPSC_VLYNQ:
- case DAVINCI_LPSC_UHPI:
- case DAVINCI_LPSC_DDR_EMIF:
- case DAVINCI_LPSC_AEMIF:
- case DAVINCI_LPSC_MMC_SD:
- case DAVINCI_LPSC_MEMSTICK:
- case DAVINCI_LPSC_McBSP:
- case DAVINCI_LPSC_GPIO:
- writel(readl(mdctl) | 0x200, mdctl);
- break;
-#endif
- }
-
- writel(0x01, ptcmd);
-
- while (readl(ptstat) & 0x01)
- continue;
- while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
- continue;
-}
-
-void lpsc_on(unsigned int id)
-{
- lpsc_transition(id, 0x03);
-}
-
-void lpsc_syncreset(unsigned int id)
-{
- lpsc_transition(id, 0x01);
-}
-
-void lpsc_disable(unsigned int id)
-{
- lpsc_transition(id, 0x0);
-}
-
-/* Not all DaVinci chips have a DSP power domain. */
-#ifdef CONFIG_SOC_DM644X
-
-/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-void dsp_on(void)
-{
- int i;
-
- if (REG(PSC_PDSTAT1) & 0x1f)
- return; /* Already on */
-
- REG(PSC_GBLCTL) |= 0x01;
- REG(PSC_PDCTL1) |= 0x01;
- REG(PSC_PDCTL1) &= ~0x100;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
- REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
- REG(PSC_PTCMD) = 0x02;
-
- for (i = 0; i < 100; i++) {
- if (REG(PSC_EPCPR) & 0x02)
- break;
- }
-
- REG(PSC_CHP_SHRTSW) = 0x01;
- REG(PSC_PDCTL1) |= 0x100;
- REG(PSC_EPCCR) = 0x02;
-
- for (i = 0; i < 100; i++) {
- if (!(REG(PSC_PTSTAT) & 0x02))
- break;
- }
-
- REG(PSC_GBLCTL) &= ~0x1f;
-}
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-#endif /* have a DSP */
diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.c b/arch/arm/cpu/arm926ejs/davinci/reset.c
deleted file mode 100644
index 6b0f154..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/reset.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Processor reset using WDT.
- *
- * Copyright (C) 2012 Dmitry Bondar <bond@inmys.ru>
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/timer_defs.h>
-#include <asm/arch/hardware.h>
-
-void reset_cpu(unsigned long a)
-{
- struct davinci_timer *const wdttimer =
- (struct davinci_timer *)DAVINCI_WDOG_BASE;
- writel(0x08, &wdttimer->tgcr);
- writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
- writel(0, &wdttimer->tim12);
- writel(0, &wdttimer->tim34);
- writel(0, &wdttimer->prd12);
- writel(0, &wdttimer->prd34);
- writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr);
- writel(readl(&wdttimer->wdtcr) | 0x4000, &wdttimer->wdtcr);
- writel(0xa5c64000, &wdttimer->wdtcr);
- writel(0xda7e4000, &wdttimer->wdtcr);
- writel(0x4000, &wdttimer->wdtcr);
- while (1)
- /*nothing*/;
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c
deleted file mode 100644
index 49349da..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <config.h>
-#include <spl.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-#include <nand.h>
-#include <asm/arch/dm365_lowlevel.h>
-#include <ns16550.h>
-#include <malloc.h>
-#include <spi_flash.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
-
- NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
-}
-#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
-
-void spl_board_init(void)
-{
-#ifdef CONFIG_SOC_DM365
- dm36x_lowlevel_init(0);
-#endif
-#ifdef CONFIG_SOC_DA8XX
- arch_cpu_init();
-#endif
- preloader_console_init();
-}
-
-u32 spl_boot_mode(void)
-{
- return MMCSD_MODE_RAW;
-}
-
-u32 spl_boot_device(void)
-{
-#ifdef CONFIG_SPL_NAND_SIMPLE
- return BOOT_DEVICE_NAND;
-#elif defined(CONFIG_SPL_SPI_LOAD)
- return BOOT_DEVICE_SPI;
-#elif defined(CONFIG_SPL_MMC_LOAD)
- return BOOT_DEVICE_MMC1;
-#else
- puts("Unknown boot device\n");
- hang();
-#endif
-}
diff --git a/arch/arm/cpu/arm926ejs/davinci/timer.c b/arch/arm/cpu/arm926ejs/davinci/timer.c
deleted file mode 100644
index c7d0652..0000000
--- a/arch/arm/cpu/arm926ejs/davinci/timer.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/timer_defs.h>
-#include <div64.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct davinci_timer * const timer =
- (struct davinci_timer *)CONFIG_SYS_TIMERBASE;
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-#define TIM_CLK_DIV 16
-
-int timer_init(void)
-{
- /* We are using timer34 in unchained 32-bit mode, full speed */
- writel(0x0, &timer->tcr);
- writel(0x0, &timer->tgcr);
- writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
- writel(0x0, &timer->tim34);
- writel(TIMER_LOAD_VAL, &timer->prd34);
- writel(2 << 22, &timer->tcr);
- gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
- gd->arch.timer_reset_value = 0;
-
- return(0);
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
- unsigned long now = readl(&timer->tim34);
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
-
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-ulong get_timer(ulong base)
-{
- unsigned long long timer_diff;
-
- timer_diff = get_ticks() - gd->arch.timer_reset_value;
-
- return lldiv(timer_diff,
- (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long endtime;
-
- endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
- 1000000UL);
- endtime += get_ticks();
-
- while (get_ticks() < endtime)
- ;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gd->arch.timer_rate_hz;
-}
-
-#ifdef CONFIG_HW_WATCHDOG
-static struct davinci_timer * const wdttimer =
- (struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
-
-/*
- * See prufw2.pdf for using Timer as a WDT
- */
-void davinci_hw_watchdog_enable(void)
-{
- writel(0x0, &wdttimer->tcr);
- writel(0x0, &wdttimer->tgcr);
- /* TIMMODE = 2h */
- writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr);
- writel(CONFIG_SYS_WDT_PERIOD_LOW, &wdttimer->prd12);
- writel(CONFIG_SYS_WDT_PERIOD_HIGH, &wdttimer->prd34);
- writel(2 << 22, &wdttimer->tcr);
- writel(0x0, &wdttimer->tim12);
- writel(0x0, &wdttimer->tim34);
- /* set WDEN bit, WDKEY 0xa5c6 */
- writel(0xa5c64000, &wdttimer->wdtcr);
- /* clear counter register */
- writel(0xda7e4000, &wdttimer->wdtcr);
-}
-
-void davinci_hw_watchdog_reset(void)
-{
- writel(0xa5c64000, &wdttimer->wdtcr);
- writel(0xda7e4000, &wdttimer->wdtcr);
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
deleted file mode 100644
index 45c6687..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
+++ /dev/null
@@ -1,88 +0,0 @@
-if KIRKWOOD
-
-choice
- prompt "Marvell Kirkwood board select"
-
-config TARGET_OPENRD
- bool "Marvell OpenRD Board"
-
-config TARGET_MV88F6281GTW_GE
- bool "MV88f6281GTW_GE Board"
-
-config TARGET_RD6281A
- bool "RD6281A Board"
-
-config TARGET_DREAMPLUG
- bool "DreamPlug Board"
-
-config TARGET_GURUPLUG
- bool "GuruPlug Board"
-
-config TARGET_SHEEVAPLUG
- bool "SheevaPlug Board"
-
-config TARGET_LSXL
- bool "lsxl Board"
-
-config TARGET_POGO_E02
- bool "pogo_e02 Board"
-
-config TARGET_DNS325
- bool "dns325 Board"
-
-config TARGET_ICONNECT
- bool "iconnect Board"
-
-config TARGET_TK71
- bool "TK71 Board"
-
-config TARGET_KM_KIRKWOOD
- bool "KM_KIRKWOOD Board"
-
-config TARGET_NET2BIG_V2
- bool "LaCie 2Big Network v2 NAS Board"
-
-config TARGET_NETSPACE_V2
- bool "LaCie netspace_v2 Board"
-
-config TARGET_WIRELESS_SPACE
- bool "LaCie Wireless_space Board"
-
-config TARGET_IB62X0
- bool "ib62x0 Board"
-
-config TARGET_DOCKSTAR
- bool "Dockstar Board"
-
-config TARGET_GOFLEXHOME
- bool "GoFlex Home Board"
-
-config TARGET_NAS220
- bool "BlackArmor NAS220"
-
-endchoice
-
-config SYS_SOC
- default "kirkwood"
-
-source "board/Marvell/openrd/Kconfig"
-source "board/Marvell/mv88f6281gtw_ge/Kconfig"
-source "board/Marvell/rd6281a/Kconfig"
-source "board/Marvell/dreamplug/Kconfig"
-source "board/Marvell/guruplug/Kconfig"
-source "board/Marvell/sheevaplug/Kconfig"
-source "board/buffalo/lsxl/Kconfig"
-source "board/cloudengines/pogo_e02/Kconfig"
-source "board/d-link/dns325/Kconfig"
-source "board/iomega/iconnect/Kconfig"
-source "board/karo/tk71/Kconfig"
-source "board/keymile/km_arm/Kconfig"
-source "board/LaCie/net2big_v2/Kconfig"
-source "board/LaCie/netspace_v2/Kconfig"
-source "board/LaCie/wireless_space/Kconfig"
-source "board/raidsonic/ib62x0/Kconfig"
-source "board/Seagate/dockstar/Kconfig"
-source "board/Seagate/goflexhome/Kconfig"
-source "board/Seagate/nas220/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Makefile b/arch/arm/cpu/arm926ejs/kirkwood/Makefile
deleted file mode 100644
index df4756e..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o
-obj-y += cache.o
-obj-y += mpp.o
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cache.c b/arch/arm/cpu/arm926ejs/kirkwood/cache.c
deleted file mode 100644
index e18a309..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/cache.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (c) 2012 Michael Walle
- * Michael Walle <michael@walle.cc>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/cpu.h>
-
-#define FEROCEON_EXTRA_FEATURE_L2C_EN (1<<22)
-
-void l2_cache_disable()
-{
- u32 ctrl;
-
- ctrl = readfr_extra_feature_reg();
- ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
- writefr_extra_feature_reg(ctrl);
-}
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
deleted file mode 100644
index 4c9d3fd..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/cache.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <mvebu_mmc.h>
-
-void reset_cpu(unsigned long ignored)
-{
- struct kwcpu_registers *cpureg =
- (struct kwcpu_registers *)KW_CPU_REG_BASE;
-
- writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
- &cpureg->rstoutn_mask);
- writel(readl(&cpureg->sys_soft_rst) | 1,
- &cpureg->sys_soft_rst);
- while (1) ;
-}
-
-/*
- * Window Size
- * Used with the Base register to set the address window size and location.
- * Must be programmed from LSB to MSB as sequence of ones followed by
- * sequence of zeros. The number of ones specifies the size of the window in
- * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
- * NOTE: A value of 0x0 specifies 64-KByte size.
- */
-unsigned int kw_winctrl_calcsize(unsigned int sizeval)
-{
- int i;
- unsigned int j = 0;
- u32 val = sizeval >> 1;
-
- for (i = 0; val >= 0x10000; i++) {
- j |= (1 << i);
- val = val >> 1;
- }
- return (0x0000ffff & j);
-}
-
-/*
- * kw_config_adr_windows - Configure address Windows
- *
- * There are 8 address windows supported by Kirkwood Soc to addess different
- * devices. Each window can be configured for size, BAR and remap addr
- * Below configuration is standard for most of the cases
- *
- * If remap function not used, remap_lo must be set as base
- *
- * Reference Documentation:
- * Mbus-L to Mbus Bridge Registers Configuration.
- * (Sec 25.1 and 25.3 of Datasheet)
- */
-int kw_config_adr_windows(void)
-{
- struct kwwin_registers *winregs =
- (struct kwwin_registers *)KW_CPU_WIN_BASE;
-
- /* Window 0: PCIE MEM address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
- KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
-
- writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
- writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
- writel(0x0, &winregs[0].remap_hi);
-
- /* Window 1: PCIE IO address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
- KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
- writel(KW_DEFADR_PCI_IO, &winregs[1].base);
- writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
- writel(0x0, &winregs[1].remap_hi);
-
- /* Window 2: NAND Flash address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
- KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
- writel(KW_DEFADR_NANDF, &winregs[2].base);
- writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
- writel(0x0, &winregs[2].remap_hi);
-
- /* Window 3: SPI Flash address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
- KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
- writel(KW_DEFADR_SPIF, &winregs[3].base);
- writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
- writel(0x0, &winregs[3].remap_hi);
-
- /* Window 4: BOOT Memory address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
- KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
- writel(KW_DEFADR_BOOTROM, &winregs[4].base);
-
- /* Window 5: Security SRAM address space */
- writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
- KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
- writel(KW_DEFADR_SASRAM, &winregs[5].base);
-
- /* Window 6-7: Disabled */
- writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
- writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
-
- return 0;
-}
-
-/*
- * SYSRSTn Duration Counter Support
- *
- * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
- * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
- * The SYSRSTn duration counter is useful for implementing a manufacturer
- * or factory reset. Upon a long reset assertion that is greater than a
- * pre-configured environment variable value for sysrstdelay,
- * The counter value is stored in the SYSRSTn Length Counter Register
- * The counter is based on the 25-MHz reference clock (40ns)
- * It is a 29-bit counter, yielding a maximum counting duration of
- * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
- * it remains at this value until counter reset is triggered by setting
- * bit 31 of KW_REG_SYSRST_CNT
- */
-static void kw_sysrst_action(void)
-{
- int ret;
- char *s = getenv("sysrstcmd");
-
- if (!s) {
- debug("Error.. %s failed, check sysrstcmd\n",
- __FUNCTION__);
- return;
- }
-
- debug("Starting %s process...\n", __FUNCTION__);
- ret = run_command(s, 0);
- if (ret != 0)
- debug("Error.. %s failed\n", __FUNCTION__);
- else
- debug("%s process finished\n", __FUNCTION__);
-}
-
-static void kw_sysrst_check(void)
-{
- u32 sysrst_cnt, sysrst_dly;
- char *s;
-
- /*
- * no action if sysrstdelay environment variable is not defined
- */
- s = getenv("sysrstdelay");
- if (s == NULL)
- return;
-
- /* read sysrstdelay value */
- sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
-
- /* read SysRst Length counter register (bits 28:0) */
- sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
- debug("H/w Rst hold time: %d.%d secs\n",
- sysrst_cnt / SYSRST_CNT_1SEC_VAL,
- sysrst_cnt % SYSRST_CNT_1SEC_VAL);
-
- /* clear the counter for next valid read*/
- writel(1 << 31, KW_REG_SYSRST_CNT);
-
- /*
- * sysrst_action:
- * if H/w Reset key is pressed and hold for time
- * more than sysrst_dly in seconds
- */
- if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
- kw_sysrst_action();
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- char *rev = "??";
- u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
- u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
-
- if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
- printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
- return -1;
- }
-
- switch (revid) {
- case 0:
- if (devid == 0x6281)
- rev = "Z0";
- else if (devid == 0x6282)
- rev = "A0";
- break;
- case 1:
- rev = "A1";
- break;
- case 2:
- rev = "A0";
- break;
- case 3:
- rev = "A1";
- break;
- default:
- break;
- }
-
- printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
- u32 reg;
- struct kwcpu_registers *cpureg =
- (struct kwcpu_registers *)KW_CPU_REG_BASE;
-
- /* Linux expects` the internal registers to be at 0xf1000000 */
- writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
-
- /* Enable and invalidate L2 cache in write through mode */
- writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
- invalidate_l2_cache();
-
- kw_config_adr_windows();
-
-#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
- /*
- * Configures the I/O voltage of the pads connected to Egigabit
- * Ethernet interface to 1.8V
- * By default it is set to 3.3V
- */
- reg = readl(KW_REG_MPP_OUT_DRV_REG);
- reg |= (1 << 7);
- writel(reg, KW_REG_MPP_OUT_DRV_REG);
-#endif
-#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
- /*
- * Set egiga port0/1 in normal functional mode
- * This is required becasue on kirkwood by default ports are in reset mode
- * OS egiga driver may not have provision to set them in normal mode
- * and if u-boot is build without network support, network may fail at OS level
- */
- reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
- reg &= ~(1 << 4); /* Clear PortReset Bit */
- writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
- reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
- reg &= ~(1 << 4); /* Clear PortReset Bit */
- writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
-#endif
-#ifdef CONFIG_KIRKWOOD_PCIE_INIT
- /*
- * Enable PCI Express Port0
- */
- reg = readl(&cpureg->ctrl_stat);
- reg |= (1 << 0); /* Set PEX0En Bit */
- writel(reg, &cpureg->ctrl_stat);
-#endif
- return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-/*
- * SOC specific misc init
- */
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
- volatile u32 temp;
-
- /*CPU streaming & write allocate */
- temp = readfr_extra_feature_reg();
- temp &= ~(1 << 28); /* disable wr alloc */
- writefr_extra_feature_reg(temp);
-
- temp = readfr_extra_feature_reg();
- temp &= ~(1 << 29); /* streaming disabled */
- writefr_extra_feature_reg(temp);
-
- /* L2Cache settings */
- temp = readfr_extra_feature_reg();
- /* Disable L2C pre fetch - Set bit 24 */
- temp |= (1 << 24);
- /* enable L2C - Set bit 22 */
- temp |= (1 << 22);
- writefr_extra_feature_reg(temp);
-
- icache_enable();
- /* Change reset vector to address 0x0 */
- temp = get_cr();
- set_cr(temp & ~CR_V);
-
- /* checks and execute resset to factory event */
- kw_sysrst_check();
-
- return 0;
-}
-#endif /* CONFIG_ARCH_MISC_INIT */
-
-#ifdef CONFIG_MVGBE
-int cpu_eth_init(bd_t *bis)
-{
- mvgbe_initialize(bis);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_MVEBU_MMC
-int board_mmc_init(bd_t *bis)
-{
- mvebu_mmc_init(bis);
- return 0;
-}
-#endif /* CONFIG_MVEBU_MMC */
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
deleted file mode 100644
index 7222504..0000000
--- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/mpp.c
- *
- * MPP functions for Marvell Kirkwood SoCs
- * Referenced from Linux kernel source
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <asm/arch/mpp.h>
-
-static u32 kirkwood_variant(void)
-{
- switch (readl(KW_REG_DEVICE_ID) & 0x03) {
- case 1:
- return MPP_F6192_MASK;
- case 2:
- return MPP_F6281_MASK;
- default:
- debug("MPP setup: unknown kirkwood variant\n");
- return 0;
- }
-}
-
-#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4))
-#define MPP_NR_REGS (1 + MPP_MAX/8)
-
-void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save)
-{
- u32 mpp_ctrl[MPP_NR_REGS];
- unsigned int variant_mask;
- int i;
-
- variant_mask = kirkwood_variant();
- if (!variant_mask)
- return;
-
- debug( "initial MPP regs:");
- for (i = 0; i < MPP_NR_REGS; i++) {
- mpp_ctrl[i] = readl(MPP_CTRL(i));
- debug(" %08x", mpp_ctrl[i]);
- }
- debug("\n");
-
-
- while (*mpp_list) {
- unsigned int num = MPP_NUM(*mpp_list);
- unsigned int sel = MPP_SEL(*mpp_list);
- unsigned int sel_save;
- int shift;
-
- if (num > MPP_MAX) {
- debug("kirkwood_mpp_conf: invalid MPP "
- "number (%u)\n", num);
- continue;
- }
- if (!(*mpp_list & variant_mask)) {
- debug("kirkwood_mpp_conf: requested MPP%u config "
- "unavailable on this hardware\n", num);
- continue;
- }
-
- shift = (num & 7) << 2;
-
- if (mpp_save) {
- sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf;
- *mpp_save = num | (sel_save << 8) | variant_mask;
- mpp_save++;
- }
-
- mpp_ctrl[num / 8] &= ~(0xf << shift);
- mpp_ctrl[num / 8] |= sel << shift;
-
- mpp_list++;
- }
-
- debug(" final MPP regs:");
- for (i = 0; i < MPP_NR_REGS; i++) {
- writel(mpp_ctrl[i], MPP_CTRL(i));
- debug(" %08x", mpp_ctrl[i]);
- }
- debug("\n");
-
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
deleted file mode 100644
index 365892c..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = clock.o reset.o timer.o
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
deleted file mode 100644
index 1f6f66e..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Get the peripheral bus frequency depending on pll pin settings
- */
-ulong get_bus_freq(ulong dummy)
-{
- struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
- MB86R0x_CRG_BASE;
- uint32_t pllmode;
-
- pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE;
-
- if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20)
- return 40000000;
-
- return 41164767;
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
deleted file mode 100644
index 7bd77ff..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * (C) Copyright 2010
- * Matthias Weisser <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-/*
- * Reset the cpu by setting software reset request bit
- */
-void reset_cpu(ulong ignored)
-{
- struct mb86r0x_crg * crg = (struct mb86r0x_crg *)
- MB86R0x_CRG_BASE;
-
- writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr);
- while (1)
- /* NOP */;
- /* Never reached */
-}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
deleted file mode 100644
index bb07819..0000000
--- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2010
- * Matthias Weisser, Graf-Syteco <weisserm@arcor.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <div64.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, TIMER_FREQ);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= TIMER_FREQ;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int timer_init(void)
-{
- struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
- MB86R0x_TIMER_BASE;
- ulong ctrl = readl(&timer->control);
-
- writel(TIMER_LOAD_VAL, &timer->load);
-
- ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S |
- MB86R0x_TIMER_SIZE_32;
-
- writel(ctrl, &timer->control);
-
- /* capture current value time */
- lastdec = readl(&timer->value);
- timestamp = 0; /* start "advancing" time stamp from 0 */
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-unsigned long long get_ticks(void)
-{
- struct mb86r0x_timer * timer = (struct mb86r0x_timer *)
- MB86R0x_TIMER_BASE;
- ulong now = readl(&timer->value);
-
- if (now <= lastdec) {
- /* normal mode (non roll) */
- /* move stamp forward with absolut diff ticks */
- timestamp += lastdec - now;
- } else {
- /* we have rollover of incrementer */
- timestamp += lastdec + TIMER_LOAD_VAL - now;
- }
- lastdec = now;
- return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
- return tick_to_time(get_ticks());
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = usec_to_tick(usec);
- tmp = get_ticks(); /* get current timestamp */
-
- while ((get_ticks() - tmp) < tmo) /* loop till event */
- /*NOP*/;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- ulong tbclk;
-
- tbclk = TIMER_FREQ;
- return tbclk;
-}
diff --git a/arch/arm/cpu/arm926ejs/nomadik/Kconfig b/arch/arm/cpu/arm926ejs/nomadik/Kconfig
deleted file mode 100644
index 265f336..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if ARCH_NOMADIK
-
-choice
- prompt "Nomadik board select"
-
-config NOMADIK_NHK8815
- bool "ST 8815 Nomadik Hardware Kit"
-
-endchoice
-
-config SYS_SOC
- default "nomadik"
-
-source "board/st/nhk8815/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/arm926ejs/nomadik/Makefile b/arch/arm/cpu/arm926ejs/nomadik/Makefile
deleted file mode 100644
index cdf1345..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = timer.o gpio.o
-obj-y += reset.o
diff --git a/arch/arm/cpu/arm926ejs/nomadik/gpio.c b/arch/arm/cpu/arm926ejs/nomadik/gpio.c
deleted file mode 100644
index eff5b2b..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/gpio.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-
-static unsigned long gpio_base[4] = {
- NOMADIK_GPIO0_BASE,
- NOMADIK_GPIO1_BASE,
- NOMADIK_GPIO2_BASE,
- NOMADIK_GPIO3_BASE
-};
-
-enum gpio_registers {
- GPIO_DAT = 0x00, /* data register */
- GPIO_DATS = 0x04, /* data set */
- GPIO_DATC = 0x08, /* data clear */
- GPIO_PDIS = 0x0c, /* pull disable */
- GPIO_DIR = 0x10, /* direction */
- GPIO_DIRS = 0x14, /* direction set */
- GPIO_DIRC = 0x18, /* direction clear */
- GPIO_AFSLA = 0x20, /* alternate function select A */
- GPIO_AFSLB = 0x24, /* alternate function select B */
-};
-
-static inline unsigned long gpio_to_base(int gpio)
-{
- return gpio_base[gpio / 32];
-}
-
-static inline u32 gpio_to_bit(int gpio)
-{
- return 1 << (gpio & 0x1f);
-}
-
-void nmk_gpio_af(int gpio, int alternate_function)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
- u32 afunc, bfunc;
-
- /* alternate function is 0..3, with one bit per register */
- afunc = readl(base + GPIO_AFSLA) & ~bit;
- bfunc = readl(base + GPIO_AFSLB) & ~bit;
- if (alternate_function & 1) afunc |= bit;
- if (alternate_function & 2) bfunc |= bit;
- writel(afunc, base + GPIO_AFSLA);
- writel(bfunc, base + GPIO_AFSLB);
-}
-
-void nmk_gpio_dir(int gpio, int dir)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- if (dir)
- writel(bit, base + GPIO_DIRS);
- else
- writel(bit, base + GPIO_DIRC);
-}
-
-void nmk_gpio_set(int gpio, int val)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- if (val)
- writel(bit, base + GPIO_DATS);
- else
- writel(bit, base + GPIO_DATC);
-}
-
-int nmk_gpio_get(int gpio)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- return readl(base + GPIO_DAT) & bit;
-}
diff --git a/arch/arm/cpu/arm926ejs/nomadik/reset.S b/arch/arm/cpu/arm926ejs/nomadik/reset.S
deleted file mode 100644
index ec95472..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/reset.S
+++ /dev/null
@@ -1,14 +0,0 @@
-#include <config.h>
-/*
- * Processor reset for Nomadik
- */
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r0, =NOMADIK_SRC_BASE /* System and Reset Controller */
- ldr r1, =0x1
- str r1, [r0, #0x18]
-
-_loop_forever:
- b _loop_forever
diff --git a/arch/arm/cpu/arm926ejs/nomadik/timer.c b/arch/arm/cpu/arm926ejs/nomadik/timer.c
deleted file mode 100644
index 775d0b7..0000000
--- a/arch/arm/cpu/arm926ejs/nomadik/timer.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mtu.h>
-
-/*
- * The timer is a decrementer, we'll left it free running at 2.4MHz.
- * We have 2.4 ticks per microsecond and an overflow in almost 30min
- */
-#define TIMER_CLOCK (24 * 100 * 1000)
-#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
-#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
-#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
-#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
-
-/* macro to read the decrementing 32 bit timer as an increasing count */
-#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
-
-/* Configure a free-running, auto-wrap counter with no prescaler */
-int timer_init(void)
-{
- ulong val;
-
- writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
- CONFIG_SYS_TIMERBASE + MTU_CR(0));
-
- /* Reset the timer */
- writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
- /*
- * The load-register isn't really immediate: it changes on clock
- * edges, so we must wait for our newly-written value to appear.
- * Since we might miss reading 0, wait for any change in value.
- */
- val = READ_TIMER();
- while (READ_TIMER() == val)
- ;
-
- return 0;
-}
-
-/* Return how many HZ passed since "base" */
-ulong get_timer(ulong base)
-{
- return TICKS_TO_HZ(READ_TIMER()) - base;
-}
-
-/* Delay x useconds */
-void __udelay(unsigned long usec)
-{
- ulong ini, end;
-
- ini = READ_TIMER();
- end = ini + USEC_TO_COUNT(usec);
- while ((signed)(end - READ_TIMER()) > 0)
- ;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Kconfig b/arch/arm/cpu/arm926ejs/orion5x/Kconfig
deleted file mode 100644
index 5a54262..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if ORION5X
-
-choice
- prompt "Marvell Orion board select"
-
-config TARGET_EDMINIV2
- bool "LaCie Ethernet Disk mini V2"
-
-endchoice
-
-config SYS_SOC
- default "orion5x"
-
-source "board/LaCie/edminiv2/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/arm926ejs/orion5x/Makefile b/arch/arm/cpu/arm926ejs/orion5x/Makefile
deleted file mode 100644
index 546ebcb..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
-#
-# Based on original Kirkwood support which is
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o
-obj-y += dram.o
-obj-y += timer.o
-
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-obj-y += lowlevel_init.o
-endif
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
deleted file mode 100644
index f88db3b..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/cache.h>
-#include <asm/io.h>
-#include <u-boot/md5.h>
-#include <asm/arch/cpu.h>
-
-#define BUFLEN 16
-
-void reset_cpu(unsigned long ignored)
-{
- struct orion5x_cpu_registers *cpureg =
- (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
-
- writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
- &cpureg->rstoutn_mask);
- writel(readl(&cpureg->sys_soft_rst) | 1,
- &cpureg->sys_soft_rst);
- while (1)
- ;
-}
-
-/*
- * Compute Window Size field value from size expressed in bytes
- * Used with the Base register to set the address window size and location.
- * Must be programmed from LSB to MSB as sequence of ones followed by
- * sequence of zeros. The number of ones specifies the size of the window in
- * 64 KiB granularity (e.g., a value of 0x00FF specifies 256 = 16 MiB).
- * NOTES:
- * 1) A sizeval equal to 0x0 specifies 4 GiB.
- * 2) A return value of 0x0 specifies 64 KiB.
- */
-unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
-{
- /*
- * Calculate the number of 64 KiB blocks needed minus one (rounding up).
- * For sizeval > 0 this is equivalent to:
- * sizeval = (u32) ceil((double) sizeval / 65536.0) - 1
- */
- sizeval = (sizeval - 1) >> 16;
-
- /*
- * Propagate 'one' bits to the right by 'oring' them.
- * We need only treat bits 15-0.
- */
- sizeval |= sizeval >> 1; /* 'Or' bit 15 onto bit 14 */
- sizeval |= sizeval >> 2; /* 'Or' bits 15-14 onto bits 13-12 */
- sizeval |= sizeval >> 4; /* 'Or' bits 15-12 onto bits 11-8 */
- sizeval |= sizeval >> 8; /* 'Or' bits 15-8 onto bits 7-0*/
-
- return sizeval;
-}
-
-/*
- * orion5x_config_adr_windows - Configure address Windows
- *
- * There are 8 address windows supported by Orion5x Soc to addess different
- * devices. Each window can be configured for size, BAR and remap addr
- * Below configuration is standard for most of the cases
- *
- * If remap function not used, remap_lo must be set as base
- *
- * NOTES:
- *
- * 1) in order to avoid windows with inconsistent control and base values
- * (which could prevent access to BOOTCS and hence execution from FLASH)
- * always disable window before writing the base value then reenable it
- * by writing the control value.
- *
- * 2) in order to avoid losing access to BOOTCS when disabling window 7,
- * first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
- * then configure windows 6 for its own target.
- *
- * Reference Documentation:
- * Mbus-L to Mbus Bridge Registers Configuration.
- * (Sec 25.1 and 25.3 of Datasheet)
- */
-int orion5x_config_adr_windows(void)
-{
- struct orion5x_win_registers *winregs =
- (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
-
-/* Disable window 0, configure it for its intended target, enable it. */
- writel(0, &winregs[0].ctrl);
- writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
- writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
- writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
- ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
- ORION5X_WIN_ENABLE), &winregs[0].ctrl);
-/* Disable window 1, configure it for its intended target, enable it. */
- writel(0, &winregs[1].ctrl);
- writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
- writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
- writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
- ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
- ORION5X_WIN_ENABLE), &winregs[1].ctrl);
-/* Disable window 2, configure it for its intended target, enable it. */
- writel(0, &winregs[2].ctrl);
- writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
- ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
- ORION5X_WIN_ENABLE), &winregs[2].ctrl);
-/* Disable window 3, configure it for its intended target, enable it. */
- writel(0, &winregs[3].ctrl);
- writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
- ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
- ORION5X_WIN_ENABLE), &winregs[3].ctrl);
-/* Disable window 4, configure it for its intended target, enable it. */
- writel(0, &winregs[4].ctrl);
- writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
- ORION5X_WIN_ENABLE), &winregs[4].ctrl);
-/* Disable window 5, configure it for its intended target, enable it. */
- writel(0, &winregs[5].ctrl);
- writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
- ORION5X_WIN_ENABLE), &winregs[5].ctrl);
-/* Disable window 6, configure it for FLASH, enable it. */
- writel(0, &winregs[6].ctrl);
- writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
- ORION5X_WIN_ENABLE), &winregs[6].ctrl);
-/* Disable window 7, configure it for FLASH, enable it. */
- writel(0, &winregs[7].ctrl);
- writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
- ORION5X_WIN_ENABLE), &winregs[7].ctrl);
-/* Disable window 6, configure it for its intended target, enable it. */
- writel(0, &winregs[6].ctrl);
- writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
- ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
- ORION5X_WIN_ENABLE), &winregs[6].ctrl);
-
- return 0;
-}
-
-/*
- * Orion5x identification is done through PCIE space.
- */
-
-u32 orion5x_device_id(void)
-{
- return readl(PCIE_DEV_ID_OFF) >> 16;
-}
-
-u32 orion5x_device_rev(void)
-{
- return readl(PCIE_DEV_REV_OFF) & 0xff;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-
-/* Display device and revision IDs.
- * This function must cover all known device/revision
- * combinations, not only the one for which u-boot is
- * compiled; this way, one can identify actual HW in
- * case of a mismatch.
- */
-int print_cpuinfo(void)
-{
- char dev_str[7]; /* room enough for 0x0000 plus null byte */
- char rev_str[5]; /* room enough for 0x00 plus null byte */
- char *dev_name = NULL;
- char *rev_name = NULL;
-
- u32 dev = orion5x_device_id();
- u32 rev = orion5x_device_rev();
-
- if (dev == MV88F5181_DEV_ID) {
- dev_name = "MV88F5181";
- if (rev == MV88F5181_REV_B1)
- rev_name = "B1";
- else if (rev == MV88F5181L_REV_A1) {
- dev_name = "MV88F5181L";
- rev_name = "A1";
- } else if (rev == MV88F5181L_REV_A0) {
- dev_name = "MV88F5181L";
- rev_name = "A0";
- }
- } else if (dev == MV88F5182_DEV_ID) {
- dev_name = "MV88F5182";
- if (rev == MV88F5182_REV_A2)
- rev_name = "A2";
- } else if (dev == MV88F5281_DEV_ID) {
- dev_name = "MV88F5281";
- if (rev == MV88F5281_REV_D2)
- rev_name = "D2";
- else if (rev == MV88F5281_REV_D1)
- rev_name = "D1";
- else if (rev == MV88F5281_REV_D0)
- rev_name = "D0";
- } else if (dev == MV88F6183_DEV_ID) {
- dev_name = "MV88F6183";
- if (rev == MV88F6183_REV_B0)
- rev_name = "B0";
- }
- if (dev_name == NULL) {
- sprintf(dev_str, "0x%04x", dev);
- dev_name = dev_str;
- }
- if (rev_name == NULL) {
- sprintf(rev_str, "0x%02x", rev);
- rev_name = rev_str;
- }
-
- printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
- /* Enable and invalidate L2 cache in write through mode */
- invalidate_l2_cache();
-
- orion5x_config_adr_windows();
-
- return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-/*
- * SOC specific misc init
- */
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
- u32 temp;
-
- /*CPU streaming & write allocate */
- temp = readfr_extra_feature_reg();
- temp &= ~(1 << 28); /* disable wr alloc */
- writefr_extra_feature_reg(temp);
-
- temp = readfr_extra_feature_reg();
- temp &= ~(1 << 29); /* streaming disabled */
- writefr_extra_feature_reg(temp);
-
- /* L2Cache settings */
- temp = readfr_extra_feature_reg();
- /* Disable L2C pre fetch - Set bit 24 */
- temp |= (1 << 24);
- /* enable L2C - Set bit 22 */
- temp |= (1 << 22);
- writefr_extra_feature_reg(temp);
-
- icache_enable();
- /* Change reset vector to address 0x0 */
- temp = get_cr();
- set_cr(temp & ~CR_V);
-
- /* Set CPIOs and MPPs - values provided by board
- include file */
- writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
- writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
- writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
- writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
- writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
- writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
-
- /* initialize timer */
- timer_init_r();
- return 0;
-}
-#endif /* CONFIG_ARCH_MISC_INIT */
-
-#ifdef CONFIG_MVGBE
-int cpu_eth_init(bd_t *bis)
-{
- mvgbe_initialize(bis);
- return 0;
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c
deleted file mode 100644
index 9ed93d2..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/dram.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/arch/cpu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * orion5x_sdram_bar - reads SDRAM Base Address Register
- */
-u32 orion5x_sdram_bar(enum memory_bank bank)
-{
- struct orion5x_ddr_addr_decode_registers *winregs =
- (struct orion5x_ddr_addr_decode_registers *)
- ORION5X_DRAM_BASE;
-
- u32 result = 0;
- u32 enable = 0x01 & winregs[bank].size;
-
- if ((!enable) || (bank > BANK3))
- return 0;
-
- result = winregs[bank].base;
- return result;
-}
-int dram_init (void)
-{
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size(
- (long *) orion5x_sdram_bar(0),
- CONFIG_MAX_RAM_BANK_SIZE);
- return 0;
-}
-
-void dram_init_banksize (void)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
- gd->bd->bi_dram[i].size = get_ram_size(
- (long *) (gd->bd->bi_dram[i].start),
- CONFIG_MAX_RAM_BANK_SIZE);
- }
-}
diff --git a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S b/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
deleted file mode 100644
index 4dacc29..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include "asm/arch/orion5x.h"
-
-/*
- * Configuration values for SDRAM access setup
- */
-
-#define SDRAM_CONFIG 0x3148400
-#define SDRAM_MODE 0x62
-#define SDRAM_CONTROL 0x4041000
-#define SDRAM_TIME_CTRL_LOW 0x11602220
-#define SDRAM_TIME_CTRL_HI 0x40c
-#define SDRAM_OPEN_PAGE_EN 0x0
-/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
-#define SDRAM_BANK0_SIZE 0x3ff0001
-#define SDRAM_ADDR_CTRL 0x10
-
-#define SDRAM_OP_NOP 0x05
-#define SDRAM_OP_SETMODE 0x03
-
-#define SDRAM_PAD_CTRL_WR_EN 0x80000000
-#define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
-#define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
-#define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
-
-/*
- * For Guideline MEM-3 - Drive Strength value
- */
-
-#define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
-#define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
-
-/*
- * For Guideline MEM-4 - DQS Reference Delay Tuning
- */
-
-#define MSAR_ARMDDRCLCK_MASK 0x000000f0
-#define MSAR_ARMDDRCLCK_H_MASK 0x00000100
-
-#define MSAR_ARMDDRCLCK_333_167 0x00000000
-#define MSAR_ARMDDRCLCK_500_167 0x00000030
-#define MSAR_ARMDDRCLCK_667_167 0x00000060
-#define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
-#define MSAR_ARMDDRCLCK_400_200 0x00000010
-#define MSAR_ARMDDRCLCK_600_200 0x00000050
-#define MSAR_ARMDDRCLCK_800_200 0x00000070
-
-#define FTDLL_DDR1_166MHZ 0x0047F001
-
-#define FTDLL_DDR1_200MHZ 0x0044D001
-
-/*
- * Low-level init happens right after start.S has switched to SVC32,
- * flushed and disabled caches and disabled MMU. We're still running
- * from the boot chip select, so the first thing we should do is set
- * up RAM for us to relocate into.
- */
-
-.globl lowlevel_init
-
-lowlevel_init:
-
- /* Use 'r4 as the base for internal register accesses */
- ldr r4, =ORION5X_REGS_PHY_BASE
-
- /* move internal registers from the default 0xD0000000
- * to their intended location, defined by SoC */
- ldr r3, =0xD0000000
- add r3, r3, #0x20000
- str r4, [r3, #0x80]
-
- /* Use R3 as the base for DRAM registers */
- add r3, r4, #0x01000
-
- /*DDR SDRAM Initialization Control */
- ldr r6, =0x00000001
- str r6, [r3, #0x480]
-
- /* Use R3 as the base for PCI registers */
- add r3, r4, #0x31000
-
- /* Disable arbiter */
- ldr r6, =0x00000030
- str r6, [r3, #0xd00]
-
- /* Use R3 as the base for DRAM registers */
- add r3, r4, #0x01000
-
- /* set all dram windows to 0 */
- mov r6, #0
- str r6, [r3, #0x504]
- str r6, [r3, #0x50C]
- str r6, [r3, #0x514]
- str r6, [r3, #0x51C]
-
- /* 1) Configure SDRAM */
- ldr r6, =SDRAM_CONFIG
- str r6, [r3, #0x400]
-
- /* 2) Set SDRAM Control reg */
- ldr r6, =SDRAM_CONTROL
- str r6, [r3, #0x404]
-
- /* 3) Write SDRAM address control register */
- ldr r6, =SDRAM_ADDR_CTRL
- str r6, [r3, #0x410]
-
- /* 4) Write SDRAM bank 0 size register */
- ldr r6, =SDRAM_BANK0_SIZE
- str r6, [r3, #0x504]
- /* keep other banks disabled */
-
- /* 5) Write SDRAM open pages control register */
- ldr r6, =SDRAM_OPEN_PAGE_EN
- str r6, [r3, #0x414]
-
- /* 6) Write SDRAM timing Low register */
- ldr r6, =SDRAM_TIME_CTRL_LOW
- str r6, [r3, #0x408]
-
- /* 7) Write SDRAM timing High register */
- ldr r6, =SDRAM_TIME_CTRL_HI
- str r6, [r3, #0x40C]
-
- /* 8) Write SDRAM mode register */
- /* The CPU must not attempt to change the SDRAM Mode register setting */
- /* prior to DRAM controller completion of the DRAM initialization */
- /* sequence. To guarantee this restriction, it is recommended that */
- /* the CPU sets the SDRAM Operation register to NOP command, performs */
- /* read polling until the register is back in Normal operation value, */
- /* and then sets SDRAM Mode register to its new value. */
-
- /* 8.1 write 'nop' to SDRAM operation */
- ldr r6, =SDRAM_OP_NOP
- str r6, [r3, #0x418]
-
- /* 8.2 poll SDRAM operation until back in 'normal' mode. */
-1:
- ldr r6, [r3, #0x418]
- cmp r6, #0
- bne 1b
-
- /* 8.3 Now its safe to write new value to SDRAM Mode register */
- ldr r6, =SDRAM_MODE
- str r6, [r3, #0x41C]
-
- /* 8.4 Set new mode */
- ldr r6, =SDRAM_OP_SETMODE
- str r6, [r3, #0x418]
-
- /* 8.5 poll SDRAM operation until back in 'normal' mode. */
-2:
- ldr r6, [r3, #0x418]
- cmp r6, #0
- bne 2b
-
- /* DDR SDRAM Address/Control Pads Calibration */
- ldr r6, [r3, #0x4C0]
-
- /* Set Bit [31] to make the register writable */
- orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
- str r6, [r3, #0x4C0]
-
- bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
- bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
- bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
- bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
-
- /* Get the final N locked value of driving strength [22:17] */
- mov r1, r6
- mov r1, r1, LSL #9
- mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
- orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
-
- /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
- orr r6, r6, r1
- str r6, [r3, #0x4C0]
-
- /* DDR SDRAM Data Pads Calibration */
- ldr r6, [r3, #0x4C4]
-
- /* Set Bit [31] to make the register writable */
- orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
- str r6, [r3, #0x4C4]
-
- bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
- bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
- bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
- bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
-
- /* Get the final N locked value of driving strength [22:17] */
- mov r1, r6
- mov r1, r1, LSL #9
- mov r1, r1, LSR #26
- orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
-
- /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
- orr r6, r6, r1
-
- str r6, [r3, #0x4C4]
-
- /* Implement Guideline (GL# MEM-3) Drive Strength Value */
- /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
-
- ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
-
- /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
- ldr r6, [r3, #0x4C0]
- orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
- str r6, [r3, #0x4C0]
-
- /* Correct strength and disable writes again */
- bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
- bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
- orr r6, r6, r1
- str r6, [r3, #0x4C0]
-
- /* Enable writes to DDR SDRAM Data Pads Calibration register */
- ldr r6, [r3, #0x4C4]
- orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
- str r6, [r3, #0x4C4]
-
- /* Correct strength and disable writes again */
- bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
- bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
- orr r6, r6, r1
- str r6, [r3, #0x4C4]
-
- /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
- /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
-
- /* Get the "sample on reset" register for the DDR frequancy */
- ldr r3, =0x10000
- ldr r6, [r3, #0x010]
- ldr r1, =MSAR_ARMDDRCLCK_MASK
- and r1, r6, r1
-
- ldr r6, =FTDLL_DDR1_166MHZ
- cmp r1, #MSAR_ARMDDRCLCK_333_167
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_500_167
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_667_167
- beq 3f
-
- ldr r6, =FTDLL_DDR1_200MHZ
- cmp r1, #MSAR_ARMDDRCLCK_400_200_1
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_400_200
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_600_200
- beq 3f
- cmp r1, #MSAR_ARMDDRCLCK_800_200
- beq 3f
-
- ldr r6, =0
-
-3:
- /* Use R3 as the base for DRAM registers */
- add r3, r4, #0x01000
-
- ldr r2, [r3, #0x484]
- orr r2, r2, r6
- str r2, [r3, #0x484]
-
- /* Return to U-boot via saved link register */
- mov pc, lr
diff --git a/arch/arm/cpu/arm926ejs/orion5x/timer.c b/arch/arm/cpu/arm926ejs/orion5x/timer.c
deleted file mode 100644
index ec4f6be..0000000
--- a/arch/arm/cpu/arm926ejs/orion5x/timer.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Based on original Kirkwood support which is
- * Copyright (C) Marvell International Ltd. and its affiliates
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#define UBOOT_CNTR 0 /* counter to use for uboot timer */
-
-/* Timer reload and current value registers */
-struct orion5x_tmr_val {
- u32 reload; /* Timer reload reg */
- u32 val; /* Timer value reg */
-};
-
-/* Timer registers */
-struct orion5x_tmr_registers {
- u32 ctrl; /* Timer control reg */
- u32 pad[3];
- struct orion5x_tmr_val tmr[2];
- u32 wdt_reload;
- u32 wdt_val;
-};
-
-struct orion5x_tmr_registers *orion5x_tmr_regs =
- (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
-
-/*
- * ARM Timers Registers Map
- */
-#define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
-#define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
-#define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
-
-/*
- * ARM Timers Control Register
- * CPU_TIMERS_CTRL_REG (CTCR)
- */
-#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
-#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
-#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-
-#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
-#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-
-/*
- * ARM Timer\Watchdog Reload Register
- * CNTMR_RELOAD_REG (TRR)
- */
-#define TRG_ARM_TIMER_REL_OFFS 0
-#define TRG_ARM_TIMER_REL_MASK 0xffffffff
-
-/*
- * ARM Timer\Watchdog Register
- * CNTMR_VAL_REG (TVRG)
- */
-#define TVR_ARM_TIMER_OFFS 0
-#define TVR_ARM_TIMER_MASK 0xffffffff
-#define TVR_ARM_TIMER_MAX 0xffffffff
-#define TIMER_LOAD_VAL 0xffffffff
-
-static inline ulong read_timer(void)
-{
- return readl(CNTMR_VAL_REG(UBOOT_CNTR))
- / (CONFIG_SYS_TCLK / 1000);
-}
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec +
- (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-static inline ulong uboot_cntr_val(void)
-{
- return readl(CNTMR_VAL_REG(UBOOT_CNTR));
-}
-
-void __udelay(unsigned long usec)
-{
- uint current;
- ulong delayticks;
-
- current = uboot_cntr_val();
- delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
-
- if (current < delayticks) {
- delayticks -= current;
- while (uboot_cntr_val() < current)
- ;
- while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
- ;
- } else {
- while (uboot_cntr_val() > (current - delayticks))
- ;
- }
-}
-
-/*
- * init the counter
- */
-int timer_init(void)
-{
- unsigned int cntmrctrl;
-
- /* load value into timer */
- writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
- writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
-
- /* enable timer in auto reload mode */
- cntmrctrl = readl(CNTMR_CTRL_REG);
- cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
- cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
- writel(cntmrctrl, CNTMR_CTRL_REG);
- return 0;
-}
-
-void timer_init_r(void)
-{
- /* init the timestamp and lastdec value */
- lastdec = read_timer();
- timestamp = 0;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile
deleted file mode 100644
index 988341f..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2011
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Lei Wen <leiwen@marvell.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o timer.o dram.o
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
deleted file mode 100644
index 4e2a177..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
-#define SET_MRVL_ID (1<<8)
-#define L2C_RAM_SEL (1<<4)
-
-int arch_cpu_init(void)
-{
- u32 val;
- struct panthcpu_registers *cpuregs =
- (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
- struct panthapb_registers *apbclkres =
- (struct panthapb_registers*) PANTHEON_APBC_BASE;
-
- struct panthmpmu_registers *mpmu =
- (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
-
- struct panthapmu_registers *apmu =
- (struct panthapmu_registers *) PANTHEON_APMU_BASE;
-
- /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
- val = readl(&cpuregs->cpu_conf);
- val = val | SET_MRVL_ID;
- writel(val, &cpuregs->cpu_conf);
-
- /* Turn on clock gating (PMUM_CCGR) */
- writel(0xFFFFFFFF, &mpmu->ccgr);
-
- /* Turn on clock gating (PMUM_ACGR) */
- writel(0xFFFFFFFF, &mpmu->acgr);
-
- /* Turn on uart2 clock */
- writel(UARTCLK14745KHZ, &apbclkres->uart0);
-
- /* Enable GPIO clock */
- writel(APBC_APBCLK, &apbclkres->gpio);
-
-#ifdef CONFIG_I2C_MV
- /* Enable I2C clock */
- writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
- writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
-#endif
-
-#ifdef CONFIG_MV_SDHCI
- /* Enable mmc clock */
- writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
- &apmu->sd1);
- writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
- &apmu->sd3);
-#endif
-
- icache_enable();
-
- return 0;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- u32 id;
- struct panthcpu_registers *cpuregs =
- (struct panthcpu_registers*) PANTHEON_CPU_BASE;
-
- id = readl(&cpuregs->chip_id);
- printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
- return 0;
-}
-#endif
-
-#ifdef CONFIG_I2C_MV
-void i2c_clk_enable(void)
-{
-}
-#endif
diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c
deleted file mode 100644
index f77e3d0..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/dram.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>,
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pantheon.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Pantheon DRAM controller supports upto 8 banks
- * for chip select 0 and 1
- */
-
-/*
- * DDR Memory Control Registers
- * Refer Datasheet 4.4
- */
-struct panthddr_map_registers {
- u32 cs; /* Memory Address Map Register -CS */
- u32 pad[3];
-};
-
-struct panthddr_registers {
- u8 pad[0x100 - 0x000];
- struct panthddr_map_registers mmap[2];
-};
-
-/*
- * panth_sdram_base - reads SDRAM Base Address Register
- */
-u32 panth_sdram_base(int chip_sel)
-{
- struct panthddr_registers *ddr_regs =
- (struct panthddr_registers *)PANTHEON_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
- return result;
-}
-
-/*
- * panth_sdram_size - reads SDRAM size
- */
-u32 panth_sdram_size(int chip_sel)
-{
- struct panthddr_registers *ddr_regs =
- (struct panthddr_registers *)PANTHEON_DRAM_BASE;
- u32 result = 0;
- u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
-
- if (!CS_valid)
- return 0;
-
- result = readl(&ddr_regs->mmap[chip_sel].cs);
- result = (result >> 16) & 0xF;
- if (result < 0x7) {
- printf("Unknown DRAM Size\n");
- return -1;
- } else {
- return ((0x8 << (result - 0x7)) * 1024 * 1024);
- }
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
- int i;
-
- gd->ram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = panth_sdram_base(i);
- gd->bd->bi_dram[i].size = panth_sdram_size(i);
- /*
- * It is assumed that all memory banks are consecutive
- * and without gaps.
- * If the gap is found, ram_size will be reported for
- * consecutive memory only
- */
- if (gd->bd->bi_dram[i].start != gd->ram_size)
- break;
-
- gd->ram_size += gd->bd->bi_dram[i].size;
-
- }
-
- for (; i < CONFIG_NR_DRAM_BANKS; i++) {
- /*
- * If above loop terminated prematurely, we need to set
- * remaining banks' start address & size as 0. Otherwise other
- * u-boot functions and Linux kernel gets wrong values which
- * could result in crash
- */
- gd->bd->bi_dram[i].start = 0;
- gd->bd->bi_dram[i].size = 0;
- }
- return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
- dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
deleted file mode 100644
index 6382d3b..0000000
--- a/arch/arm/cpu/arm926ejs/pantheon/timer.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/pantheon.h>
-
-/*
- * Timer registers
- * Refer 6.2.9 in Datasheet
- */
-struct panthtmr_registers {
- u32 clk_ctrl; /* Timer clk control reg */
- u32 match[9]; /* Timer match registers */
- u32 count[3]; /* Timer count registers */
- u32 status[3];
- u32 ie[3];
- u32 preload[3]; /* Timer preload value */
- u32 preload_ctrl[3];
- u32 wdt_match_en;
- u32 wdt_match_r;
- u32 wdt_val;
- u32 wdt_sts;
- u32 icr[3];
- u32 wdt_icr;
- u32 cer; /* Timer count enable reg */
- u32 cmr;
- u32 ilr[3];
- u32 wcr;
- u32 wfar;
- u32 wsar;
- u32 cvwr[3];
-};
-
-#define TIMER 0 /* Use TIMER 0 */
-/* Each timer has 3 match registers */
-#define MATCH_CMP(x) ((3 * TIMER) + x)
-#define TIMER_LOAD_VAL 0xffffffff
-#define COUNT_RD_REQ 0x1
-
-DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
-
-/*
- * For preventing risk of instability in reading counter value,
- * first set read request to register cvwr and then read same
- * register after it captures counter value.
- */
-ulong read_timer(void)
-{
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
- volatile int loop=100;
- ulong val;
-
- writel(COUNT_RD_REQ, &panthtimers->cvwr);
- while (loop--)
- val = readl(&panthtimers->cvwr);
-
- /*
- * This stop gcc complain and prevent loop mistake init to 0
- */
- val = readl(&panthtimers->cvwr);
-
- return val;
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (now >= gd->arch.tbl) {
- /* normal mode */
- gd->arch.tbu += now - gd->arch.tbl;
- } else {
- /* we have an overflow ... */
- gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
- }
- gd->arch.tbl = now;
-
- return gd->arch.tbu;
-}
-
-ulong get_timer(ulong base)
-{
- return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
- base);
-}
-
-void __udelay(unsigned long usec)
-{
- ulong delayticks;
- ulong endtime;
-
- delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
- endtime = get_timer_masked() + delayticks;
-
- while (get_timer_masked() < endtime)
- ;
-}
-
-/*
- * init the Timer
- */
-int timer_init(void)
-{
- struct panthapb_registers *apb1clkres =
- (struct panthapb_registers *) PANTHEON_APBC_BASE;
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
-
- /* Enable Timer clock at 3.25 MHZ */
- writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
-
- /* load value into timer */
- writel(0x0, &panthtimers->clk_ctrl);
- /* Use Timer 0 Match Resiger 0 */
- writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
- /* Preload value is 0 */
- writel(0x0, &panthtimers->preload[TIMER]);
- /* Enable match comparator 0 for Timer 0 */
- writel(0x1, &panthtimers->preload_ctrl[TIMER]);
-
- /* Enable timer 0 */
- writel(0x1, &panthtimers->cer);
- /* init the gd->arch.tbu and gd->arch.tbl value */
- gd->arch.tbl = read_timer();
- gd->arch.tbu = 0;
-
- return 0;
-}
-
-#define MPMU_APRR_WDTR (1<<4)
-#define TMR_WFAR 0xbaba /* WDT Register First key */
-#define TMP_WSAR 0xeb10 /* WDT Register Second key */
-
-/*
- * This function uses internal Watchdog Timer
- * based reset mechanism.
- * Steps to write watchdog registers (protected access)
- * 1. Write key value to TMR_WFAR reg.
- * 2. Write key value to TMP_WSAR reg.
- * 3. Perform write operation.
- */
-void reset_cpu (unsigned long ignored)
-{
- struct panthmpmu_registers *mpmu =
- (struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
- struct panthtmr_registers *panthtimers =
- (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
- u32 val;
-
- /* negate hardware reset to the WDT after system reset */
- val = readl(&mpmu->aprr);
- val = val | MPMU_APRR_WDTR;
- writel(val, &mpmu->aprr);
-
- /* reset/enable WDT clock */
- writel(APBC_APBCLK, &mpmu->wdtpcr);
-
- /* clear previous WDT status */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0, &panthtimers->wdt_sts);
-
- /* set match counter */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0xf, &panthtimers->wdt_match_r);
-
- /* enable WDT reset */
- writel(TMR_WFAR, &panthtimers->wfar);
- writel(TMP_WSAR, &panthtimers->wsar);
- writel(0x3, &panthtimers->wdt_match_en);
-
- /*enable functional WDT clock */
- writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/arm926ejs/versatile/Kconfig b/arch/arm/cpu/arm926ejs/versatile/Kconfig
deleted file mode 100644
index d2e76f4..0000000
--- a/arch/arm/cpu/arm926ejs/versatile/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if ARCH_VERSATILE
-
-config SYS_BOARD
- default "versatile"
-
-config SYS_VENDOR
- default "armltd"
-
-config SYS_SOC
- default "versatile"
-
-config SYS_CONFIG_NAME
- default "versatile"
-
-endif
diff --git a/arch/arm/cpu/arm926ejs/versatile/Makefile b/arch/arm/cpu/arm926ejs/versatile/Makefile
deleted file mode 100644
index 907f516..0000000
--- a/arch/arm/cpu/arm926ejs/versatile/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = timer.o
-obj-y += reset.o
diff --git a/arch/arm/cpu/arm926ejs/versatile/reset.S b/arch/arm/cpu/arm926ejs/versatile/reset.S
deleted file mode 100644
index 1c557b0..0000000
--- a/arch/arm/cpu/arm926ejs/versatile/reset.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * armboot - Startup Code for ARM926EJS CPU-core
- *
- * Copyright (c) 2003 Texas Instruments
- *
- * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
- * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
- * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
- * Copyright (c) 2003 Kshitij <kshitij@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r1, rstctl1 /* get clkm1 reset ctl */
- mov r3, #0x0
- strh r3, [r1] /* clear it */
- mov r3, #0x8
- strh r3, [r1] /* force dsp+arm reset */
-_loop_forever:
- b _loop_forever
-
-rstctl1:
- .word 0xfffece10
diff --git a/arch/arm/cpu/arm926ejs/versatile/timer.c b/arch/arm/cpu/arm926ejs/versatile/timer.c
deleted file mode 100644
index 5d694d8..0000000
--- a/arch/arm/cpu/arm926ejs/versatile/timer.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#define TIMER_ENABLE (1 << 7)
-#define TIMER_MODE_MSK (1 << 6)
-#define TIMER_MODE_FR (0 << 6)
-#define TIMER_MODE_PD (1 << 6)
-
-#define TIMER_INT_EN (1 << 5)
-#define TIMER_PRS_MSK (3 << 2)
-#define TIMER_PRS_8S (1 << 3)
-#define TIMER_SIZE_MSK (1 << 2)
-#define TIMER_ONE_SHT (1 << 0)
-
-int timer_init (void)
-{
- ulong tmr_ctrl_val;
-
- /* 1st disable the Timer */
- tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
- tmr_ctrl_val &= ~TIMER_ENABLE;
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
-
- /*
- * The Timer Control Register has one Undefined/Shouldn't Use Bit
- * So we should do read/modify/write Operation
- */
-
- /*
- * Timer Mode : Free Running
- * Interrupt : Disabled
- * Prescale : 8 Stage, Clk/256
- * Tmr Siz : 16 Bit Counter
- * Tmr in Wrapping Mode
- */
- tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
- tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
- tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
-
- *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
-
- return 0;
-}
-
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 409e6f5..b228ed6 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_IPROC) += iproc-common/
obj-$(CONFIG_KONA) += kona-common/
obj-$(CONFIG_OMAP_COMMON) += omap-common/
obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
-obj-$(CONFIG_TEGRA) += tegra-common/
ifneq (,$(filter s5pc1xx exynos,$(SOC)))
obj-y += s5p-common/
@@ -40,13 +39,11 @@ endif
obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
-obj-$(CONFIG_AT91FAMILY) += at91/
+obj-$(CONFIG_BCM2835) += bcm2835/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(CONFIG_ARCH_EXYNOS) += exynos/
-obj-$(CONFIG_ARCH_HIGHBANK) += highbank/
-obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
obj-$(CONFIG_MX6) += mx6/
@@ -58,7 +55,6 @@ obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
obj-$(CONFIG_SOCFPGA) += socfpga/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
-obj-$(CONFIG_TEGRA20) += tegra20/
obj-$(CONFIG_U8500) += u8500/
obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
obj-$(CONFIG_VF610) += vf610/
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 31188c8..529a119 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -118,4 +118,7 @@ void enable_basic_clocks(void)
/* Select the Master osc clk as Timer2 clock source */
writel(0x1, &cmdpll->clktimer2clk);
+
+ /* For OPP100 the mac clock should be /5. */
+ writel(0x4, &cmdpll->clkselmacclk);
}
diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/cpu/armv7/at91/Makefile
deleted file mode 100644
index f4f35a4..0000000
--- a/arch/arm/cpu/armv7/at91/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2013
-# Bo Shen <voice.shen@atmel.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o
-obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o
-obj-y += clock.o
-obj-y += cpu.o
-obj-y += reset.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c
deleted file mode 100644
index 0bf453e..0000000
--- a/arch/arm/cpu/armv7/at91/clock.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
- *
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned long at91_css_to_rate(unsigned long css)
-{
- switch (css) {
- case AT91_PMC_MCKR_CSS_SLOW:
- return CONFIG_SYS_AT91_SLOW_CLOCK;
- case AT91_PMC_MCKR_CSS_MAIN:
- return gd->arch.main_clk_rate_hz;
- case AT91_PMC_MCKR_CSS_PLLA:
- return gd->arch.plla_rate_hz;
- }
-
- return 0;
-}
-
-static u32 at91_pll_rate(u32 freq, u32 reg)
-{
- unsigned mul, div;
-
- div = reg & 0xff;
- mul = (reg >> 18) & 0x7f;
- if (div && mul) {
- freq /= div;
- freq *= mul + 1;
- } else {
- freq = 0;
- }
-
- return freq;
-}
-
-int at91_clock_init(unsigned long main_clock)
-{
- unsigned freq, mckr;
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
- unsigned tmp;
- /*
- * When the bootloader initialized the main oscillator correctly,
- * there's no problem using the cycle counter. But if it didn't,
- * or when using oscillator bypass mode, we must be told the speed
- * of the main clock.
- */
- if (!main_clock) {
- do {
- tmp = readl(&pmc->mcfr);
- } while (!(tmp & AT91_PMC_MCFR_MAINRDY));
- tmp &= AT91_PMC_MCFR_MAINF_MASK;
- main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
- }
-#endif
- gd->arch.main_clk_rate_hz = main_clock;
-
- /* report if PLLA is more than mildly overclocked */
- gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
-
- /*
- * MCK and CPU derive from one of those primary clocks.
- * For now, assume this parentage won't change.
- */
- mckr = readl(&pmc->mckr);
-
- /* plla divisor by 2 */
- if (mckr & (1 << 12))
- gd->arch.plla_rate_hz >>= 1;
-
- gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
- freq = gd->arch.mck_rate_hz;
-
- /* prescale */
- freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
-
- switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
- case AT91_PMC_MCKR_MDIV_2:
- gd->arch.mck_rate_hz = freq / 2;
- break;
- case AT91_PMC_MCKR_MDIV_3:
- gd->arch.mck_rate_hz = freq / 3;
- break;
- case AT91_PMC_MCKR_MDIV_4:
- gd->arch.mck_rate_hz = freq / 4;
- break;
- default:
- break;
- }
-
- gd->arch.cpu_clk_rate_hz = freq;
-
- return 0;
-}
-
-void at91_plla_init(u32 pllar)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- writel(pllar, &pmc->pllar);
- while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
- ;
-}
-
-void at91_mck_init(u32 mckr)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- u32 tmp;
-
- tmp = readl(&pmc->mckr);
- tmp &= ~(AT91_PMC_MCKR_CSS_MASK |
- AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_2);
-#ifdef CPU_HAS_H32MXDIV
- tmp &= ~AT91_PMC_MCKR_H32MXDIV;
-#endif
-
- tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK |
- AT91_PMC_MCKR_PRES_MASK |
- AT91_PMC_MCKR_MDIV_MASK |
- AT91_PMC_MCKR_PLLADIV_2);
-#ifdef CPU_HAS_H32MXDIV
- tmp |= mckr & AT91_PMC_MCKR_H32MXDIV;
-#endif
-
- writel(tmp, &pmc->mckr);
-
- while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
- ;
-}
-
-void at91_periph_clk_enable(int id)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- u32 regval;
-
- if (id > AT91_PMC_PCR_PID_MASK)
- return;
-
- regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
-
- writel(regval, &pmc->pcr);
-}
-
-void at91_periph_clk_disable(int id)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- u32 regval;
-
- if (id > AT91_PMC_PCR_PID_MASK)
- return;
-
- regval = AT91_PMC_PCR_CMD_WRITE | id;
-
- writel(regval, &pmc->pcr);
-}
diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk
deleted file mode 100644
index db60308..0000000
--- a/arch/arm/cpu/armv7/at91/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2014, Andreas Bießmann <andreas.devel@googlemail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifndef CONFIG_SPL_BUILD
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c
deleted file mode 100644
index 8d86f97..0000000
--- a/arch/arm/cpu/armv7/at91/cpu.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- * (C) Copyright 2009
- * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * (C) Copyright 2013
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_dbu.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_gpbr.h>
-#include <asm/arch/clk.h>
-
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
-#endif
-
-int arch_cpu_init(void)
-{
- return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-}
-
-void arch_preboot_os(void)
-{
- ulong cpiv;
- at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
-
- cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
-
- /*
- * Disable PITC
- * Add 0x1000 to current counter to stop it faster
- * without waiting for wrapping back to 0
- */
- writel(cpiv + 0x1000, &pit->mr);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- char buf[32];
-
- printf("CPU: %s\n", get_cpu_name());
- printf("Crystal frequency: %8s MHz\n",
- strmhz(buf, get_main_clk_rate()));
- printf("CPU clock : %8s MHz\n",
- strmhz(buf, get_cpu_clk_rate()));
- printf("Master clock : %8s MHz\n",
- strmhz(buf, get_mck_clk_rate()));
-
- return 0;
-}
-#endif
-
-void enable_caches(void)
-{
- icache_enable();
- dcache_enable();
-}
-
-unsigned int get_chip_id(void)
-{
- return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
-}
-
-unsigned int get_extension_chip_id(void)
-{
- return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
-}
diff --git a/arch/arm/cpu/armv7/at91/reset.c b/arch/arm/cpu/armv7/at91/reset.c
deleted file mode 100644
index b30e79b..0000000
--- a/arch/arm/cpu/armv7/at91/reset.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2013
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_rstc.h>
-
-/* Reset the cpu by telling the reset controller to do so */
-void reset_cpu(ulong ignored)
-{
- at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
-
- writel(AT91_RSTC_KEY
- | AT91_RSTC_CR_PROCRST /* Processor Reset */
- | AT91_RSTC_CR_PERRST /* Peripheral Reset */
-#ifdef CONFIG_AT91RESET_EXTRST
- | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */
-#endif
- , &rstc->cr);
- /* never reached */
- do { } while (1);
-}
diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
deleted file mode 100644
index 78ecfc8..0000000
--- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Copyright (C) 2012-2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sama5d3.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-
-unsigned int has_emac()
-{
- return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36();
-}
-
-unsigned int has_gmac()
-{
- return !cpu_is_sama5d31();
-}
-
-unsigned int has_lcdc()
-{
- return !cpu_is_sama5d35();
-}
-
-char *get_cpu_name()
-{
- unsigned int extension_id = get_extension_chip_id();
-
- if (cpu_is_sama5d3())
- switch (extension_id) {
- case ARCH_EXID_SAMA5D31:
- return "SAMA5D31";
- case ARCH_EXID_SAMA5D33:
- return "SAMA5D33";
- case ARCH_EXID_SAMA5D34:
- return "SAMA5D34";
- case ARCH_EXID_SAMA5D35:
- return "SAMA5D35";
- case ARCH_EXID_SAMA5D36:
- return "SAMA5D36";
- default:
- return "Unknown CPU type";
- }
- else
- return "Unknown CPU type";
-}
-
-void at91_serial0_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */
- at91_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_USART0);
-}
-
-void at91_serial1_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */
- at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_USART1);
-}
-
-void at91_serial2_hw_init(void)
-{
- at91_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */
- at91_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_USART2);
-}
-
-void at91_seriald_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */
- at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_DBGU);
-}
-
-#if defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
- at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */
- at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */
- at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */
-
- if (cs_mask & (1 << 0))
- at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
- if (cs_mask & (1 << 1))
- at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
- if (cs_mask & (1 << 2))
- at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
- if (cs_mask & (1 << 3))
- at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-void at91_mci_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */
- at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */
- at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */
- at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */
- at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */
-#ifdef CONFIG_ATMEL_MCI_8BIT
- at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */
- at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */
- at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */
- at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */
-#endif
- at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_MCI0);
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */
- at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */
- at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */
- at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */
- at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */
- at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */
- at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */
- at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */
- at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */
- at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_EMAC);
-}
-
-void at91_gmac_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */
- at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */
- at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */
- at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */
- at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */
-
- at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */
- at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */
-
- at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */
- at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */
- at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_GMAC);
-}
-#endif
-
-#ifdef CONFIG_LCD
-void at91_lcd_hw_init(void)
-{
- at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
- at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
- at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
- at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
- at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
-
- /* The lower 16-bit of LCD only available on Port A */
- at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
- at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
- at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
- at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
- at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
- at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
- at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
- at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
- at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */
- at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */
- at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
- at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
- at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
- at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
- at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
- at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
-
- /* Enable clock */
- at91_periph_clk_enable(ATMEL_ID_LCDC);
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-void at91_udp_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable UPLL clock */
- writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
- /* Enable UDPHS clock */
- at91_periph_clk_enable(ATMEL_ID_UDPHS);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/at91/sama5d4_devices.c b/arch/arm/cpu/armv7/at91/sama5d4_devices.c
deleted file mode 100644
index ef39cb7..0000000
--- a/arch/arm/cpu/armv7/at91/sama5d4_devices.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (C) 2014 Atmel
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/sama5_matrix.h>
-#include <asm/arch/sama5_sfr.h>
-#include <asm/arch/sama5d4.h>
-
-char *get_cpu_name()
-{
- unsigned int extension_id = get_extension_chip_id();
-
- if (cpu_is_sama5d4())
- switch (extension_id) {
- case ARCH_EXID_SAMA5D41:
- return "SAMA5D41";
- case ARCH_EXID_SAMA5D42:
- return "SAMA5D42";
- case ARCH_EXID_SAMA5D43:
- return "SAMA5D43";
- case ARCH_EXID_SAMA5D44:
- return "SAMA5D44";
- default:
- return "Unknown CPU type";
- }
- else
- return "Unknown CPU type";
-}
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-void at91_udp_hw_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable UPLL clock */
- writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
- /* Enable UDPHS clock */
- at91_periph_clk_enable(ATMEL_ID_UDPHS);
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-void matrix_init(void)
-{
- struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
- struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
- int i;
-
- /* Disable the write protect */
- writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
- writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-
- /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
- for (i = 4; i <= 10; i++) {
- writel(0x000f0f0f, &h64mx->ssr[i]);
- writel(0x0000ffff, &h64mx->sassr[i]);
- writel(0x0000000f, &h64mx->srtsr[i]);
- }
-
- /* CS3 */
- writel(0x00c0c0c0, &h32mx->ssr[3]);
- writel(0xff000000, &h32mx->sassr[3]);
- writel(0xff000000, &h32mx->srtsr[3]);
-
- /* NFC SRAM */
- writel(0x00010101, &h32mx->ssr[4]);
- writel(0x00000001, &h32mx->sassr[4]);
- writel(0x00000001, &h32mx->srtsr[4]);
-
- /* Enable the write protect */
- writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
- writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-}
-
-void redirect_int_from_saic_to_aic(void)
-{
- struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
- u32 key32;
-
- if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
- key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
- writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
- }
-}
-#endif
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c
deleted file mode 100644
index 19bf80b..0000000
--- a/arch/arm/cpu/armv7/at91/timer.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2013
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <div64.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * We're using the SAMA5D3x PITC in 32 bit mode, by
- * setting the 20 bit counter period to its maximum (0xfffff).
- * (See the relevant data sheets to understand that this really works)
- *
- * We do also mimic the typical powerpc way of incrementing
- * two 32 bit registers called tbl and tbu.
- *
- * Those registers increment at 1/16 the main clock rate.
- */
-
-#define TIMER_LOAD_VAL 0xfffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
- tick *= CONFIG_SYS_HZ;
- do_div(tick, gd->arch.timer_rate_hz);
-
- return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
- usec *= gd->arch.timer_rate_hz;
- do_div(usec, 1000000);
-
- return usec;
-}
-
-/*
- * Use the PITC in full 32 bit incrementing mode
- */
-int timer_init(void)
-{
- at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
-
- /* Enable PITC Clock */
- at91_periph_clk_enable(ATMEL_ID_PIT);
-
- /* Enable PITC */
- writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
-
- gd->arch.timer_rate_hz = get_pit_clk_rate() / 16;
-
- gd->arch.tbu = 0;
- gd->arch.tbl = 0;
-
- return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
- at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
-
- ulong now = readl(&pit->piir);
-
- /* increment tbu if tbl has rolled over */
- if (now < gd->arch.tbl)
- gd->arch.tbu++;
- gd->arch.tbl = now;
- return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long start;
- ulong tmo;
-
- start = get_ticks(); /* get current timestamp */
- tmo = usec_to_tick(usec); /* convert usecs to ticks */
- while ((get_ticks() - start) < tmo)
- ; /* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
- return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return gd->arch.timer_rate_hz;
-}
diff --git a/arch/arm/cpu/armv7/bcm2835/Makefile b/arch/arm/cpu/armv7/bcm2835/Makefile
new file mode 100644
index 0000000..ed1ee47
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm2835/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2012 Stephen Warren
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+src_dir := ../../arm1176/bcm2835/
+
+obj-y :=
+obj-y += $(src_dir)/init.o
+obj-y += $(src_dir)/reset.o
+obj-y += $(src_dir)/timer.o
+obj-y += $(src_dir)/mbox.o
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index 7fcb5d2..eb86a7f 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -6,7 +6,7 @@ choice
config TARGET_SMDKV310
select SUPPORT_SPL
bool "Exynos4210 SMDKV310 board"
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_TRATS
bool "Exynos4210 Trats board"
@@ -33,38 +33,59 @@ config TARGET_ARNDALE
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SMDK5250
bool "SMDK5250 board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SNOW
bool "Snow board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SMDK5420
bool "SMDK5420 board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_PEACH_PI
bool "Peach Pi board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_PEACH_PIT
bool "Peach Pit board"
select SUPPORT_SPL
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
endchoice
config SYS_SOC
default "exynos"
+config DM
+ default y
+
+config DM_SERIAL
+ default y
+
+config DM_SPI
+ default y
+
+config DM_SPI_FLASH
+ default y
+
+config DM_GPIO
+ default y
+
+config SYS_MALLOC_F
+ default y
+
+config SYS_MALLOC_F_LEN
+ default 0x400
+
source "board/samsung/smdkv310/Kconfig"
source "board/samsung/trats/Kconfig"
source "board/samsung/universal_c210/Kconfig"
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index b31c13b..c6455c2 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -20,42 +20,84 @@
* positions of the peripheral clocks of the src and div registers
*/
struct clk_bit_info {
+ enum periph_id id;
+ int32_t src_mask;
+ int32_t div_mask;
+ int32_t prediv_mask;
int8_t src_bit;
int8_t div_bit;
int8_t prediv_bit;
};
-/* src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[] = {
- {0, 0, -1},
- {4, 4, -1},
- {8, 8, -1},
- {12, 12, -1},
- {0, 0, 8},
- {4, 16, 24},
- {8, 0, 8},
- {12, 16, 24},
- {-1, -1, -1},
- {16, 0, 8},
- {20, 16, 24},
- {24, 0, 8},
- {0, 0, 4},
- {4, 12, 16},
- {-1, -1, -1},
- {-1, -1, -1},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {-1, 24, 0},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
- {24, 0, -1},
+static struct clk_bit_info exynos5_bit_info[] = {
+ /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
+ {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
+ {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
+ {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
+ {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
+ {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C6, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_I2C7, -1, 0x7, 0x7, -1, 24, 0},
+ {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 16, 0, 8},
+ {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 20, 16, 24},
+ {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 24, 0, 8},
+ {PERIPH_ID_SDMMC0, 0xf, 0xf, 0xff, 0, 0, 8},
+ {PERIPH_ID_SDMMC1, 0xf, 0xf, 0xff, 4, 16, 24},
+ {PERIPH_ID_SDMMC2, 0xf, 0xf, 0xff, 8, 0, 8},
+ {PERIPH_ID_SDMMC3, 0xf, 0xf, 0xff, 12, 16, 24},
+ {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
+ {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
+ {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 0, 0, 4},
+ {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 4, 12, 16},
+ {PERIPH_ID_SDMMC4, 0xf, 0xf, 0xff, 16, 0, 8},
+ {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 0, -1},
+ {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 0, -1},
+
+ {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
+};
+
+static struct clk_bit_info exynos542x_bit_info[] = {
+ /* periph id s_mask d_mask p_mask s_bit d_bit p_bit */
+ {PERIPH_ID_UART0, 0xf, 0xf, -1, 4, 8, -1},
+ {PERIPH_ID_UART1, 0xf, 0xf, -1, 8, 12, -1},
+ {PERIPH_ID_UART2, 0xf, 0xf, -1, 12, 16, -1},
+ {PERIPH_ID_UART3, 0xf, 0xf, -1, 16, 20, -1},
+ {PERIPH_ID_I2C0, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C1, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C2, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C3, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C4, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C5, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C6, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C7, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 20, 20, 8},
+ {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 24, 24, 16},
+ {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 28, 28, 24},
+ {PERIPH_ID_SDMMC0, 0x7, 0x3ff, -1, 8, 0, -1},
+ {PERIPH_ID_SDMMC1, 0x7, 0x3ff, -1, 12, 10, -1},
+ {PERIPH_ID_SDMMC2, 0x7, 0x3ff, -1, 16, 20, -1},
+ {PERIPH_ID_I2C8, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2C9, -1, 0x3f, -1, -1, 8, -1},
+ {PERIPH_ID_I2S0, 0xf, 0xf, 0xff, 0, 0, 4},
+ {PERIPH_ID_I2S1, 0xf, 0xf, 0xff, 4, 12, 16},
+ {PERIPH_ID_SPI3, 0xf, 0xf, 0xff, 12, 16, 0},
+ {PERIPH_ID_SPI4, 0xf, 0xf, 0xff, 16, 20, 8},
+ {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 28, -1},
+ {PERIPH_ID_I2C10, -1, 0x3f, -1, -1, 8, -1},
+
+ {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
};
/* Epll Clock division values to achive different frequency output */
@@ -260,11 +302,72 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
return fout;
}
+/* exynos542x: return pll clock frequency */
+static unsigned long exynos542x_get_pll_clk(int pllreg)
+{
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ unsigned long r, k = 0;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ case BPLL:
+ r = readl(&clk->bpll_con0);
+ break;
+ case RPLL:
+ r = readl(&clk->rpll_con0);
+ k = readl(&clk->rpll_con1);
+ break;
+ case SPLL:
+ r = readl(&clk->spll_con0);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ return exynos_get_pll_clk(pllreg, r, k);
+}
+
+static struct clk_bit_info *get_clk_bit_info(int peripheral)
+{
+ int i;
+ struct clk_bit_info *info;
+
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ info = exynos542x_bit_info;
+ else
+ info = exynos5_bit_info;
+
+ for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
+ if (info[i].id == peripheral)
+ break;
+ }
+
+ if (info[i].id == PERIPH_ID_NONE)
+ debug("ERROR: Peripheral ID %d not found\n", peripheral);
+
+ return &info[i];
+}
+
static unsigned long exynos5_get_periph_rate(int peripheral)
{
- struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
- unsigned long sclk, sub_clk;
- unsigned int src, div, sub_div;
+ struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
+ unsigned long sclk = 0;
+ unsigned int src = 0, div = 0, sub_div = 0;
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
@@ -286,27 +389,30 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
break;
case PERIPH_ID_I2S0:
src = readl(&clk->src_mau);
- div = readl(&clk->div_mau);
+ div = sub_div = readl(&clk->div_mau);
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
src = readl(&clk->src_peric1);
- div = readl(&clk->div_peric1);
+ div = sub_div = readl(&clk->div_peric1);
break;
case PERIPH_ID_SPI2:
src = readl(&clk->src_peric1);
- div = readl(&clk->div_peric2);
+ div = sub_div = readl(&clk->div_peric2);
break;
case PERIPH_ID_SPI3:
case PERIPH_ID_SPI4:
src = readl(&clk->sclk_src_isp);
- div = readl(&clk->sclk_div_isp);
+ div = sub_div = readl(&clk->sclk_div_isp);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
+ src = readl(&clk->src_fsys);
+ div = sub_div = readl(&clk->div_fsys1);
+ break;
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC3:
src = readl(&clk->src_fsys);
- div = readl(&clk->div_fsys1);
+ div = sub_div = readl(&clk->div_fsys2);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
@@ -316,18 +422,17 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
- sclk = exynos5_get_pll_clk(MPLL);
- sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
- & 0x7) + 1;
- div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
- & 0x7) + 1;
- return (sclk / sub_div) / div;
+ src = EXYNOS_SRC_MPLL;
+ div = readl(&clk->div_top0);
+ sub_div = readl(&clk->div_top1);
+ break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
};
- src = (src >> bit_info->src_bit) & 0xf;
+ if (bit_info->src_bit >= 0)
+ src = (src >> bit_info->src_bit) & bit_info->src_mask;
switch (src) {
case EXYNOS_SRC_MPLL:
@@ -340,68 +445,126 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
sclk = exynos5_get_pll_clk(VPLL);
break;
default:
+ debug("%s: EXYNOS_SRC %d not supported\n", __func__, src);
return 0;
}
- /* Ratio clock division for this peripheral */
- sub_div = (div >> bit_info->div_bit) & 0xf;
- sub_clk = sclk / (sub_div + 1);
-
- /* Pre-ratio clock division for SDMMC0 and 2 */
- if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
- div = (div >> bit_info->prediv_bit) & 0xff;
- return sub_clk / (div + 1);
- }
+ /* Clock divider ratio for this peripheral */
+ if (bit_info->div_bit >= 0)
+ div = (div >> bit_info->div_bit) & bit_info->div_mask;
- return sub_clk;
-}
+ /* Clock pre-divider ratio for this peripheral */
+ if (bit_info->prediv_bit >= 0)
+ sub_div = (sub_div >> bit_info->prediv_bit)
+ & bit_info->prediv_mask;
-unsigned long clock_get_periph_rate(int peripheral)
-{
- if (cpu_is_exynos5())
- return exynos5_get_periph_rate(peripheral);
- else
- return 0;
+ /* Calculate and return required clock rate */
+ return (sclk / (div + 1)) / (sub_div + 1);
}
-/* exynos5420: return pll clock frequency */
-static unsigned long exynos5420_get_pll_clk(int pllreg)
+static unsigned long exynos542x_get_periph_rate(int peripheral)
{
+ struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
+ unsigned long sclk = 0;
+ unsigned int src = 0, div = 0, sub_div = 0;
struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long r, k = 0;
+ (struct exynos5420_clock *)samsung_get_base_clock();
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ case PERIPH_ID_UART3:
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ case PERIPH_ID_PWM4:
+ src = readl(&clk->src_peric0);
+ div = readl(&clk->div_peric0);
break;
- case MPLL:
- r = readl(&clk->mpll_con0);
+ case PERIPH_ID_SPI0:
+ case PERIPH_ID_SPI1:
+ case PERIPH_ID_SPI2:
+ src = readl(&clk->src_peric1);
+ div = readl(&clk->div_peric1);
+ sub_div = readl(&clk->div_peric4);
break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
+ case PERIPH_ID_SPI3:
+ case PERIPH_ID_SPI4:
+ src = readl(&clk->src_isp);
+ div = readl(&clk->div_isp1);
+ sub_div = readl(&clk->div_isp1);
break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ case PERIPH_ID_SDMMC2:
+ case PERIPH_ID_SDMMC3:
+ src = readl(&clk->src_fsys);
+ div = readl(&clk->div_fsys1);
break;
- case BPLL:
- r = readl(&clk->bpll_con0);
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ case PERIPH_ID_I2C3:
+ case PERIPH_ID_I2C4:
+ case PERIPH_ID_I2C5:
+ case PERIPH_ID_I2C6:
+ case PERIPH_ID_I2C7:
+ case PERIPH_ID_I2C8:
+ case PERIPH_ID_I2C9:
+ case PERIPH_ID_I2C10:
+ src = EXYNOS542X_SRC_MPLL;
+ div = readl(&clk->div_top1);
break;
- case RPLL:
- r = readl(&clk->rpll_con0);
- k = readl(&clk->rpll_con1);
+ default:
+ debug("%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ };
+
+ if (bit_info->src_bit >= 0)
+ src = (src >> bit_info->src_bit) & bit_info->src_mask;
+
+ switch (src) {
+ case EXYNOS542X_SRC_MPLL:
+ sclk = exynos542x_get_pll_clk(MPLL);
break;
- case SPLL:
- r = readl(&clk->spll_con0);
+ case EXYNOS542X_SRC_SPLL:
+ sclk = exynos542x_get_pll_clk(SPLL);
+ break;
+ case EXYNOS542X_SRC_EPLL:
+ sclk = exynos542x_get_pll_clk(EPLL);
+ break;
+ case EXYNOS542X_SRC_RPLL:
+ sclk = exynos542x_get_pll_clk(RPLL);
break;
default:
- printf("Unsupported PLL (%d)\n", pllreg);
+ debug("%s: EXYNOS542X_SRC %d not supported", __func__, src);
return 0;
}
- return exynos_get_pll_clk(pllreg, r, k);
+ /* Clock divider ratio for this peripheral */
+ if (bit_info->div_bit >= 0)
+ div = (div >> bit_info->div_bit) & bit_info->div_mask;
+
+ /* Clock pre-divider ratio for this peripheral */
+ if (bit_info->prediv_bit >= 0)
+ sub_div = (sub_div >> bit_info->prediv_bit)
+ & bit_info->prediv_mask;
+
+ /* Calculate and return required clock rate */
+ return (sclk / (div + 1)) / (sub_div + 1);
+}
+
+unsigned long clock_get_periph_rate(int peripheral)
+{
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ return exynos542x_get_periph_rate(peripheral);
+ return exynos5_get_periph_rate(peripheral);
+ } else {
+ return 0;
+ }
}
/* exynos4: return ARM clock frequency */
@@ -527,27 +690,6 @@ static unsigned long exynos4x12_get_pwm_clk(void)
return pclk;
}
-/* exynos5420: return pwm clock frequency */
-static unsigned long exynos5420_get_pwm_clk(void)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int ratio;
-
- /*
- * CLK_DIV_PERIC0
- * PWM_RATIO [31:28]
- */
- ratio = readl(&clk->div_peric0);
- ratio = (ratio >> 28) & 0xf;
- sclk = get_pll_clk(MPLL);
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
/* exynos4: return uart clock frequency */
static unsigned long exynos4_get_uart_clk(int dev_index)
{
@@ -640,100 +782,6 @@ static unsigned long exynos4x12_get_uart_clk(int dev_index)
return uclk;
}
-/* exynos5: return uart clock frequency */
-static unsigned long exynos5_get_uart_clk(int dev_index)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_PERIC0
- * UART0_SEL [3:0]
- * UART1_SEL [7:4]
- * UART2_SEL [8:11]
- * UART3_SEL [12:15]
- * UART4_SEL [16:19]
- * UART5_SEL [23:20]
- */
- sel = readl(&clk->src_peric0);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIC0
- * UART0_RATIO [3:0]
- * UART1_RATIO [7:4]
- * UART2_RATIO [8:11]
- * UART3_RATIO [12:15]
- * UART4_RATIO [16:19]
- * UART5_RATIO [23:20]
- */
- ratio = readl(&clk->div_peric0);
- ratio = (ratio >> (dev_index << 2)) & 0xf;
-
- uclk = sclk / (ratio + 1);
-
- return uclk;
-}
-
-/* exynos5420: return uart clock frequency */
-static unsigned long exynos5420_get_uart_clk(int dev_index)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_PERIC0
- * UART0_SEL [6:4]
- * UART1_SEL [10:8]
- * UART2_SEL [14:12]
- * UART3_SEL [18:16]
- * generalised calculation as follows
- * sel = (sel >> ((dev_index * 4) + 4)) & mask;
- */
- sel = readl(&clk->src_peric0);
- sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
-
- if (sel == 0x3)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x6)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(RPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIC0
- * UART0_RATIO [11:8]
- * UART1_RATIO [15:12]
- * UART2_RATIO [19:16]
- * UART3_RATIO [23:20]
- * generalised calculation as follows
- * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
- */
- ratio = readl(&clk->div_peric0);
- ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
-
- uclk = sclk / (ratio + 1);
-
- return uclk;
-}
-
static unsigned long exynos4_get_mmc_clk(int dev_index)
{
struct exynos4_clock *clk =
@@ -783,94 +831,6 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
return uclk;
}
-static unsigned long exynos5_get_mmc_clk(int dev_index)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel, ratio, pre_ratio;
- int shift = 0;
-
- sel = readl(&clk->src_fsys);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- switch (dev_index) {
- case 0:
- case 1:
- ratio = readl(&clk->div_fsys1);
- pre_ratio = readl(&clk->div_fsys1);
- break;
- case 2:
- case 3:
- ratio = readl(&clk->div_fsys2);
- pre_ratio = readl(&clk->div_fsys2);
- break;
- default:
- return 0;
- }
-
- if (dev_index == 1 || dev_index == 3)
- shift = 16;
-
- ratio = (ratio >> shift) & 0xf;
- pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
- uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
-
- return uclk;
-}
-
-static unsigned long exynos5420_get_mmc_clk(int dev_index)
-{
- struct exynos5420_clock *clk =
- (struct exynos5420_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel, ratio;
-
- /*
- * CLK_SRC_FSYS
- * MMC0_SEL [10:8]
- * MMC1_SEL [14:12]
- * MMC2_SEL [18:16]
- * generalised calculation as follows
- * sel = (sel >> ((dev_index * 4) + 8)) & mask
- */
- sel = readl(&clk->src_fsys);
- sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
-
- if (sel == 0x3)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x4)
- sclk = get_pll_clk(SPLL);
- else if (sel == 0x6)
- sclk = get_pll_clk(EPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_FSYS1
- * MMC0_RATIO [9:0]
- * MMC1_RATIO [19:10]
- * MMC2_RATIO [29:20]
- * generalised calculation as follows
- * ratio = (ratio >> (dev_index * 10)) & mask
- */
- ratio = readl(&clk->div_fsys1);
- ratio = (ratio >> (dev_index * 10)) & 0x3ff;
-
- uclk = (sclk / (ratio + 1));
-
- return uclk;
-}
-
/* exynos4: set the mmc clock */
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
@@ -1249,29 +1209,6 @@ void exynos4_set_mipi_clk(void)
clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
}
-/*
- * I2C
- *
- * exynos5: obtaining the I2C clock
- */
-static unsigned long exynos5_get_i2c_clk(void)
-{
- struct exynos5_clock *clk =
- (struct exynos5_clock *)samsung_get_base_clock();
- unsigned long aclk_66, aclk_66_pre, sclk;
- unsigned int ratio;
-
- sclk = get_pll_clk(MPLL);
-
- ratio = (readl(&clk->div_top1)) >> 24;
- ratio &= 0x7;
- aclk_66_pre = sclk / (ratio + 1);
- ratio = readl(&clk->div_top0);
- ratio &= 0x7;
- aclk_66 = aclk_66_pre / (ratio + 1);
- return aclk_66;
-}
-
int exynos5_set_epll_clk(unsigned long rate)
{
unsigned int epll_con, epll_con_k;
@@ -1585,7 +1522,7 @@ unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_pll_clk(pllreg);
+ return exynos542x_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else {
if (proid_is_exynos4412())
@@ -1608,7 +1545,7 @@ unsigned long get_arm_clk(void)
unsigned long get_i2c_clk(void)
{
if (cpu_is_exynos5()) {
- return exynos5_get_i2c_clk();
+ return clock_get_periph_rate(PERIPH_ID_I2C0);
} else if (cpu_is_exynos4()) {
return exynos4_get_i2c_clk();
} else {
@@ -1620,8 +1557,6 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
} else {
if (proid_is_exynos4412())
@@ -1632,10 +1567,28 @@ unsigned long get_pwm_clk(void)
unsigned long get_uart_clk(int dev_index)
{
+ enum periph_id id;
+
+ switch (dev_index) {
+ case 0:
+ id = PERIPH_ID_UART0;
+ break;
+ case 1:
+ id = PERIPH_ID_UART1;
+ break;
+ case 2:
+ id = PERIPH_ID_UART2;
+ break;
+ case 3:
+ id = PERIPH_ID_UART3;
+ break;
+ default:
+ debug("%s: invalid UART index %d", __func__, dev_index);
+ return -1;
+ }
+
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_uart_clk(dev_index);
- return exynos5_get_uart_clk(dev_index);
+ return clock_get_periph_rate(id);
} else {
if (proid_is_exynos4412())
return exynos4x12_get_uart_clk(dev_index);
@@ -1645,10 +1598,28 @@ unsigned long get_uart_clk(int dev_index)
unsigned long get_mmc_clk(int dev_index)
{
+ enum periph_id id;
+
+ switch (dev_index) {
+ case 0:
+ id = PERIPH_ID_SDMMC0;
+ break;
+ case 1:
+ id = PERIPH_ID_SDMMC1;
+ break;
+ case 2:
+ id = PERIPH_ID_SDMMC2;
+ break;
+ case 3:
+ id = PERIPH_ID_SDMMC3;
+ break;
+ default:
+ debug("%s: invalid MMC index %d", __func__, dev_index);
+ return -1;
+ }
+
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
- return exynos5420_get_mmc_clk(dev_index);
- return exynos5_get_mmc_clk(dev_index);
+ return clock_get_periph_rate(id);
} else {
return exynos4_get_mmc_clk(dev_index);
}
@@ -1656,6 +1627,10 @@ unsigned long get_mmc_clk(int dev_index)
void set_mmc_clk(int dev_index, unsigned int div)
{
+ /* If want to set correct value, it needs to substract one from div.*/
+ if (div > 0)
+ div -= 1;
+
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_mmc_clk(dev_index, div);
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index 1520d64..1b12051 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -102,10 +102,34 @@ static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
}
}
+static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
+{
+ struct exynos5420_power *power =
+ (struct exynos5420_power *)samsung_get_base_power();
+
+ if (enable) {
+ /* Enabling USBDEV_PHY */
+ setbits_le32(&power->usbdev_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ setbits_le32(&power->usbdev1_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ } else {
+ /* Disabling USBDEV_PHY */
+ clrbits_le32(&power->usbdev_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ clrbits_le32(&power->usbdev1_phy_control,
+ POWER_USB_DRD_PHY_CTRL_EN);
+ }
+}
+
void set_usbdrd_phy_ctrl(unsigned int enable)
{
- if (cpu_is_exynos5())
- exynos5_set_usbdrd_phy_ctrl(enable);
+ if (cpu_is_exynos5()) {
+ if (proid_is_exynos5420() || proid_is_exynos5800())
+ exynos5420_set_usbdev_phy_ctrl(enable);
+ else
+ exynos5_set_usbdrd_phy_ctrl(enable);
+ }
}
static void exynos5_dp_phy_control(unsigned int enable)
diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c
index bc237c9..c7f943e 100644
--- a/arch/arm/cpu/armv7/exynos/spl_boot.c
+++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -309,4 +309,3 @@ void board_init_r(gd_t *id, ulong dest_addr)
while (1)
;
}
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/arch/arm/cpu/armv7/highbank/Kconfig b/arch/arm/cpu/armv7/highbank/Kconfig
deleted file mode 100644
index 0e73c04..0000000
--- a/arch/arm/cpu/armv7/highbank/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if ARCH_HIGHBANK
-
-config SYS_BOARD
- default "highbank"
-
-config SYS_SOC
- default "highbank"
-
-config SYS_CONFIG_NAME
- default "highbank"
-
-endif
diff --git a/arch/arm/cpu/armv7/highbank/Makefile b/arch/arm/cpu/armv7/highbank/Makefile
deleted file mode 100644
index 876099d..0000000
--- a/arch/arm/cpu/armv7/highbank/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := timer.o
diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c
deleted file mode 100644
index d56bf21..0000000
--- a/arch/arm/cpu/armv7/highbank/timer.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2010-2011 Calxeda, Inc.
- *
- * Based on arm926ejs/mx27/timer.c
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch-armv7/systimer.h>
-
-#undef SYSTIMER_BASE
-#define SYSTIMER_BASE 0xFFF34000 /* Timer 0 and 1 base */
-
-static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
-
-/*
- * Start the timer
- */
-int timer_init(void)
-{
- /*
- * Setup timer0
- */
- writel(0, &systimer_base->timer0control);
- writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
- writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
- writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256,
- &systimer_base->timer0control);
-
- return 0;
-
-}
diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/cpu/armv7/keystone/Kconfig
deleted file mode 100644
index 134ae87..0000000
--- a/arch/arm/cpu/armv7/keystone/Kconfig
+++ /dev/null
@@ -1,22 +0,0 @@
-if ARCH_KEYSTONE
-
-choice
- prompt "TI Keystone board select"
-
-config TARGET_K2HK_EVM
- bool "TI Keystone 2 Kepler/Hawking EVM"
-
-config TARGET_K2E_EVM
- bool "TI Keystone 2 Edison EVM"
-
-config TARGET_K2L_EVM
- bool "TI Keystone 2 Lamar EVM"
-
-endchoice
-
-config SYS_SOC
- default "keystone"
-
-source "board/ti/ks2_evm/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
deleted file mode 100644
index ed030db..0000000
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2012-2014
-# Texas Instruments Incorporated, <www.ti.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += init.o
-obj-y += psc.o
-obj-y += clock.o
-obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
-obj-$(CONFIG_SOC_K2E) += clock-k2e.o
-obj-$(CONFIG_SOC_K2L) += clock-k2l.o
-obj-y += cmd_clock.o
-obj-y += cmd_mon.o
-obj-y += msmc.o
-obj-y += ddr3.o cmd_ddr3.o
-obj-y += keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c
deleted file mode 100644
index 31f6661..0000000
--- a/arch/arm/cpu/armv7/keystone/clock-k2e.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Keystone2: get clk rate for K2E
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-const struct keystone_pll_regs keystone_pll_regs[] = {
- [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
- [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
- [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
-int dev_speeds[] = {
- SPD800,
- SPD850,
- SPD1000,
- SPD1250,
- SPD1350,
- SPD1400,
- SPD1500,
- SPD1400,
- SPD1350,
- SPD1250,
- SPD1000,
- SPD850,
- SPD800
-};
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll: pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, output_div = 2;
- unsigned long ret;
- u32 tmp, reg;
-
- if (pll == CORE_PLL) {
- ret = external_clk[sys_clk];
- if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
- /* PLL mode */
- tmp = __raw_readl(KS2_MAINPLLCTL0);
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
- (pllctl_reg_read(pll, mult) &
- PLLM_MULT_LO_MASK)) + 1;
- output_div = ((pllctl_reg_read(pll, secctl) >>
- PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
- ret = ret / prediv / output_div * mult;
- }
- } else {
- switch (pll) {
- case PASS_PLL:
- ret = external_clk[pa_clk];
- reg = KS2_PASSPLLCTL0;
- break;
- case DDR3_PLL:
- ret = external_clk[ddr3_clk];
- reg = KS2_DDR3APLLCTL0;
- break;
- default:
- return 0;
- }
-
- tmp = __raw_readl(reg);
-
- if (!(tmp & PLLCTL_BYPASS)) {
- /* Bypass disabled */
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
- output_div = ((tmp >> PLL_CLKOD_SHIFT) &
- PLL_CLKOD_MASK) + 1;
- ret = ((ret / prediv) * mult) / output_div;
- }
- }
-
- return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- switch (clk) {
- case core_pll_clk: return pll_freq_get(CORE_PLL);
- case pass_pll_clk: return pll_freq_get(PASS_PLL);
- case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
- case sys_clk0_1_clk:
- case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
- case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
- case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
- case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
- case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
- case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
- case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
- case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
- case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
- case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
- case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
- case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
- case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
- case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
- case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
- default:
- break;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
deleted file mode 100644
index 1591960..0000000
--- a/arch/arm/cpu/armv7/keystone/clock-k2hk.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Keystone2: get clk rate for K2HK
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-const struct keystone_pll_regs keystone_pll_regs[] = {
- [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
- [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
- [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
- [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
- [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
-};
-
-int dev_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-int arm_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD800,
- SPD1400,
- SPD1350,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll: pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, output_div = 2;
- unsigned long ret;
- u32 tmp, reg;
-
- if (pll == CORE_PLL) {
- ret = external_clk[sys_clk];
- if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
- /* PLL mode */
- tmp = __raw_readl(KS2_MAINPLLCTL0);
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
- (pllctl_reg_read(pll, mult) &
- PLLM_MULT_LO_MASK)) + 1;
- output_div = ((pllctl_reg_read(pll, secctl) >>
- PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
- ret = ret / prediv / output_div * mult;
- }
- } else {
- switch (pll) {
- case PASS_PLL:
- ret = external_clk[pa_clk];
- reg = KS2_PASSPLLCTL0;
- break;
- case TETRIS_PLL:
- ret = external_clk[tetris_clk];
- reg = KS2_ARMPLLCTL0;
- break;
- case DDR3A_PLL:
- ret = external_clk[ddr3a_clk];
- reg = KS2_DDR3APLLCTL0;
- break;
- case DDR3B_PLL:
- ret = external_clk[ddr3b_clk];
- reg = KS2_DDR3BPLLCTL0;
- break;
- default:
- return 0;
- }
-
- tmp = __raw_readl(reg);
-
- if (!(tmp & PLLCTL_BYPASS)) {
- /* Bypass disabled */
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
- output_div = ((tmp >> PLL_CLKOD_SHIFT) &
- PLL_CLKOD_MASK) + 1;
- ret = ((ret / prediv) * mult) / output_div;
- }
- }
-
- return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- switch (clk) {
- case core_pll_clk: return pll_freq_get(CORE_PLL);
- case pass_pll_clk: return pll_freq_get(PASS_PLL);
- case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
- case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
- case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
- case sys_clk0_1_clk:
- case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
- case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
- case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
- case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
- case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
- case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
- case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
- case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
- case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
- case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
- case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
- case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
- case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
- case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
- case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
- default:
- break;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c b/arch/arm/cpu/armv7/keystone/clock-k2l.c
deleted file mode 100644
index 1c5e4d5..0000000
--- a/arch/arm/cpu/armv7/keystone/clock-k2l.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Keystone2: get clk rate for K2L
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-const struct keystone_pll_regs keystone_pll_regs[] = {
- [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
- [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
- [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
- [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
-int dev_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD800,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-int arm_speeds[] = {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD800,
- SPD1400,
- SPD1350,
- SPD1200,
- SPD1000,
- SPD800,
- SPD800,
- SPD800,
-};
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll: pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
- unsigned long mult = 1, prediv = 1, output_div = 2;
- unsigned long ret;
- u32 tmp, reg;
-
- if (pll == CORE_PLL) {
- ret = external_clk[sys_clk];
- if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
- /* PLL mode */
- tmp = __raw_readl(KS2_MAINPLLCTL0);
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
- (pllctl_reg_read(pll, mult) &
- PLLM_MULT_LO_MASK)) + 1;
- output_div = ((pllctl_reg_read(pll, secctl) >>
- PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
- ret = ret / prediv / output_div * mult;
- }
- } else {
- switch (pll) {
- case PASS_PLL:
- ret = external_clk[pa_clk];
- reg = KS2_PASSPLLCTL0;
- break;
- case TETRIS_PLL:
- ret = external_clk[tetris_clk];
- reg = KS2_ARMPLLCTL0;
- break;
- case DDR3_PLL:
- ret = external_clk[ddr3_clk];
- reg = KS2_DDR3APLLCTL0;
- break;
- default:
- return 0;
- }
-
- tmp = __raw_readl(reg);
- if (!(tmp & PLLCTL_BYPASS)) {
- /* Bypass disabled */
- prediv = (tmp & PLL_DIV_MASK) + 1;
- mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
- output_div = ((tmp >> PLL_CLKOD_SHIFT) &
- PLL_CLKOD_MASK) + 1;
- ret = ((ret / prediv) * mult) / output_div;
- }
- }
-
- return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
- switch (clk) {
- case core_pll_clk: return pll_freq_get(CORE_PLL);
- case pass_pll_clk: return pll_freq_get(PASS_PLL);
- case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
- case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
- case sys_clk0_1_clk:
- case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
- case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
- case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
- case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
- case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
- case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
- case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
- case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
- case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
- case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
- case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
- case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
- case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
- case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
- case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
- default:
- break;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
deleted file mode 100644
index d13fbc1..0000000
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Keystone2: pll initialization
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-#define MAX_SPEEDS 13
-
-static void wait_for_completion(const struct pll_init_data *data)
-{
- int i;
- for (i = 0; i < 100; i++) {
- sdelay(450);
- if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
- break;
- }
-}
-
-void init_pll(const struct pll_init_data *data)
-{
- u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
-
- pllm = data->pll_m - 1;
- plld = (data->pll_d - 1) & PLL_DIV_MASK;
- pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
-
- if (data->pll == MAIN_PLL) {
- /* The requered delay before main PLL configuration */
- sdelay(210000);
-
- tmp = pllctl_reg_read(data->pll, secctl);
-
- if (tmp & (PLLCTL_BYPASS)) {
- setbits_le32(keystone_pll_regs[data->pll].reg1,
- BIT(MAIN_ENSAT_OFFSET));
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
- PLLCTL_PLLENSRC);
- sdelay(340);
-
- pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- sdelay(21000);
-
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
- } else {
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
- PLLCTL_PLLENSRC);
- sdelay(340);
- }
-
- pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
-
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLLM_MULT_HI_SMASK, (pllm << 6));
-
- /* Set the BWADJ (12 bit field) */
- tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLL_BWADJ_LO_SMASK,
- (tmp_ctl << PLL_BWADJ_LO_SHIFT));
- clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
- PLL_BWADJ_HI_MASK,
- (tmp_ctl >> 8));
-
- /*
- * Set the pll divider (6 bit field) *
- * PLLD[5:0] is located in MAINPLLCTL0
- */
- clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
- PLL_DIV_MASK, plld);
-
- /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
- pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
- (pllod << PLL_CLKOD_SHIFT));
- wait_for_completion(data);
-
- pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
- pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
- pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
- pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
- pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
-
- pllctl_reg_setbits(data->pll, alnctl, 0x1f);
-
- /*
- * Set GOSET bit in PLLCMD to initiate the GO operation
- * to change the divide
- */
- pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
- sdelay(1500); /* wait for the phase adj */
- wait_for_completion(data);
-
- /* Reset PLL */
- pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
- sdelay(21000); /* Wait for a minimum of 7 us*/
- pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
- sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
-
- pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
-
- tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-
-#ifndef CONFIG_SOC_K2E
- } else if (data->pll == TETRIS_PLL) {
- bwadj = pllm >> 1;
- /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
- setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- /*
- * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
- * only applicable for Kepler
- */
- clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
- /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
- setbits_le32(keystone_pll_regs[data->pll].reg1 ,
- PLL_PLLRST | PLLCTL_ENSAT);
-
- /*
- * 3 Program PLLM and PLLD in PLLCTL0 register
- * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
- * PLLCTL1 register. BWADJ value must be set
- * to ((PLLM + 1) >> 1) – 1)
- */
- tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
- (pllm << 6) |
- (plld & PLL_DIV_MASK) |
- (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
-
- /* Set BWADJ[11:8] bits */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
- tmp &= ~(PLL_BWADJ_HI_MASK);
- tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
- /*
- * 5 Wait for at least 5 us based on the reference
- * clock (PLL reset time)
- */
- sdelay(21000); /* Wait for a minimum of 7 us*/
-
- /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
- clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
- /*
- * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
- * (PLL lock time)
- */
- sdelay(105000);
- /* 8 disable bypass */
- clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- /*
- * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
- * only applicable for Kepler
- */
- setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
-#endif
- } else {
- setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
- /*
- * process keeps state of Bypass bit while programming
- * all other DDR PLL settings
- */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
- tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
-
- /*
- * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
- * bypass disabled
- */
- bwadj = pllm >> 1;
- tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
- (pllm << PLL_MULT_SHIFT) |
- (plld & PLL_DIV_MASK) |
- (pllod << PLL_CLKOD_SHIFT);
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
-
- /* Set BWADJ[11:8] bits */
- tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
- tmp &= ~(PLL_BWADJ_HI_MASK);
- tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
-
- __raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
-
- /* Reset bit: bit 14 for both DDR3 & PASS PLL */
- tmp = PLL_PLLRST;
- /* Set RESET bit = 1 */
- setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
- /* Wait for a minimum of 7 us*/
- sdelay(21000);
- /* Clear RESET bit */
- clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
- sdelay(105000);
-
- /* clear BYPASS (Enable PLL Mode) */
- clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
- sdelay(21000); /* Wait for a minimum of 7 us*/
- }
-
- /*
- * This is required to provide a delay between multiple
- * consequent PPL configurations
- */
- sdelay(210000);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
- int i;
-
- for (i = 0; i < num_pll; i++)
- init_pll(&config[i]);
-}
-
-static int get_max_speed(u32 val, int *speeds)
-{
- int j;
-
- if (!val)
- return speeds[0];
-
- for (j = 1; j < MAX_SPEEDS; j++) {
- if (val == 1)
- return speeds[j];
- val >>= 1;
- }
-
- return SPD800;
-}
-
-#ifdef CONFIG_SOC_K2HK
-static u32 read_efuse_bootrom(void)
-{
- return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
- __raw_readl(KS2_REV1_DEVSPEED);
-}
-#else
-static inline u32 read_efuse_bootrom(void)
-{
- return __raw_readl(KS2_EFUSE_BOOTROM);
-}
-#endif
-
-inline int get_max_dev_speed(void)
-{
- return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
-}
-
-#ifndef CONFIG_SOC_K2E
-inline int get_max_arm_speed(void)
-{
- return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
-}
-#endif
-
-void pass_pll_pa_clk_enable(void)
-{
- u32 reg;
-
- reg = readl(keystone_pll_regs[PASS_PLL].reg1);
-
- reg |= PLLCTL_PAPLL;
- writel(reg, keystone_pll_regs[PASS_PLL].reg1);
-
- /* wait till clock is enabled */
- sdelay(15000);
-}
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
deleted file mode 100644
index af1b701..0000000
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * keystone2: commands for clocks
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/psc_defs.h>
-
-struct pll_init_data cmd_pll_data = {
- .pll = MAIN_PLL,
- .pll_m = 16,
- .pll_d = 1,
- .pll_od = 2,
-};
-
-int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc != 5)
- goto pll_cmd_usage;
-
- if (strncmp(argv[1], "pa", 2) == 0)
- cmd_pll_data.pll = PASS_PLL;
-#ifndef CONFIG_SOC_K2E
- else if (strncmp(argv[1], "arm", 3) == 0)
- cmd_pll_data.pll = TETRIS_PLL;
-#endif
-#ifdef CONFIG_SOC_K2HK
- else if (strncmp(argv[1], "ddr3a", 5) == 0)
- cmd_pll_data.pll = DDR3A_PLL;
- else if (strncmp(argv[1], "ddr3b", 5) == 0)
- cmd_pll_data.pll = DDR3B_PLL;
-#else
- else if (strncmp(argv[1], "ddr3", 4) == 0)
- cmd_pll_data.pll = DDR3_PLL;
-#endif
- else
- goto pll_cmd_usage;
-
- cmd_pll_data.pll_m = simple_strtoul(argv[2], NULL, 10);
- cmd_pll_data.pll_d = simple_strtoul(argv[3], NULL, 10);
- cmd_pll_data.pll_od = simple_strtoul(argv[4], NULL, 10);
-
- printf("Trying to set pll %d; mult %d; div %d; OD %d\n",
- cmd_pll_data.pll, cmd_pll_data.pll_m,
- cmd_pll_data.pll_d, cmd_pll_data.pll_od);
- init_pll(&cmd_pll_data);
-
- return 0;
-
-pll_cmd_usage:
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- pllset, 5, 0, do_pll_cmd,
- "set pll multiplier and pre divider",
- PLLSET_CMD_LIST " <mult> <div> <OD>\n"
-);
-
-int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int clk;
- unsigned int freq;
-
- if (argc != 2)
- goto getclk_cmd_usage;
-
- clk = simple_strtoul(argv[1], NULL, 10);
-
- freq = clk_get_rate(clk);
- printf("clock index [%d] - frequency %u\n", clk, freq);
- return 0;
-
-getclk_cmd_usage:
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- getclk, 2, 0, do_getclk_cmd,
- "get clock rate",
- "<clk index>\n"
- "The indexes for clocks:\n"
- CLOCK_INDEXES_LIST
-);
-
-int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int psc_module;
- int res;
-
- if (argc != 3)
- goto psc_cmd_usage;
-
- psc_module = simple_strtoul(argv[1], NULL, 10);
- if (strcmp(argv[2], "en") == 0) {
- res = psc_enable_module(psc_module);
- printf("psc_enable_module(%d) - %s\n", psc_module,
- (res) ? "ERROR" : "OK");
- return 0;
- }
-
- if (strcmp(argv[2], "di") == 0) {
- res = psc_disable_module(psc_module);
- printf("psc_disable_module(%d) - %s\n", psc_module,
- (res) ? "ERROR" : "OK");
- return 0;
- }
-
- if (strcmp(argv[2], "domain") == 0) {
- res = psc_disable_domain(psc_module);
- printf("psc_disable_domain(%d) - %s\n", psc_module,
- (res) ? "ERROR" : "OK");
- return 0;
- }
-
-psc_cmd_usage:
- return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
- psc, 3, 0, do_psc_cmd,
- "<enable/disable psc module os disable domain>",
- "<mod/domain index> <en|di|domain>\n"
- "Intended to control Power and Sleep Controller (PSC) domains and\n"
- "modules. The module or domain index exectly corresponds to ones\n"
- "listed in official TRM. For instance, to enable MSMC RAM clock\n"
- "domain use command: psc 14 en.\n"
-);
diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
deleted file mode 100644
index ea78ad8..0000000
--- a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * Keystone2: DDR3 test commands
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/ddr3.h>
-#include <common.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
-
-#define DDR_REMAP_ADDR 0x80000000
-#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
-
-#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
- CONFIG_STACKSIZE) >> 17) - 2)
-
-#define DDR_TEST_BURST_SIZE 1024
-
-static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
-{
- u32 index_start, value, index;
-
- index_start = start_address;
-
- while (1) {
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4)
- __raw_writel(index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4) {
- value = __raw_readl(index);
- if (value != index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readl(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- if (quick)
- continue;
-
- /* Write a pattern for complementary values */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4)
- __raw_writel((u32)~index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 4) {
- value = __raw_readl(index);
- if (value != ~index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readl(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 2)
- __raw_writew((u16)index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 2) {
- value = __raw_readw(index);
- if (value != (u16)index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readw(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
-
- /* Write a pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 1)
- __raw_writeb((u8)index, index);
-
- /* Read and check the pattern */
- for (index = index_start;
- index < index_start + DDR_TEST_BURST_SIZE;
- index += 1) {
- value = __raw_readb(index);
- if (value != (u8)index) {
- printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
- index, value, __raw_readb(index));
-
- return -1;
- }
- }
-
- index_start += DDR_TEST_BURST_SIZE;
- if (index_start >= end_address)
- break;
- }
-
- puts("ddr memory test PASSED!\n");
- return 0;
-}
-
-static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
-{
- u32 index, value, index2, value2;
-
- for (index = address1, index2 = address2;
- index < address1 + size;
- index += 4, index2 += 4) {
- value = __raw_readl(index);
- value2 = __raw_readl(index2);
-
- if (value != value2) {
- printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
- index, value, index2, value2);
-
- return -1;
- }
- }
-
- puts("ddr memory compare PASSED!\n");
- return 0;
-}
-
-static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
-{
- u32 value1, value2, value3;
-
- puts("Disabling DDR ECC ...\n");
- ddr3_disable_ecc(base);
-
- value1 = __raw_readl(address);
- value2 = value1 ^ ecc_err;
- __raw_writel(value2, address);
-
- value3 = __raw_readl(address);
- printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
- address, value1, value2, ecc_err, value3);
-
- __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
- base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
-
- puts("Enabling DDR ECC ...\n");
- ddr3_enable_ecc(base, 1);
-
- value1 = __raw_readl(address);
- printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
-
- ddr3_check_ecc_int(base);
- return 0;
-}
-
-static int do_ddr_test(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- u32 start_addr, end_addr, size, ecc_err;
-
- if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
- if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
- puts("ECC RMW isn't supported for this SOC\n");
- return 1;
- }
-
- start_addr = simple_strtoul(argv[2], NULL, 16);
- ecc_err = simple_strtoul(argv[3], NULL, 16);
-
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
- (start_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1))) {
- puts("Invalid address!\n");
- return cmd_usage(cmdtp);
- }
-
- ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
- start_addr, ecc_err);
- return 0;
- }
-
- if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
- ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
- return cmd_usage(cmdtp);
-
- start_addr = simple_strtoul(argv[2], NULL, 16);
- end_addr = simple_strtoul(argv[3], NULL, 16);
-
- if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
- (start_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
- (end_addr < CONFIG_SYS_SDRAM_BASE) ||
- (end_addr > (CONFIG_SYS_SDRAM_BASE +
- CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
- puts("Invalid start or end address!\n");
- return cmd_usage(cmdtp);
- }
-
- puts("Please wait ...\n");
- if (argc == 5) {
- size = simple_strtoul(argv[4], NULL, 16);
- ddr_memory_compare(start_addr, end_addr, size);
- } else {
- ddr_memory_test(start_addr, end_addr, 0);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(ddr, 5, 1, do_ddr_test,
- "DDR3 test",
- "test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
- " address to end address\n"
- "ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
- " compare DDR data of (size) bytes from start address to end\n"
- " address\n"
- "ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
- " in DDR data at <addr>, the command will read a 32-bit data\n"
- " from <addr>, and write (data ^ bit_err) back to <addr>\n"
-);
diff --git a/arch/arm/cpu/armv7/keystone/cmd_mon.c b/arch/arm/cpu/armv7/keystone/cmd_mon.c
deleted file mode 100644
index f9f58a3..0000000
--- a/arch/arm/cpu/armv7/keystone/cmd_mon.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * K2HK: secure kernel command file
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-asm(".arch_extension sec\n\t");
-
-static int mon_install(u32 addr, u32 dpsc, u32 freq)
-{
- int result;
-
- __asm__ __volatile__ (
- "stmfd r13!, {lr}\n"
- "mov r0, %1\n"
- "mov r1, %2\n"
- "mov r2, %3\n"
- "blx r0\n"
- "ldmfd r13!, {lr}\n"
- : "=&r" (result)
- : "r" (addr), "r" (dpsc), "r" (freq)
- : "cc", "r0", "r1", "r2", "memory");
- return result;
-}
-
-static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- u32 addr, dpsc_base = 0x1E80000, freq;
- int rcode = 0;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- freq = clk_get_rate(sys_clk0_6_clk);
-
- addr = simple_strtoul(argv[1], NULL, 16);
-
- rcode = mon_install(addr, dpsc_base, freq);
- printf("## installed monitor, freq [%d], status %d\n",
- freq, rcode);
-
- return 0;
-}
-
-U_BOOT_CMD(mon_install, 2, 0, do_mon_install,
- "Install boot kernel at 'addr'",
- ""
-);
-
-static void core_spin(void)
-{
- while (1)
- ; /* forever */;
-}
-
-int mon_power_on(int core_id, void *ep)
-{
- int result;
-
- asm volatile (
- "stmfd r13!, {lr}\n"
- "mov r1, %1\n"
- "mov r2, %2\n"
- "mov r0, #0\n"
- "smc #0\n"
- "ldmfd r13!, {lr}\n"
- : "=&r" (result)
- : "r" (core_id), "r" (ep)
- : "cc", "r0", "r1", "r2", "memory");
- return result;
-}
-
-int mon_power_off(int core_id)
-{
- int result;
-
- asm volatile (
- "stmfd r13!, {lr}\n"
- "mov r1, %1\n"
- "mov r0, #1\n"
- "smc #1\n"
- "ldmfd r13!, {lr}\n"
- : "=&r" (result)
- : "r" (core_id)
- : "cc", "r0", "r1", "memory");
- return result;
-}
-
-int do_mon_power(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- int rcode = 0, core_id, on;
- void (*fn)(void);
-
- fn = core_spin;
-
- if (argc < 3)
- return CMD_RET_USAGE;
-
- core_id = simple_strtoul(argv[1], NULL, 16);
- on = simple_strtoul(argv[2], NULL, 16);
-
- if (on)
- rcode = mon_power_on(core_id, fn);
- else
- rcode = mon_power_off(core_id);
-
- if (on) {
- if (!rcode)
- printf("core %d powered on successfully\n", core_id);
- else
- printf("core %d power on failure\n", core_id);
- } else {
- printf("core %d powered off successfully\n", core_id);
- }
-
- return 0;
-}
-
-U_BOOT_CMD(mon_power, 3, 0, do_mon_power,
- "Power On/Off secondary core",
- "mon_power <coreid> <oper>\n"
- "- coreid (1-3) and oper (1 - ON, 0 - OFF)\n"
- ""
-);
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
deleted file mode 100644
index 923906a..0000000
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * Keystone2: DDR3 initialization
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <asm/arch/msmc.h>
-#include <asm/arch/ddr3.h>
-#include <asm/arch/psc_defs.h>
-
-#include <asm/ti-common/ti-edma3.h>
-
-#define DDR3_EDMA_BLK_SIZE_SHIFT 10
-#define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT)
-#define DDR3_EDMA_BCNT 0x8000
-#define DDR3_EDMA_CCNT 1
-#define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
-#define DDR3_EDMA_SLOT_NUM 1
-
-void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
-{
- unsigned int tmp;
-
- while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
- & 0x00000001) != 0x00000001)
- ;
-
- __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
-
- tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
- tmp &= ~(phy_cfg->pgcr1_mask);
- tmp |= phy_cfg->pgcr1_val;
- __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
-
- __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET);
- __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET);
- __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET);
- __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET);
-
- tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
- tmp &= ~(phy_cfg->dcr_mask);
- tmp |= phy_cfg->dcr_val;
- __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
-
- __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
- __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
- __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
- __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
- __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
- __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
- __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
- __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
-
- __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
- __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
- __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
-
- __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
- while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
- ;
-
- __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
- while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
- ;
-}
-
-void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
-{
- __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET);
- __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
- __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
- __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
- __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
- __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET);
- __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
-}
-
-int ddr3_ecc_support_rmw(u32 base)
-{
- u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
-
- /* Check the DDR3 controller ID reg if the controllers
- supports ECC RMW or not */
- if (value == 0x40461C02)
- return 1;
-
- return 0;
-}
-
-static void ddr3_ecc_config(u32 base, u32 value)
-{
- u32 data;
-
- __raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET);
- udelay(100000); /* delay required to synchronize across clock domains */
-
- if (value & KS2_DDR3_ECC_EN) {
- /* Clear the 1-bit error count */
- data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
- __raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
-
- /* enable the ECC interrupt */
- __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
- KS2_DDR3_WR_ECC_ERR_SYS,
- base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
-
- /* Clear the ECC error interrupt status */
- __raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
- KS2_DDR3_WR_ECC_ERR_SYS,
- base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
- }
-}
-
-static void ddr3_reset_data(u32 base, u32 ddr3_size)
-{
- u32 mpax[2];
- u32 seg_num;
- u32 seg, blks, dst, edma_blks;
- struct edma3_slot_config slot;
- struct edma3_channel_config edma_channel;
- u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
-
- /* Setup an edma to copy the 1k block to the entire DDR */
- puts("\nClear entire DDR3 memory to enable ECC\n");
-
- /* save the SES MPAX regs */
- msmc_get_ses_mpax(8, 0, mpax);
-
- /* setup edma slot 1 configuration */
- slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
- EDMA3_SLOPT_COMP_CODE(0) |
- EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
- slot.bcnt = DDR3_EDMA_BCNT;
- slot.acnt = DDR3_EDMA_BLK_SIZE;
- slot.ccnt = DDR3_EDMA_CCNT;
- slot.src_bidx = 0;
- slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
- slot.src_cidx = 0;
- slot.dst_cidx = 0;
- slot.link = EDMA3_PARSET_NULL_LINK;
- slot.bcntrld = 0;
- edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
-
- /* configure quik edma channel */
- edma_channel.slot = DDR3_EDMA_SLOT_NUM;
- edma_channel.chnum = 0;
- edma_channel.complete_code = 0;
- /* event trigger after dst update */
- edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
- qedma3_start(KS2_EDMA0_BASE, &edma_channel);
-
- /* DDR3 size in segments (4KB seg size) */
- seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
-
- for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
- /* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
- access slave interface so that edma driver can access */
- msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
- KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
-
- if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
- edma_blks = KS2_MSMC_MAP_SEG_NUM <<
- (KS2_MSMC_SEG_SIZE_SHIFT
- - DDR3_EDMA_BLK_SIZE_SHIFT);
- else
- edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
- - DDR3_EDMA_BLK_SIZE_SHIFT);
-
- /* Use edma driver to scrub 2GB DDR memory */
- for (dst = base, blks = 0; blks < edma_blks;
- blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
- edma3_set_src_addr(KS2_EDMA0_BASE,
- edma_channel.slot, (u32)edma_src);
- edma3_set_dest_addr(KS2_EDMA0_BASE,
- edma_channel.slot, (u32)dst);
-
- while (edma3_check_for_transfer(KS2_EDMA0_BASE,
- &edma_channel))
- udelay(10);
- }
- }
-
- qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
-
- /* restore the SES MPAX regs */
- msmc_set_ses_mpax(8, 0, mpax);
-}
-
-static void ddr3_ecc_init_range(u32 base)
-{
- u32 ecc_val = KS2_DDR3_ECC_EN;
- u32 rmw = ddr3_ecc_support_rmw(base);
-
- if (rmw)
- ecc_val |= KS2_DDR3_ECC_RMW_EN;
-
- __raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
-
- ddr3_ecc_config(base, ecc_val);
-}
-
-void ddr3_enable_ecc(u32 base, int test)
-{
- u32 ecc_val = KS2_DDR3_ECC_ENABLE;
- u32 rmw = ddr3_ecc_support_rmw(base);
-
- if (test)
- ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
-
- if (!rmw) {
- if (!test)
- /* by default, disable ecc when rmw = 0 and no
- ecc test */
- ecc_val = 0;
- } else {
- ecc_val |= KS2_DDR3_ECC_RMW_EN;
- }
-
- ddr3_ecc_config(base, ecc_val);
-}
-
-void ddr3_disable_ecc(u32 base)
-{
- ddr3_ecc_config(base, 0);
-}
-
-#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
-static void cic_init(u32 base)
-{
- /* Disable CIC global interrupts */
- __raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
-
- /* Set to normal mode, no nesting, no priority hold */
- __raw_writel(0, base + KS2_CIC_CTRL);
- __raw_writel(0, base + KS2_CIC_HOST_CTRL);
-
- /* Enable CIC global interrupts */
- __raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
-}
-
-static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
-{
- /* Map the system interrupt to a CIC channel */
- __raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
-
- /* Enable CIC system interrupt */
- __raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
-
- /* Enable CIC Host interrupt */
- __raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
-}
-
-static void ddr3_map_ecc_cic2_irq(u32 base)
-{
- cic_init(base);
- cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
- KS2_CIC2_DDR3_ECC_IRQ_NUM);
-}
-#endif
-
-void ddr3_init_ecc(u32 base)
-{
- u32 ddr3_size;
-
- if (!ddr3_ecc_support_rmw(base)) {
- ddr3_disable_ecc(base);
- return;
- }
-
- ddr3_ecc_init_range(base);
- ddr3_size = ddr3_get_size();
- ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
-
- /* mapping DDR3 ECC system interrupt from CIC2 to GIC */
-#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
- ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
-#endif
- ddr3_enable_ecc(base, 0);
-}
-
-void ddr3_check_ecc_int(u32 base)
-{
- char *env;
- int ecc_test = 0;
- u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
-
- env = getenv("ecc_test");
- if (env)
- ecc_test = simple_strtol(env, NULL, 0);
-
- if (value & KS2_DDR3_WR_ECC_ERR_SYS)
- puts("DDR3 ECC write error interrupted\n");
-
- if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
- puts("DDR3 ECC 2-bit error interrupted\n");
-
- if (!ecc_test) {
- puts("Reseting the device ...\n");
- reset_cpu(0);
- }
- }
-
- value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
- if (value) {
- printf("1-bit ECC err count: 0x%x\n", value);
- value = __raw_readl(base +
- KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
- printf("1-bit ECC err address log: 0x%x\n", value);
- }
-}
-
-void ddr3_reset_ddrphy(void)
-{
- u32 tmp;
-
- /* Assert DDR3A PHY reset */
- tmp = readl(KS2_DDR3APLLCTL1);
- tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
- writel(tmp, KS2_DDR3APLLCTL1);
-
- /* wait 10us to catch the reset */
- udelay(10);
-
- /* Release DDR3A PHY reset */
- tmp = readl(KS2_DDR3APLLCTL1);
- tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
- __raw_writel(tmp, KS2_DDR3APLLCTL1);
-}
-
-#ifdef CONFIG_SOC_K2HK
-/**
- * ddr3_reset_workaround - reset workaround in case if leveling error
- * detected for PG 1.0 and 1.1 k2hk SoCs
- */
-void ddr3_err_reset_workaround(void)
-{
- unsigned int tmp;
- unsigned int tmp_a;
- unsigned int tmp_b;
-
- /*
- * Check for PGSR0 error bits of DDR3 PHY.
- * Check for WLERR, QSGERR, WLAERR,
- * RDERR, WDERR, REERR, WEERR error to see if they are set or not
- */
- tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
- tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
-
- if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
- printf("DDR Leveling Error Detected!\n");
- printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
- printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
-
- /*
- * Write Keys to KICK registers to enable writes to registers
- * in boot config space
- */
- __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
- __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
-
- /*
- * Move DDR3A Module out of reset isolation by setting
- * MDCTL23[12] = 0
- */
- tmp_a = __raw_readl(KS2_PSC_BASE +
- PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
-
- tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
- __raw_writel(tmp_a, KS2_PSC_BASE +
- PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
-
- /*
- * Move DDR3B Module out of reset isolation by setting
- * MDCTL24[12] = 0
- */
- tmp_b = __raw_readl(KS2_PSC_BASE +
- PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
- tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
- __raw_writel(tmp_b, KS2_PSC_BASE +
- PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
-
- /*
- * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
- * to RSTCTRL and RSTCFG
- */
- tmp = __raw_readl(KS2_RSTCTRL);
- tmp &= KS2_RSTCTRL_MASK;
- tmp |= KS2_RSTCTRL_KEY;
- __raw_writel(tmp, KS2_RSTCTRL);
-
- /*
- * Set PLL Controller to drive hard reset on SW trigger by
- * setting RSTCFG[13] = 0
- */
- tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
- tmp &= ~KS2_RSTYPE_PLL_SOFT;
- __raw_writel(tmp, KS2_RSTCTRL_RSCFG);
-
- reset_cpu(0);
- }
-}
-#endif
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
deleted file mode 100644
index c96845c..0000000
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Keystone2: Architecture initialization
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <asm/arch/msmc.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/psc_defs.h>
-
-#define MAX_PCI_PORTS 2
-enum pci_mode {
- ENDPOINT,
- LEGACY_ENDPOINT,
- ROOTCOMPLEX,
-};
-
-#define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
-#define DEVCFG_MODE_SHIFT 1
-
-void chip_configuration_unlock(void)
-{
- __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
- __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
-}
-
-#ifdef CONFIG_SOC_K2L
-void osr_init(void)
-{
- u32 i;
- u32 j;
- u32 val;
- u32 base = KS2_OSR_CFG_BASE;
- u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
-
- /* Enable the OSR clock domain */
- psc_enable_module(KS2_LPSC_OSR);
-
- /* Disable OSR ECC check for all the ram banks */
- for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
- val = i | KS2_OSR_ECC_VEC_TRIG_RD |
- (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
-
- writel(val , base + KS2_OSR_ECC_VEC);
-
- /**
- * wait till read is done.
- * Print should be added after earlyprintk support is added.
- */
- for (j = 0; j < 10000; j++) {
- val = readl(base + KS2_OSR_ECC_VEC);
- if (val & KS2_OSR_ECC_VEC_RD_DONE)
- break;
- }
-
- ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
- KS2_OSR_ECC_CTRL_CHK;
-
- writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
- writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
- }
-
- /* Reset OSR memory to all zeros */
- for (i = 0; i < KS2_OSR_SIZE; i += 4)
- writel(0, KS2_OSR_DATA_BASE + i);
-
- /* Enable OSR ECC check for all the ram banks */
- for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
- writel(ecc_ctrl[i] |
- KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
-}
-#endif
-
-/* Function to set up PCIe mode */
-static void config_pcie_mode(int pcie_port, enum pci_mode mode)
-{
- u32 val = __raw_readl(KS2_DEVCFG);
-
- if (pcie_port >= MAX_PCI_PORTS)
- return;
-
- /**
- * each pci port has two bits for mode and it starts at
- * bit 1. So use port number to get the right bit position.
- */
- pcie_port <<= 1;
- val &= ~(DEVCFG_MODE_MASK << pcie_port);
- val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
- __raw_writel(val, KS2_DEVCFG);
-}
-
-int arch_cpu_init(void)
-{
- chip_configuration_unlock();
- icache_enable();
-
- msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
- msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
- msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
- msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
-
- /* Initialize the PCIe-0 to work as Root Complex */
- config_pcie_mode(0, ROOTCOMPLEX);
-#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
- msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
- /* Initialize the PCIe-1 to work as Root Complex */
- config_pcie_mode(1, ROOTCOMPLEX);
-#endif
-#ifdef CONFIG_SOC_K2L
- osr_init();
-#endif
-
- /*
- * just initialise the COM2 port so that TI specific
- * UART register PWREMU_MGMT is initialized. Linux UART
- * driver doesn't handle this.
- */
- NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
- return 0;
-}
-
-void reset_cpu(ulong addr)
-{
- volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
- u32 tmp;
-
- tmp = *rstctrl & KS2_RSTCTRL_MASK;
- *rstctrl = tmp | KS2_RSTCTRL_KEY;
-
- *rstctrl &= KS2_RSTCTRL_SWRST;
-
- for (;;)
- ;
-}
-
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-#endif
-}
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c
deleted file mode 100644
index 11a9357..0000000
--- a/arch/arm/cpu/armv7/keystone/keystone.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Keystone EVM : Board initialization
- *
- * (C) Copyright 2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mon.h>
-#include <asm/arch/psc_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/hardware.h>
-
-/**
- * cpu_to_bus - swap bytes of the 32-bit data if the device is BE
- * @ptr - array of data
- * @length - lenght of data array
- */
-int cpu_to_bus(u32 *ptr, u32 length)
-{
- u32 i;
-
- if (!(readl(KS2_DEVSTAT) & 0x1))
- for (i = 0; i < length; i++, ptr++)
- *ptr = cpu_to_be32(*ptr);
-
- return 0;
-}
-
-static int turn_off_myself(void)
-{
- printf("Turning off ourselves\r\n");
- mon_power_off(0);
-
- psc_disable_module(KS2_LPSC_TETRIS);
- psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
-
- asm volatile ("isb\n"
- "dsb\n"
- "wfi\n");
-
- printf("What! Should not see that\n");
- return 0;
-}
-
-static void turn_off_all_dsps(int num_dsps)
-{
- int i;
-
- for (i = 0; i < num_dsps; i++) {
- if (psc_disable_module(i + KS2_LPSC_GEM_0))
- printf("Cannot disable module for #%d DSP", i);
-
- if (psc_disable_domain(i + 8))
- printf("Cannot disable domain for #%d DSP", i);
- }
-}
-
-int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- return turn_off_myself();
-}
-
-U_BOOT_CMD(
- killme, 1, 0, do_killme_cmd,
- "turn off main ARM core",
- "turn off main ARM core. Should not live after that :(\n"
-);
-
-int misc_init_r(void)
-{
- char *env;
- long ks2_debug = 0;
-
- env = getenv("ks2_debug");
-
- if (env)
- ks2_debug = simple_strtol(env, NULL, 0);
-
- if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0)
- turn_off_all_dsps(KS2_NUM_DSPS);
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
deleted file mode 100644
index 7899141..0000000
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * MSMC controller utilities
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/msmc.h>
-
-struct mpax {
- u32 mpaxl;
- u32 mpaxh;
-};
-
-struct msms_regs {
- u32 pid;
- u32 _res_04;
- u32 smcerrar;
- u32 smcerrxr;
- u32 smedcc;
- u32 smcea;
- u32 smsecc;
- u32 smpfar;
- u32 smpfxr;
- u32 smpfr;
- u32 smpfcr;
- u32 _res_2c;
- u32 sbndc[8];
- u32 sbndm;
- u32 sbnde;
- u32 _res_58;
- u32 cfglck;
- u32 cfgulck;
- u32 cfglckstat;
- u32 sms_mpax_lck;
- u32 sms_mpax_ulck;
- u32 sms_mpax_lckstat;
- u32 ses_mpax_lck;
- u32 ses_mpax_ulck;
- u32 ses_mpax_lckstat;
- u32 smestat;
- u32 smirstat;
- u32 smirc;
- u32 smiestat;
- u32 smiec;
- u32 _res_94_c0[12];
- u32 smncerrar;
- u32 smncerrxr;
- u32 smncea;
- u32 _res_d0_1fc[76];
- struct mpax sms[16][8];
- struct mpax ses[16][8];
-};
-
-
-void msmc_share_all_segments(int priv_id)
-{
- struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
- int j;
-
- for (j = 0; j < 8; j++) {
- msmc->sms[priv_id][j].mpaxh &= 0xffffff7ful;
- msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
- }
-}
-
-void msmc_map_ses_segment(int priv_id, int ses_pair,
- u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size)
-{
- struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
-
- msmc->ses[priv_id][ses_pair].mpaxh = src_pfn << 12 |
- (size & 0x1f) | 0x80;
- msmc->ses[priv_id][ses_pair].mpaxl = dst_pfn << 8 | 0x3f;
-}
-
-void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
-{
- struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
-
- *mpax++ = msmc->ses[priv_id][ses_pair].mpaxl;
- *mpax = msmc->ses[priv_id][ses_pair].mpaxh;
-}
-
-void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
-{
- struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
-
- msmc->ses[priv_id][ses_pair].mpaxl = *mpax++;
- msmc->ses[priv_id][ses_pair].mpaxh = *mpax;
-}
diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c
deleted file mode 100644
index 237e776..0000000
--- a/arch/arm/cpu/armv7/keystone/psc.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Keystone: PSC configuration module
- *
- * (C) Copyright 2012-2014
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/psc_defs.h>
-
-int psc_delay(void)
-{
- udelay(10);
- return 10;
-}
-
-/*
- * FUNCTION PURPOSE: Wait for end of transitional state
- *
- * DESCRIPTION: Polls pstat for the selected domain and waits for transitions
- * to be complete.
- *
- * Since this is boot loader code it is *ASSUMED* that interrupts
- * are disabled and no other core is mucking around with the psc
- * at the same time.
- *
- * Returns 0 when the domain is free. Returns -1 if a timeout
- * occurred waiting for the completion.
- */
-int psc_wait(u32 domain_num)
-{
- u32 retry;
- u32 ptstat;
-
- /*
- * Do nothing if the power domain is in transition. This should never
- * happen since the boot code is the only software accesses psc.
- * It's still remotely possible that the hardware state machines
- * initiate transitions.
- * Don't trap if the domain (or a module in this domain) is
- * stuck in transition.
- */
- retry = 0;
-
- do {
- ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT);
- ptstat = ptstat & (1 << domain_num);
- } while ((ptstat != 0) && ((retry += psc_delay()) <
- PSC_PTSTAT_TIMEOUT_LIMIT));
-
- if (retry >= PSC_PTSTAT_TIMEOUT_LIMIT)
- return -1;
-
- return 0;
-}
-
-u32 psc_get_domain_num(u32 mod_num)
-{
- u32 domain_num;
-
- /* Get the power domain associated with the module number */
- domain_num = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
- domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
-
- return domain_num;
-}
-
-/*
- * FUNCTION PURPOSE: Power up/down a module
- *
- * DESCRIPTION: Powers up/down the requested module and the associated power
- * domain if required. No action is taken it the module is
- * already powered up/down.
- *
- * This only controls modules. The domain in which the module
- * resides will be left in the power on state. Multiple modules
- * can exist in a power domain, so powering down the domain based
- * on a single module is not done.
- *
- * Returns 0 on success, -1 if the module can't be powered up, or
- * if there is a timeout waiting for the transition.
- */
-int psc_set_state(u32 mod_num, u32 state)
-{
- u32 domain_num;
- u32 pdctl;
- u32 mdctl;
- u32 ptcmd;
- u32 reset_iso;
- u32 v;
-
- /*
- * Get the power domain associated with the module number, and reset
- * isolation functionality
- */
- v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
- domain_num = PSC_REG_MDCFG_GET_PD(v);
- reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v);
-
- /* Wait for the status of the domain/module to be non-transitional */
- if (psc_wait(domain_num) != 0)
- return -1;
-
- /*
- * Perform configuration even if the current status matches the
- * existing state
- *
- * Set the next state of the power domain to on. It's OK if the domain
- * is always on. This code will not ever power down a domain, so no
- * change is made if the new state is power down.
- */
- if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
- pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
- pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
- PSC_REG_VAL_PDCTL_NEXT_ON);
- __raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
- }
-
- /* Set the next state for the module to enabled/disabled */
- mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
- mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
- mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
- __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-
- /* Trigger the enable */
- ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
- ptcmd |= (u32)(1<<domain_num);
- __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
-
- /* Wait on the complete */
- return psc_wait(domain_num);
-}
-
-/*
- * FUNCTION PURPOSE: Power up a module
- *
- * DESCRIPTION: Powers up the requested module and the associated power domain
- * if required. No action is taken it the module is already
- * powered up.
- *
- * Returns 0 on success, -1 if the module can't be powered up, or
- * if there is a timeout waiting for the transition.
- */
-int psc_enable_module(u32 mod_num)
-{
- u32 mdctl;
-
- /* Set the bit to apply reset */
- mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
- if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
- return 0;
-
- return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON);
-}
-
-/*
- * FUNCTION PURPOSE: Power down a module
- *
- * DESCRIPTION: Powers down the requested module.
- *
- * Returns 0 on success, -1 on failure or timeout.
- */
-int psc_disable_module(u32 mod_num)
-{
- u32 mdctl;
-
- /* Set the bit to apply reset */
- mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
- if ((mdctl & 0x3f) == 0)
- return 0;
- mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
- __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-
- return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
-}
-
-/*
- * FUNCTION PURPOSE: Set the reset isolation bit in mdctl
- *
- * DESCRIPTION: The reset isolation enable bit is set. The state of the module
- * is not changed. Returns 0 if the module config showed that
- * reset isolation is supported. Returns 1 otherwise. This is not
- * an error, but setting the bit in mdctl has no effect.
- */
-int psc_set_reset_iso(u32 mod_num)
-{
- u32 v;
- u32 mdctl;
-
- /* Set the reset isolation bit */
- mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
- mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
- __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-
- v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
- if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
- return 0;
-
- return 1;
-}
-
-/*
- * FUNCTION PURPOSE: Disable a power domain
- *
- * DESCRIPTION: The power domain is disabled
- */
-int psc_disable_domain(u32 domain_num)
-{
- u32 pdctl;
- u32 ptcmd;
-
- pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
- pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
- pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
- __raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
-
- ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
- ptcmd |= (u32)(1 << domain_num);
- __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
-
- return psc_wait(domain_num);
-}
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index ce2d92f..1a640bb 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -8,14 +8,214 @@
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/arch/immap_ls102xa.h>
+#include <asm/cache.h>
+#include <asm/system.h>
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#include "fsl_epu.h"
+#define DCSR_RCPM2_BLOCK_OFFSET 0x223000
+#define DCSR_RCPM2_CPMFSMCR0 0x400
+#define DCSR_RCPM2_CPMFSMSR0 0x404
+#define DCSR_RCPM2_CPMFSMCR1 0x414
+#define DCSR_RCPM2_CPMFSMSR1 0x418
+#define CPMFSMSR_FSM_STATE_MASK 0x7f
+
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Bit[1] of the descriptor indicates the descriptor type,
+ * and bit[0] indicates whether the descriptor is valid.
+ */
+#define PMD_TYPE_TABLE 0x3
+#define PMD_TYPE_SECT 0x1
+
+/* AttrIndx[2:0] */
+#define PMD_ATTRINDX(t) ((t) << 2)
+
+/* Section */
+#define PMD_SECT_AF (1 << 10)
+
+#define BLOCK_SIZE_L1 (1UL << 30)
+#define BLOCK_SIZE_L2 (1UL << 21)
+
+/* TTBCR flags */
+#define TTBCR_EAE (1 << 31)
+#define TTBCR_T0SZ(x) ((x) << 0)
+#define TTBCR_T1SZ(x) ((x) << 16)
+#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
+#define TTBCR_IRGN0_NC (0 << 8)
+#define TTBCR_IRGN0_WBWA (1 << 8)
+#define TTBCR_IRGN0_WT (2 << 8)
+#define TTBCR_IRGN0_WBNWA (3 << 8)
+#define TTBCR_IRGN0_MASK (3 << 8)
+#define TTBCR_ORGN0_NC (0 << 10)
+#define TTBCR_ORGN0_WBWA (1 << 10)
+#define TTBCR_ORGN0_WT (2 << 10)
+#define TTBCR_ORGN0_WBNWA (3 << 10)
+#define TTBCR_ORGN0_MASK (3 << 10)
+#define TTBCR_SHARED_NON (0 << 12)
+#define TTBCR_SHARED_OUTER (2 << 12)
+#define TTBCR_SHARED_INNER (3 << 12)
+#define TTBCR_EPD0 (0 << 7)
+#define TTBCR (TTBCR_SHARED_NON | \
+ TTBCR_ORGN0_NC | \
+ TTBCR_IRGN0_NC | \
+ TTBCR_USING_TTBR0 | \
+ TTBCR_EAE)
+
+/*
+ * Memory region attributes for LPAE (defined in pgtable):
+ *
+ * n = AttrIndx[2:0]
+ *
+ * n MAIR
+ * UNCACHED 000 00000000
+ * BUFFERABLE 001 01000100
+ * DEV_WC 001 01000100
+ * WRITETHROUGH 010 10101010
+ * WRITEBACK 011 11101110
+ * DEV_CACHED 011 11101110
+ * DEV_SHARED 100 00000100
+ * DEV_NONSHARED 100 00000100
+ * unused 101
+ * unused 110
+ * WRITEALLOC 111 11111111
+ */
+#define MT_MAIR0 0xeeaa4400
+#define MT_MAIR1 0xff000004
+#define MT_STRONLY_ORDER 0
+#define MT_NORMAL_NC 1
+#define MT_DEVICE_MEM 4
+#define MT_NORMAL 7
+
+/* The phy_addr must be aligned to 4KB */
+static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
+{
+ u32 value = phy_addr | PMD_TYPE_TABLE;
+
+ page_table[2 * index] = value;
+ page_table[2 * index + 1] = 0;
+}
+
+/* The phy_addr must be aligned to 4KB */
+static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
+ u32 memory_type)
+{
+ u64 value;
+
+ value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
+ value |= PMD_ATTRINDX(memory_type);
+ page_table[2 * index] = value & 0xFFFFFFFF;
+ page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
+}
+
+/*
+ * Start MMU after DDR is available, we create MMU table in DRAM.
+ * The base address of TTLB is gd->arch.tlb_addr. We use two
+ * levels of translation tables here to cover 40-bit address space.
+ *
+ * The TTLBs are located at PHY 2G~4G.
+ *
+ * VA mapping:
+ *
+ * ------- <---- 0GB
+ * | |
+ * | |
+ * |-------| <---- 0x24000000
+ * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
+ * |-------| <---- 0x300000000
+ * | |
+ * |-------| <---- 0x34000000
+ * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
+ * |-------| <---- 0x40000000
+ * | |
+ * |-------| <---- 0x80000000 DDR0 space start
+ * |\\\\\\\|
+ *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
+ * |\\\\\\\|
+ * ------- <---- 4GB DDR0 space end
+ */
+static void mmu_setup(void)
+{
+ u32 *level0_table = (u32 *)gd->arch.tlb_addr;
+ u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
+ u64 va_start = 0;
+ u32 reg;
+ int i;
+
+ /* Level 0 Table 2-3 are used to map DDR */
+ set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
+ set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
+ /* Level 0 Table 1 is used to map device */
+ set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
+ /* Level 0 Table 0 is used to map device including PCIe MEM */
+ set_pgtable(level0_table, 0, (u32)level1_table);
+
+ /* Level 1 has 512 entries */
+ for (i = 0; i < 512; i++) {
+ /* Mapping for PCIe 1 */
+ if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
+ va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
+ CONFIG_SYS_PCIE_MMAP_SIZE))
+ set_pgsection(level1_table, i,
+ CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
+ MT_DEVICE_MEM);
+ /* Mapping for PCIe 2 */
+ else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
+ va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
+ CONFIG_SYS_PCIE_MMAP_SIZE))
+ set_pgsection(level1_table, i,
+ CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
+ MT_DEVICE_MEM);
+ else
+ set_pgsection(level1_table, i,
+ va_start,
+ MT_DEVICE_MEM);
+ va_start += BLOCK_SIZE_L2;
+ }
+
+ asm volatile("dsb sy;isb");
+ asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
+ : : "r" (TTBCR) : "memory");
+ asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
+ : : "r" ((u32)level0_table), "r" (0) : "memory");
+ asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
+ : : "r" (MT_MAIR0) : "memory");
+ asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
+ : : "r" (MT_MAIR1) : "memory");
+
+ /* Set the access control to all-supervisor */
+ asm volatile("mcr p15, 0, %0, c3, c0, 0"
+ : : "r" (~0));
+
+ /* Enable the mmu */
+ reg = get_cr();
+ set_cr(reg | CR_M);
+}
+
+/*
+ * This function is called from lib/board.c. It recreates MMU
+ * table in main memory. MMU and i/d-cache are enabled here.
+ */
+void enable_caches(void)
+{
+ /* Invalidate all TLB */
+ mmu_page_table_flush(gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+ /* Set up and enable mmu */
+ mmu_setup();
+
+ /* Invalidate & Enable d-cache */
+ invalidate_dcache_all();
+ set_cr(get_cr() | CR_C);
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
@@ -78,16 +278,6 @@ int print_cpuinfo(void)
}
#endif
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
- icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
- dcache_enable();
-#endif
-}
-
#ifdef CONFIG_FSL_ESDHC
int cpu_mmc_init(bd_t *bis)
{
@@ -107,6 +297,27 @@ int cpu_eth_init(bd_t *bis)
int arch_cpu_init(void)
{
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+ void *rcpm2_base =
+ (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+ u32 state;
+
+ /*
+ * The RCPM FSM state may not be reset after power-on.
+ * So, reset them.
+ */
+ state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
+ CPMFSMSR_FSM_STATE_MASK;
+ if (state != 0) {
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
+ }
+
+ state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
+ CPMFSMSR_FSM_STATE_MASK;
+ if (state != 0) {
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
+ out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
+ }
/*
* After wakeup from deep sleep, Clear EPU registers
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index e601ba1..c01a98f 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -252,6 +252,8 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+ writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
* and RL =7. As the default values of the Mode Registers are not
@@ -265,7 +267,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
- writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
/*
@@ -274,6 +275,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
*/
if (is_dra7xx()) {
do_ext_phy_settings(base, regs);
+ writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
} else {
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 86c0e42..e19c7ae 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -19,7 +19,7 @@
ENTRY(save_boot_params)
ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
str r0, [r1]
- bx lr
+ b save_boot_params_ret
ENDPROC(save_boot_params)
ENTRY(set_pl310_ctrl_reg)
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index a029379..4a0ac2c 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -93,6 +93,21 @@ config TARGET_TWISTER
endchoice
+config DM
+ default y
+
+config DM_GPIO
+ default y if DM
+
+config DM_SERIAL
+ default y if DM
+
+config SYS_MALLOC_F
+ default y if DM
+
+config SYS_MALLOC_F_LEN
+ default 0x400 if DM
+
config SYS_SOC
default "omap3"
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 78577b1..80cb263 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -23,7 +23,7 @@ ENTRY(save_boot_params)
ldr r5, [r0, #0x4]
and r5, r5, #0xff
str r5, [r4]
- bx lr
+ b save_boot_params_ret
ENDPROC(save_boot_params)
#endif
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7d8cec0..5f8daa1 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -141,7 +141,8 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
@@ -151,10 +152,10 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@@ -165,7 +166,8 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
+ .ref_ctrl = 0x000040F1,
+ .ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8,
@@ -175,10 +177,10 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
- .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+ .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
+ .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@@ -186,18 +188,19 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
};
const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
- .sdram_config_init = 0x61851AB2,
- .sdram_config = 0x61851AB2,
+ .sdram_config_init = 0x61862B32,
+ .sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x027F88A8,
+ .ref_ctrl = 0x0000493E,
+ .ref_ctrl_final = 0x0000144A,
+ .sdram_tim1 = 0xD113781C,
+ .sdram_tim2 = 0x308F7FE3,
+ .sdram_tim3 = 0x009F86A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0024400A,
- .emif_ddr_phy_ctlr_1 = 0x0024400A,
+ .emif_ddr_phy_ctlr_1_init = 0x0E24400D,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
.emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
@@ -420,22 +423,22 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
- 0x00BB00BB,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
+ 0x00980098,
+ 0x00340034,
+ 0x00350035,
+ 0x00340034,
+ 0x00310031,
+ 0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
+ 0x00480048,
+ 0x004A004A,
+ 0x00520052,
+ 0x00550055,
+ 0x00500050,
0x00000000,
0x00600020,
0x40010080,
@@ -449,22 +452,22 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
- 0x00BB00BB,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
- 0x00440044,
+ 0x00980098,
+ 0x00330033,
+ 0x00330033,
+ 0x002F002F,
+ 0x00320032,
+ 0x00310031,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
- 0x00600060,
+ 0x00520052,
+ 0x00520052,
+ 0x00470047,
+ 0x00490049,
+ 0x00500050,
0x00000000,
0x00600020,
0x40010080,
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
index 6d94199..3586650 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -21,6 +21,9 @@ config TARGET_KZM9G
config TARGET_ALT
bool "Alt board"
+config TARGET_SILK
+ bool "Silk board"
+
endchoice
config SYS_SOC
@@ -28,7 +31,7 @@ config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
- depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
+ depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK
default n
source "board/atmark-techno/armadillo-800eva/Kconfig"
@@ -37,5 +40,6 @@ source "board/renesas/koelsch/Kconfig"
source "board/renesas/lager/Kconfig"
source "board/kmc/kzm9g/Kconfig"
source "board/renesas/alt/Kconfig"
+source "board/renesas/silk/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
index d47546a..a5dbbea 100644
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -40,7 +40,7 @@ do_lowlevel_init:
and r1, r1, #0x7F00
lsrs r1, r1, #8
cmp r1, #0x4C /* 0x4C is ID of r8a7794 */
- beq _exit_init_l2_a15
+ beq _enable_actlr_smp
/* surpress wfe if ca15 */
tst r4, #4
@@ -64,6 +64,16 @@ do_lowlevel_init:
orrne r0, r0, #0x20 /* L2CTLR[5] */
#endif
mcrne p15, 1, r0, c9, c0, 2
+
+ b _exit_init_l2_a15
+
+_enable_actlr_smp: /* R8A7794 only (CA7) */
+#ifndef CONFIG_DCACHE_OFF
+ mrc p15, 0, r0, c1, c0, 1
+ orr r0, r0, #0x40
+ mcr p15, 0, r0, c1, c0, 1
+#endif
+
_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
index 6288134..bc73813 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig
+++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
@@ -5,11 +5,11 @@ choice
config TARGET_S5P_GONI
bool "S5P Goni board"
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
config TARGET_SMDKC100
bool "Support smdkc100 board"
- select OF_CONTROL if !SPL_BUILD
+ select OF_CONTROL
endchoice
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 70048c1..9b49ece 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -31,9 +31,12 @@
*************************************************************************/
.globl reset
+ .globl save_boot_params_ret
reset:
- bl save_boot_params
+ /* Allow the board to save important registers */
+ b save_boot_params
+save_boot_params_ret:
/*
* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
* except if in HYP mode already
@@ -96,7 +99,7 @@ ENDPROC(c_runtime_cpu_setup)
*
*************************************************************************/
ENTRY(save_boot_params)
- bx lr @ back to my caller
+ b save_boot_params_ret @ back to my caller
ENDPROC(save_boot_params)
.weak save_boot_params
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 48db744..4bb12ad 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y += timer.o
obj-y += board.o
obj-y += clock.o
obj-y += cpu_info.o
+obj-y += dram_helpers.o
obj-y += pinmux.o
obj-y += usbc.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
@@ -38,7 +39,5 @@ obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
-ifdef CONFIG_SPL_FEL
-obj-y += start.o
-endif
+obj-y += fel_utils.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6e28bcd..c02c015 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -27,6 +27,17 @@
#include <linux/compiler.h>
+struct fel_stash {
+ uint32_t sp;
+ uint32_t lr;
+ uint32_t cpsr;
+ uint32_t sctlr;
+ uint32_t vbar;
+ uint32_t cr;
+};
+
+struct fel_stash fel_stash __attribute__((section(".data")));
+
static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
@@ -65,6 +76,12 @@ static int gpio_init(void)
return 0;
}
+void spl_board_load_image(void)
+{
+ debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
+ return_to_fel(fel_stash.sp, fel_stash.lr);
+}
+
void s_init(void)
{
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
@@ -95,7 +112,34 @@ void s_init(void)
*/
u32 spl_boot_device(void)
{
- return BOOT_DEVICE_MMC1;
+#ifdef CONFIG_SPL_FEL
+ /*
+ * This is the legacy compile time configuration for a special FEL
+ * enabled build. It has many restrictions and can only boot over USB.
+ */
+ return BOOT_DEVICE_BOARD;
+#else
+ /*
+ * When booting from the SD card, the "eGON.BT0" signature is expected
+ * to be found in memory at the address 0x0004 (see the "mksunxiboot"
+ * tool, which generates this header).
+ *
+ * When booting in the FEL mode over USB, this signature is patched in
+ * memory and replaced with something else by the 'fel' tool. This other
+ * signature is selected in such a way, that it can't be present in a
+ * valid bootable SD card image (because the BROM would refuse to
+ * execute the SPL in this case).
+ *
+ * This branch is just making a decision at runtime whether to load
+ * the main u-boot binary from the SD card (if the "eGON.BT0" signature
+ * is found) or return to the FEL code in the BROM to wait and receive
+ * the main u-boot binary over USB.
+ */
+ if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
+ return BOOT_DEVICE_MMC1;
+ else
+ return BOOT_DEVICE_BOARD;
+#endif
}
/* No confirmation data available in SPL yet. Hardcode bootmode */
diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk
index 00f5ffc..76ffec9 100644
--- a/arch/arm/cpu/armv7/sunxi/config.mk
+++ b/arch/arm/cpu/armv7/sunxi/config.mk
@@ -1,8 +1,6 @@
# Build a combined spl + u-boot image
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
-ifndef CONFIG_SPL_FEL
ALL-y += u-boot-sunxi-with-spl.bin
endif
endif
-endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram_helpers.c b/arch/arm/cpu/armv7/sunxi/dram_helpers.c
new file mode 100644
index 0000000..9a94e1b
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_helpers.c
@@ -0,0 +1,37 @@
+/*
+ * DRAM init helper functions
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dram.h>
+
+/*
+ * Wait up to 1s for value to be set in given part of reg.
+ */
+void mctl_await_completion(u32 *reg, u32 mask, u32 val)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ while ((readl(reg) & mask) != val) {
+ if (timer_get_us() > tmo)
+ panic("Timeout initialising DRAM\n");
+ }
+}
+
+/*
+ * Test if memory at offset offset matches memory at begin of DRAM
+ */
+bool mctl_mem_matches(u32 offset)
+{
+ /* Try to write different values to RAM at two addresses */
+ writel(0, CONFIG_SYS_SDRAM_BASE);
+ writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
+ /* Check if the same value is actually observed when reading back */
+ return readl(CONFIG_SYS_SDRAM_BASE) ==
+ readl(CONFIG_SYS_SDRAM_BASE + offset);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/fel_utils.S b/arch/arm/cpu/armv7/sunxi/fel_utils.S
new file mode 100644
index 0000000..bf00335
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/fel_utils.S
@@ -0,0 +1,42 @@
+/*
+ * Utility functions for FEL mode.
+ *
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+ ldr r0, =fel_stash
+ str sp, [r0, #0]
+ str lr, [r0, #4]
+ mrs lr, cpsr @ Read CPSR
+ str lr, [r0, #8]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
+ str lr, [r0, #12]
+ mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
+ str lr, [r0, #16]
+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
+ str lr, [r0, #20]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+ENTRY(return_to_fel)
+ mov sp, r0
+ mov lr, r1
+ ldr r0, =fel_stash
+ ldr r1, [r0, #20]
+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
+ ldr r1, [r0, #16]
+ mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
+ ldr r1, [r0, #12]
+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
+ ldr r1, [r0, #8]
+ msr cpsr, r1 @ Write CPSR
+ bx lr
+ENDPROC(return_to_fel)
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
deleted file mode 100644
index 928b7c1..0000000
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2013
- * Henrik Nordstrom <henrik@henriknordstrom.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(s_init)
-SECTIONS
-{
- . = 0x00002000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text.s_init)
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
- . = .;
-
- . = ALIGN(4);
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- . = ALIGN(4);
- .note.gnu.build-id :
- {
- *(.note.gnu.build-id)
- }
- _end = .;
-
- . = ALIGN(4096);
- .mmutable : {
- *(.mmutable)
- }
-
- .bss_start __rel_dyn_start (OVERLAY) : {
- KEEP(*(.__bss_start));
- __bss_base = .;
- }
-
- .bss __bss_base (OVERLAY) : {
- *(.bss*)
- . = ALIGN(4);
- __bss_limit = .;
- }
-
- .bss_end __bss_limit (OVERLAY) : {
- KEEP(*(.__bss_end));
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
- /DISCARD/ : { *(.note*) }
-}
diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig
deleted file mode 100644
index 1446452..0000000
--- a/arch/arm/cpu/armv7/tegra-common/Kconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-if TEGRA
-
-choice
- prompt "Tegra SoC select"
-
-config TEGRA20
- bool "Tegra20 family"
-
-config TEGRA30
- bool "Tegra30 family"
-
-config TEGRA114
- bool "Tegra114 family"
-
-config TEGRA124
- bool "Tegra124 family"
-
-endchoice
-
-config USE_PRIVATE_LIBGCC
- default y if SPL_BUILD
-
-source "arch/arm/cpu/armv7/tegra20/Kconfig"
-source "arch/arm/cpu/armv7/tegra30/Kconfig"
-source "arch/arm/cpu/armv7/tegra114/Kconfig"
-source "arch/arm/cpu/armv7/tegra124/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/tegra-common/Makefile b/arch/arm/cpu/armv7/tegra-common/Makefile
deleted file mode 100644
index 463c260..0000000
--- a/arch/arm/cpu/armv7/tegra-common/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
diff --git a/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c b/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c
deleted file mode 100644
index a94ec93..0000000
--- a/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
- *
- * Derived from code (arch/arm/lib/reset.c) that is:
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * (C) Copyright 2004 Texas Insturments
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/pmc.h>
-
-static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- puts("Entering RCM...\n");
- udelay(50000);
-
- pmc->pmc_scratch0 = 2;
- disable_interrupts();
- reset_cpu(0);
-
- return 0;
-}
-
-U_BOOT_CMD(
- enterrcm, 1, 0, do_enterrcm,
- "reset Tegra and enter USB Recovery Mode",
- ""
-);
diff --git a/arch/arm/cpu/armv7/tegra114/Kconfig b/arch/arm/cpu/armv7/tegra114/Kconfig
deleted file mode 100644
index 31012bc..0000000
--- a/arch/arm/cpu/armv7/tegra114/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TEGRA114
-
-choice
- prompt "Tegra114 board select"
-
-config TARGET_DALMORE
- bool "NVIDIA Tegra114 Dalmore evaluation board"
-
-endchoice
-
-config SYS_SOC
- default "tegra114"
-
-source "board/nvidia/dalmore/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/tegra124/Kconfig b/arch/arm/cpu/armv7/tegra124/Kconfig
deleted file mode 100644
index 88f627c..0000000
--- a/arch/arm/cpu/armv7/tegra124/Kconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-if TEGRA124
-
-choice
- prompt "Tegra124 board select"
-
-config TARGET_JETSON_TK1
- bool "NVIDIA Tegra124 Jetson TK1 board"
-
-config TARGET_NYAN_BIG
- bool "Google/NVIDIA Nyan-big Chrombook"
- help
- Nyan Big is a Tegra124 clamshell board that is very similar
- to venice2, but it has a different panel, the sdcard CD and WP
- sense are flipped, and it has a different revision of the AS3722
- PMIC. The retail name is the Acer Chromebook 13 CB5-311-T7NN
- (13.3-inch HD, NVIDIA Tegra K1, 2GB).
-
-config TARGET_VENICE2
- bool "NVIDIA Tegra124 Venice2"
-
-endchoice
-
-config SYS_SOC
- default "tegra124"
-
-source "board/nvidia/jetson-tk1/Kconfig"
-source "board/nvidia/nyan-big/Kconfig"
-source "board/nvidia/venice2/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/tegra20/Kconfig b/arch/arm/cpu/armv7/tegra20/Kconfig
deleted file mode 100644
index a354e2a..0000000
--- a/arch/arm/cpu/armv7/tegra20/Kconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-if TEGRA20
-
-choice
- prompt "Tegra20 board select"
-
-config TARGET_HARMONY
- bool "NVIDIA Tegra20 Harmony evaluation board"
-
-config TARGET_MEDCOM_WIDE
- bool "Avionic Design Medcom-Wide board"
-
-config TARGET_PAZ00
- bool "Paz00 board"
-
-config TARGET_PLUTUX
- bool "Avionic Design Plutux board"
-
-config TARGET_SEABOARD
- bool "NVIDIA Seaboard"
-
-config TARGET_TEC
- bool "Avionic Design Tamonten Evaluation Carrier"
-
-config TARGET_TRIMSLICE
- bool "Compulab TrimSlice board"
-
-config TARGET_VENTANA
- bool "NVIDIA Tegra20 Ventana evaluation board"
-
-config TARGET_WHISTLER
- bool "NVIDIA Tegra20 Whistler evaluation board"
-
-config TARGET_COLIBRI_T20_IRIS
- bool "Toradex Colibri T20 board"
-
-endchoice
-
-config SYS_SOC
- default "tegra20"
-
-source "board/nvidia/harmony/Kconfig"
-source "board/avionic-design/medcom-wide/Kconfig"
-source "board/compal/paz00/Kconfig"
-source "board/avionic-design/plutux/Kconfig"
-source "board/nvidia/seaboard/Kconfig"
-source "board/avionic-design/tec/Kconfig"
-source "board/compulab/trimslice/Kconfig"
-source "board/nvidia/ventana/Kconfig"
-source "board/nvidia/whistler/Kconfig"
-source "board/toradex/colibri_t20_iris/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile
deleted file mode 100644
index 9b4295c..0000000
--- a/arch/arm/cpu/armv7/tegra20/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_PWM_TEGRA) += pwm.o
-obj-$(CONFIG_VIDEO_TEGRA) += display.o
diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c
deleted file mode 100644
index 61efed6..0000000
--- a/arch/arm/cpu/armv7/tegra20/display.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * (C) Copyright 2010
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch/display.h>
-#include <asm/arch/dc.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
-
-static struct fdt_disp_config config;
-
-static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
-{
- unsigned h_dda, v_dda;
- unsigned long val;
-
- val = readl(&dc->cmd.disp_win_header);
- val |= WINDOW_A_SELECT;
- writel(val, &dc->cmd.disp_win_header);
-
- writel(win->fmt, &dc->win.color_depth);
-
- clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
- BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
-
- val = win->out_x << H_POSITION_SHIFT;
- val |= win->out_y << V_POSITION_SHIFT;
- writel(val, &dc->win.pos);
-
- val = win->out_w << H_SIZE_SHIFT;
- val |= win->out_h << V_SIZE_SHIFT;
- writel(val, &dc->win.size);
-
- val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
- val |= win->h << V_PRESCALED_SIZE_SHIFT;
- writel(val, &dc->win.prescaled_size);
-
- writel(0, &dc->win.h_initial_dda);
- writel(0, &dc->win.v_initial_dda);
-
- h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
- v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
-
- val = h_dda << H_DDA_INC_SHIFT;
- val |= v_dda << V_DDA_INC_SHIFT;
- writel(val, &dc->win.dda_increment);
-
- writel(win->stride, &dc->win.line_stride);
- writel(0, &dc->win.buf_stride);
-
- val = WIN_ENABLE;
- if (win->bpp < 24)
- val |= COLOR_EXPAND;
- writel(val, &dc->win.win_opt);
-
- writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
- writel(win->x, &dc->winbuf.addr_h_offset);
- writel(win->y, &dc->winbuf.addr_v_offset);
-
- writel(0xff00, &dc->win.blend_nokey);
- writel(0xff00, &dc->win.blend_1win);
-
- val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
- val |= GENERAL_UPDATE | WIN_A_UPDATE;
- writel(val, &dc->cmd.state_ctrl);
-}
-
-static void write_pair(struct fdt_disp_config *config, int item, u32 *reg)
-{
- writel(config->horiz_timing[item] |
- (config->vert_timing[item] << 16), reg);
-}
-
-static int update_display_mode(struct dc_disp_reg *disp,
- struct fdt_disp_config *config)
-{
- unsigned long val;
- unsigned long rate;
- unsigned long div;
-
- writel(0x0, &disp->disp_timing_opt);
- write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
- write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
- write_pair(config, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
- write_pair(config, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
-
- writel(config->width | (config->height << 16), &disp->disp_active);
-
- val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
- val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
- writel(val, &disp->data_enable_opt);
-
- val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
- val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
- val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
- writel(val, &disp->disp_interface_ctrl);
-
- /*
- * The pixel clock divider is in 7.1 format (where the bottom bit
- * represents 0.5). Here we calculate the divider needed to get from
- * the display clock (typically 600MHz) to the pixel clock. We round
- * up or down as requried.
- */
- rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
- div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2;
- debug("Display clock %lu, divider %lu\n", rate, div);
-
- writel(0x00010001, &disp->shift_clk_opt);
-
- val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
- val |= div << SHIFT_CLK_DIVIDER_SHIFT;
- writel(val, &disp->disp_clk_ctrl);
-
- return 0;
-}
-
-/* Start up the display and turn on power to PWMs */
-static void basic_init(struct dc_cmd_reg *cmd)
-{
- u32 val;
-
- writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
- writel(0x0000011a, &cmd->cont_syncpt_vsync);
- writel(0x00000000, &cmd->int_type);
- writel(0x00000000, &cmd->int_polarity);
- writel(0x00000000, &cmd->int_mask);
- writel(0x00000000, &cmd->int_enb);
-
- val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
- val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
- val |= PM1_ENABLE;
- writel(val, &cmd->disp_pow_ctrl);
-
- val = readl(&cmd->disp_cmd);
- val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
- writel(val, &cmd->disp_cmd);
-}
-
-static void basic_init_timer(struct dc_disp_reg *disp)
-{
- writel(0x00000020, &disp->mem_high_pri);
- writel(0x00000001, &disp->mem_high_pri_timer);
-}
-
-static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
- 0x00000000,
- 0x01000000,
- 0x00000000,
- 0x00000000,
-};
-
-static const u32 rgb_data_tab[PIN_REG_COUNT] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00210222,
- 0x00002200,
- 0x00020000,
-};
-
-static void rgb_enable(struct dc_com_reg *com)
-{
- int i;
-
- for (i = 0; i < PIN_REG_COUNT; i++) {
- writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
- writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
- writel(rgb_data_tab[i], &com->pin_output_data[i]);
- }
-
- for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
- writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
-}
-
-static int setup_window(struct disp_ctl_win *win,
- struct fdt_disp_config *config)
-{
- win->x = 0;
- win->y = 0;
- win->w = config->width;
- win->h = config->height;
- win->out_x = 0;
- win->out_y = 0;
- win->out_w = config->width;
- win->out_h = config->height;
- win->phys_addr = config->frame_buffer;
- win->stride = config->width * (1 << config->log2_bpp) / 8;
- debug("%s: depth = %d\n", __func__, config->log2_bpp);
- switch (config->log2_bpp) {
- case 5:
- case 24:
- win->fmt = COLOR_DEPTH_R8G8B8A8;
- win->bpp = 32;
- break;
- case 4:
- win->fmt = COLOR_DEPTH_B5G6R5;
- win->bpp = 16;
- break;
-
- default:
- debug("Unsupported LCD bit depth");
- return -1;
- }
-
- return 0;
-}
-
-struct fdt_disp_config *tegra_display_get_config(void)
-{
- return config.valid ? &config : NULL;
-}
-
-static void debug_timing(const char *name, unsigned int timing[])
-{
-#ifdef DEBUG
- int i;
-
- debug("%s timing: ", name);
- for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
- debug("%d ", timing[i]);
- debug("\n");
-#endif
-}
-
-/**
- * Decode panel information from the fdt, according to a standard binding
- *
- * @param blob fdt blob
- * @param node offset of fdt node to read from
- * @param config structure to store fdt config into
- * @return 0 if ok, -ve on error
- */
-static int tegra_decode_panel(const void *blob, int node,
- struct fdt_disp_config *config)
-{
- int front, back, ref;
-
- config->width = fdtdec_get_int(blob, node, "xres", -1);
- config->height = fdtdec_get_int(blob, node, "yres", -1);
- config->pixel_clock = fdtdec_get_int(blob, node, "clock", 0);
- if (!config->pixel_clock || config->width == -1 ||
- config->height == -1) {
- debug("%s: Pixel parameters missing\n", __func__);
- return -FDT_ERR_NOTFOUND;
- }
-
- back = fdtdec_get_int(blob, node, "left-margin", -1);
- front = fdtdec_get_int(blob, node, "right-margin", -1);
- ref = fdtdec_get_int(blob, node, "hsync-len", -1);
- if ((back | front | ref) == -1) {
- debug("%s: Horizontal parameters missing\n", __func__);
- return -FDT_ERR_NOTFOUND;
- }
-
- /* Use a ref-to-sync of 1 always, and take this from the front porch */
- config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
- config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
- config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
- config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
- config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
- debug_timing("horiz", config->horiz_timing);
-
- back = fdtdec_get_int(blob, node, "upper-margin", -1);
- front = fdtdec_get_int(blob, node, "lower-margin", -1);
- ref = fdtdec_get_int(blob, node, "vsync-len", -1);
- if ((back | front | ref) == -1) {
- debug("%s: Vertical parameters missing\n", __func__);
- return -FDT_ERR_NOTFOUND;
- }
-
- config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
- config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
- config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
- config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
- config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
- debug_timing("vert", config->vert_timing);
-
- return 0;
-}
-
-/**
- * Decode the display controller information from the fdt.
- *
- * @param blob fdt blob
- * @param config structure to store fdt config into
- * @return 0 if ok, -ve on error
- */
-static int tegra_display_decode_config(const void *blob,
- struct fdt_disp_config *config)
-{
- int node, rgb;
- int bpp, bit;
-
- /* TODO: Support multiple controllers */
- node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC);
- if (node < 0) {
- debug("%s: Cannot find display controller node in fdt\n",
- __func__);
- return node;
- }
- config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg");
- if (!config->disp) {
- debug("%s: No display controller address\n", __func__);
- return -1;
- }
-
- rgb = fdt_subnode_offset(blob, node, "rgb");
-
- config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
- if (config->panel_node < 0) {
- debug("%s: Cannot find panel information\n", __func__);
- return -1;
- }
-
- if (tegra_decode_panel(blob, config->panel_node, config)) {
- debug("%s: Failed to decode panel information\n", __func__);
- return -1;
- }
-
- bpp = fdtdec_get_int(blob, config->panel_node, "nvidia,bits-per-pixel",
- -1);
- bit = ffs(bpp) - 1;
- if (bpp == (1 << bit))
- config->log2_bpp = bit;
- else
- config->log2_bpp = bpp;
- if (bpp == -1) {
- debug("%s: Pixel bpp parameters missing\n", __func__);
- return -FDT_ERR_NOTFOUND;
- }
- config->bpp = bpp;
-
- config->valid = 1; /* we have a valid configuration */
-
- return 0;
-}
-
-int tegra_display_probe(const void *blob, void *default_lcd_base)
-{
- struct disp_ctl_win window;
- struct dc_ctlr *dc;
-
- if (tegra_display_decode_config(blob, &config))
- return -1;
-
- config.frame_buffer = (u32)default_lcd_base;
-
- dc = (struct dc_ctlr *)config.disp;
-
- /*
- * A header file for clock constants was NAKed upstream.
- * TODO: Put this into the FDT and fdt_lcd struct when we have clock
- * support there
- */
- clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
- 144 * 1000000);
- clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
- 600 * 1000000);
- basic_init(&dc->cmd);
- basic_init_timer(&dc->disp);
- rgb_enable(&dc->com);
-
- if (config.pixel_clock)
- update_display_mode(&dc->disp, &config);
-
- if (setup_window(&window, &config))
- return -1;
-
- update_window(dc, &window);
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/tegra20/pwm.c b/arch/arm/cpu/armv7/tegra20/pwm.c
deleted file mode 100644
index 5b88636..0000000
--- a/arch/arm/cpu/armv7/tegra20/pwm.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Tegra2 pulse width frequency modulator definitions
- *
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/pwm.h>
-
-struct pwm_info {
- struct pwm_ctlr *pwm; /* Registers for our pwm controller */
- int pwm_node; /* PWM device tree node */
-} local;
-
-void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider)
-{
- u32 reg;
-
- assert(channel < PWM_NUM_CHANNELS);
-
- /* TODO: Can we use clock_adjust_periph_pll_div() here? */
- clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate);
-
- reg = PWM_ENABLE_MASK;
- reg |= pulse_width << PWM_WIDTH_SHIFT;
- reg |= freq_divider << PWM_DIVIDER_SHIFT;
- writel(reg, &local.pwm[channel].control);
- debug("%s: channel=%d, rate=%d\n", __func__, channel, rate);
-}
-
-int pwm_request(const void *blob, int node, const char *prop_name)
-{
- int pwm_node;
- u32 data[3];
-
- if (fdtdec_get_int_array(blob, node, prop_name, data,
- ARRAY_SIZE(data))) {
- debug("%s: Cannot decode PWM property '%s'\n", __func__,
- prop_name);
- return -1;
- }
-
- pwm_node = fdt_node_offset_by_phandle(blob, data[0]);
- if (pwm_node != local.pwm_node) {
- debug("%s: PWM property '%s' phandle %d not recognised"
- "- expecting %d\n", __func__, prop_name, data[0],
- local.pwm_node);
- return -1;
- }
- if (data[1] >= PWM_NUM_CHANNELS) {
- debug("%s: PWM property '%s': invalid channel %u\n", __func__,
- prop_name, data[1]);
- return -1;
- }
-
- /*
- * TODO: We could maintain a list of requests, but it might not be
- * worth it for U-Boot.
- */
- return data[1];
-}
-
-int pwm_init(const void *blob)
-{
- local.pwm_node = fdtdec_next_compatible(blob, 0,
- COMPAT_NVIDIA_TEGRA20_PWM);
- if (local.pwm_node < 0) {
- debug("%s: Cannot find device tree node\n", __func__);
- return -1;
- }
-
- local.pwm = (struct pwm_ctlr *)fdtdec_get_addr(blob, local.pwm_node,
- "reg");
- if (local.pwm == (struct pwm_ctlr *)FDT_ADDR_T_NONE) {
- debug("%s: Cannot find pwm reg address\n", __func__);
- return -1;
- }
- debug("Tegra PWM at %p, node %d\n", local.pwm, local.pwm_node);
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/tegra30/Kconfig b/arch/arm/cpu/armv7/tegra30/Kconfig
deleted file mode 100644
index 3abdc7b..0000000
--- a/arch/arm/cpu/armv7/tegra30/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-if TEGRA30
-
-choice
- prompt "Tegra30 board select"
-
-config TARGET_APALIS_T30
- bool "Toradex Apalis T30 board"
-
-config TARGET_BEAVER
- bool "NVIDIA Tegra30 Beaver evaluation board"
-
-config TARGET_CARDHU
- bool "NVIDIA Tegra30 Cardhu evaluation board"
-
-config TARGET_COLIBRI_T30
- bool "Toradex Colibri T30 board"
-
-config TARGET_TEC_NG
- bool "Avionic Design TEC-NG board"
-
-endchoice
-
-config SYS_SOC
- default "tegra30"
-
-source "board/toradex/apalis_t30/Kconfig"
-source "board/nvidia/beaver/Kconfig"
-source "board/nvidia/cardhu/Kconfig"
-source "board/toradex/colibri_t30/Kconfig"
-source "board/avionic-design/tec-ng/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
index 5c5a84f..8335685 100644
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -48,6 +48,12 @@ config DCC_MICRO_SUPPORT_CARD
endchoice
+config SYS_MALLOC_F
+ default y
+
+config SYS_MALLOC_F_LEN
+ default 0x400
+
config CMD_PINMON
bool "Enable boot mode pins monitor command"
default y
@@ -58,14 +64,12 @@ config CMD_PINMON
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
- depends on !SPL_BUILD
help
The command "ddrphy" shows the resulting parameters of DDR PHY
training; it is useful for the evaluation of DDR PHY training.
choice
prompt "DDR3 Frequency select"
- depends on SPL_BUILD
config DDR_FREQ_1600
bool "DDR3 1600"
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index 9c6e824..fa447bc 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -155,3 +155,9 @@ ENTRY(__asm_invalidate_icache_all)
isb sy
ret
ENDPROC(__asm_invalidate_icache_all)
+
+ENTRY(__asm_flush_l3_cache)
+ mov x0, #0 /* return status as success */
+ ret
+ENDPROC(__asm_flush_l3_cache)
+ .weak __asm_flush_l3_cache
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 9dbcdf2..c5ec529 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -73,17 +73,21 @@ void invalidate_dcache_all(void)
__asm_invalidate_dcache_all();
}
-void __weak flush_l3_cache(void)
-{
-}
-
/*
- * Performs a clean & invalidation of the entire data cache at all levels
+ * Performs a clean & invalidation of the entire data cache at all levels.
+ * This function needs to be inline to avoid using stack.
+ * __asm_flush_l3_cache return status of timeout
*/
-void flush_dcache_all(void)
+inline void flush_dcache_all(void)
{
+ int ret;
+
__asm_flush_dcache_all();
- flush_l3_cache();
+ ret = __asm_flush_l3_cache();
+ if (ret)
+ debug("flushing dcache returns 0x%x\n", ret);
+ else
+ debug("flushing dcache successfully.\n");
}
/*
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 47b947f..4997487 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -10,10 +10,10 @@
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl-mc/fsl_mc.h>
#include "cpu.h"
#include "mp.h"
#include "speed.h"
-#include <fsl_mc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -150,7 +150,7 @@ static inline void final_mmu_setup(void)
* set level 2 table 0 to cache-inhibit, covering 0 to 1GB
*/
section_l1t0 = 0;
- section_l1t1 = BLOCK_SIZE_L0;
+ section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE;
section_l2 = 0;
for (i = 0; i < 512; i++) {
set_pgtable_section(level1_table_0, i, section_l1t0,
@@ -168,10 +168,10 @@ static inline void final_mmu_setup(void)
(u64)level2_table_0 | PMD_TYPE_TABLE;
level1_table_0[2] =
0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
- PMD_ATTRINDX(MT_NORMAL);
+ PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
level1_table_0[3] =
0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
- PMD_ATTRINDX(MT_NORMAL);
+ PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL);
/* Rewrite table to enable cache */
set_pgtable_section(level2_table_0,
@@ -243,59 +243,6 @@ int arch_cpu_init(void)
}
/*
- * flush_l3_cache
- * Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power
- * state, by writing to HP-F P-state request register.
- * Fixme: This function should moved to a common file if other SoCs also use
- * the same Dickens.
- */
-#define HNF0_PSTATE_REQ 0x04200010
-#define HNF1_PSTATE_REQ 0x04210010
-#define HNF2_PSTATE_REQ 0x04220010
-#define HNF3_PSTATE_REQ 0x04230010
-#define HNF4_PSTATE_REQ 0x04240010
-#define HNF5_PSTATE_REQ 0x04250010
-#define HNF6_PSTATE_REQ 0x04260010
-#define HNF7_PSTATE_REQ 0x04270010
-#define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC)
-#define HNFPSTAT_FAM 0x3
-#define HNFPSTAT_SFONLY 0x01
-
-static void hnf_pstate_req(u64 *ptr, u64 state)
-{
- int timeout = 1000;
- out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3));
- ptr++;
- /* checking if the transition is completed */
- while (timeout > 0) {
- if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3))
- break;
- udelay(100);
- timeout--;
- }
-}
-
-void flush_l3_cache(void)
-{
- hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY);
- hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM);
- hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM);
-}
-
-/*
* This function is called from lib/board.c.
* It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
* There is no need to disable d-cache for this operation.
@@ -420,6 +367,7 @@ int print_cpuinfo(void)
printf("\n Bus: %-4s MHz ",
strmhz(buf, sysinfo.freq_systembus));
printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
+ printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2));
puts("\n");
return 0;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
index e392eb9..7eb9b6a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -16,7 +16,7 @@ void ft_fixup_cpu(void *blob)
__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
fdt32_t *reg;
int addr_cells;
- u64 val;
+ u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
off = fdt_path_offset(blob, "/cpus");
@@ -29,15 +29,20 @@ void ft_fixup_cpu(void *blob)
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
+ core_id = of_read_number(reg, addr_cells);
if (reg) {
- val = spin_tbl_addr;
- val += id_to_core(of_read_number(reg, addr_cells))
- * SPIN_TABLE_ELEM_SIZE;
- val = cpu_to_fdt64(val);
- fdt_setprop_string(blob, off, "enable-method",
- "spin-table");
- fdt_setprop(blob, off, "cpu-release-addr",
- &val, sizeof(val));
+ if (core_id == 0 || (is_core_online(core_id))) {
+ val = spin_tbl_addr;
+ val += id_to_core(core_id) *
+ SPIN_TABLE_ELEM_SIZE;
+ val = cpu_to_fdt64(val);
+ fdt_setprop_string(blob, off, "enable-method",
+ "spin-table");
+ fdt_setprop(blob, off, "cpu-release-addr",
+ &val, sizeof(val));
+ } else {
+ debug("skipping offline core\n");
+ }
} else {
puts("Warning: found cpu node without reg property\n");
}
@@ -55,4 +60,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_MP
ft_fixup_cpu(blob);
#endif
+
+#ifdef CONFIG_SYS_NS16550
+ do_fixup_by_compat_u32(blob, "ns16550",
+ "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+#endif
}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index 2a88aab..886576e 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -42,10 +42,142 @@ ENTRY(lowlevel_init)
ldr x0, =secondary_boot_func
blr x0
2:
+
+#ifdef CONFIG_FSL_TZPC_BP147
+ /* Set Non Secure access for all devices protected via TZPC */
+ ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
+ orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
+ str w0, [x1]
+
+ isb
+ dsb sy
+#endif
+
+#ifdef CONFIG_FSL_TZASC_400
+ /* Set TZASC so that:
+ * a. We use only Region0 whose global secure write/read is EN
+ * b. We use only Region0 whose NSAID write/read is EN
+ *
+ * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
+ * placeholders.
+ */
+ ldr x1, =TZASC_GATE_KEEPER(0)
+ ldr x0, [x1] /* Filter 0 Gate Keeper Register */
+ orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
+ str x0, [x1]
+
+ ldr x1, =TZASC_GATE_KEEPER(1)
+ ldr x0, [x1] /* Filter 0 Gate Keeper Register */
+ orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */
+ str x0, [x1]
+
+ ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
+ ldr x0, [x1] /* Region-0 Attributes Register */
+ orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
+ orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
+ str x0, [x1]
+
+ ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
+ ldr x0, [x1] /* Region-1 Attributes Register */
+ orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */
+ orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */
+ str x0, [x1]
+
+ ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
+ ldr w0, [x1] /* Region-0 Access Register */
+ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
+ str w0, [x1]
+
+ ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
+ ldr w0, [x1] /* Region-1 Attributes Register */
+ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
+ str w0, [x1]
+
+ isb
+ dsb sy
+#endif
mov lr, x29 /* Restore LR */
ret
ENDPROC(lowlevel_init)
+hnf_pstate_poll:
+ /* x0 has the desired status, return 0 for success, 1 for timeout
+ * clobber x1, x2, x3, x4, x6, x7
+ */
+ mov x1, x0
+ mov x7, #0 /* flag for timeout */
+ mrs x3, cntpct_el0 /* read timer */
+ add x3, x3, #1200 /* timeout after 100 microseconds */
+ mov x0, #0x18
+ movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
+ mov w6, #8 /* HN-F node count */
+1:
+ ldr x2, [x0]
+ cmp x2, x1 /* check status */
+ b.eq 2f
+ mrs x4, cntpct_el0
+ cmp x4, x3
+ b.ls 1b
+ mov x7, #1 /* timeout */
+ b 3f
+2:
+ add x0, x0, #0x10000 /* move to next node */
+ subs w6, w6, #1
+ cbnz w6, 1b
+3:
+ mov x0, x7
+ ret
+
+hnf_set_pstate:
+ /* x0 has the desired state, clobber x1, x2, x6 */
+ mov x1, x0
+ /* power state to SFONLY */
+ mov w6, #8 /* HN-F node count */
+ mov x0, #0x10
+ movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
+1: /* set pstate to sfonly */
+ ldr x2, [x0]
+ and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
+ orr x2, x2, x1
+ str x2, [x0]
+ add x0, x0, #0x10000 /* move to next node */
+ subs w6, w6, #1
+ cbnz w6, 1b
+
+ ret
+
+ENTRY(__asm_flush_l3_cache)
+ /*
+ * Return status in x0
+ * success 0
+ * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
+ */
+ mov x29, lr
+ mov x8, #0
+
+ dsb sy
+ mov x0, #0x1 /* HNFPSTAT_SFONLY */
+ bl hnf_set_pstate
+
+ mov x0, #0x4 /* SFONLY status */
+ bl hnf_pstate_poll
+ cbz x0, 1f
+ mov x8, #1 /* timeout */
+1:
+ dsb sy
+ mov x0, #0x3 /* HNFPSTAT_FAM */
+ bl hnf_set_pstate
+
+ mov x0, #0xc /* FAM status */
+ bl hnf_pstate_poll
+ cbz x0, 1f
+ add x8, x8, #0x2
+1:
+ mov x0, x8
+ mov lr, x29
+ ret
+ENDPROC(__asm_flush_l3_cache)
+
/* Keep literals not used by the secondary boot code outside it */
.ltorg
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
index 94998bf..ce9c0c1 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
@@ -83,6 +83,14 @@ int is_core_valid(unsigned int core)
return !!((1 << core) & cpu_mask());
}
+int is_core_online(u64 cpu_id)
+{
+ u64 *table;
+ int pos = id_to_core(cpu_id);
+ table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
+ return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
+}
+
int cpu_reset(int nr)
{
puts("Feature is not implemented.\n");
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
index 06ac0bc..66144d6 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
@@ -32,5 +32,6 @@ int fsl_lsch3_wake_seconday_cores(void);
void *get_spin_tbl_addr(void);
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
+int is_core_online(u64 cpu_id);
#endif
#endif /* _FSL_CH3_MP_H */
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
index dc4a34b..72cd999 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -77,8 +77,10 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+ sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
#else
sys_info->freq_ddrbus = sysclk;
+ sys_info->freq_ddrbus2 = sysclk;
#endif
sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
@@ -87,6 +89,9 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
+ sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
+ FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
/*
@@ -129,7 +134,7 @@ int get_clocks(void)
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
-
+ gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#if defined(CONFIG_FSL_ESDHC)
gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif /* defined(CONFIG_FSL_ESDHC) */
@@ -156,11 +161,18 @@ ulong get_bus_freq(ulong dummy)
* get_ddr_freq
* return ddr bus freq in Hz
*********************************************/
-ulong get_ddr_freq(ulong dummy)
+ulong get_ddr_freq(ulong ctrl_num)
{
if (!gd->mem_clk)
get_clocks();
+ /*
+ * DDR controller 0 & 1 are on memory complex 0
+ * DDR controler 2 is on memory complext 1
+ */
+ if (ctrl_num >= 2)
+ return gd->arch.mem2_clk;
+
return gd->mem_clk;
}
diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile
deleted file mode 100644
index 03614d4..0000000
--- a/arch/arm/cpu/at91-common/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2013 Atmel Corporation
-# Bo Shen <voice.shen@atmel.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
-ifneq ($(CONFIG_SPL_BUILD),)
-obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
-obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
-obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
-obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
-obj-y += spl.o
-endif
diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c
deleted file mode 100644
index beec13d..0000000
--- a/arch/arm/cpu/at91-common/mpddrc.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Copyright (C) 2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/atmel_mpddrc.h>
-
-static inline void atmel_mpddr_op(int mode, u32 ram_address)
-{
- struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
-
- writel(mode, &mpddr->mr);
- writel(0, ram_address);
-}
-
-static int ddr2_decodtype_is_seq(u32 cr)
-{
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
- if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
- return 0;
-#endif
- return 1;
-}
-
-int ddr2_init(const unsigned int ram_address,
- const struct atmel_mpddr *mpddr_value)
-{
- struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
- u32 ba_off, cr;
-
- /* Compute bank offset according to NC in configuration register */
- ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
- if (ddr2_decodtype_is_seq(mpddr_value->cr))
- ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
-
- ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
-
- /* Program the memory device type into the memory device register */
- writel(mpddr_value->md, &mpddr->md);
-
- /* Program the configuration register */
- writel(mpddr_value->cr, &mpddr->cr);
-
- /* Program the timing register */
- writel(mpddr_value->tpr0, &mpddr->tpr0);
- writel(mpddr_value->tpr1, &mpddr->tpr1);
- writel(mpddr_value->tpr2, &mpddr->tpr2);
-
- /* Issue a NOP command */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
-
- /* A 200 us is provided to precede any signal toggle */
- udelay(200);
-
- /* Issue a NOP command */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
-
- /* Issue an all banks precharge command */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
-
- /* Issue an extended mode register set(EMRS2) to choose operation */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
- ram_address + (0x2 << ba_off));
-
- /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
- ram_address + (0x3 << ba_off));
-
- /*
- * Issue an extended mode register set(EMRS1) to enable DLL and
- * program D.I.C (output driver impedance control)
- */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
- ram_address + (0x1 << ba_off));
-
- /* Enable DLL reset */
- cr = readl(&mpddr->cr);
- writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
-
- /* A mode register set(MRS) cycle is issued to reset DLL */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
-
- /* Issue an all banks precharge command */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
-
- /* Two auto-refresh (CBR) cycles are provided */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
-
- /* Disable DLL reset */
- cr = readl(&mpddr->cr);
- writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
-
- /* A mode register set (MRS) cycle is issued to disable DLL reset */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
-
- /* Set OCD calibration in default state */
- cr = readl(&mpddr->cr);
- writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
-
- /*
- * An extended mode register set (EMRS1) cycle is issued
- * to OCD default value
- */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
- ram_address + (0x1 << ba_off));
-
- /* OCD calibration mode exit */
- cr = readl(&mpddr->cr);
- writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
-
- /*
- * An extended mode register set (EMRS1) cycle is issued
- * to enable OCD exit
- */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
- ram_address + (0x1 << ba_off));
-
- /* A nornal mode command is provided */
- atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
-
- /* Perform a write access to any DDR2-SDRAM address */
- writel(0, ram_address);
-
- /* Write the refresh rate */
- writel(mpddr_value->rtr, &mpddr->rtr);
-
- return 0;
-}
diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c
deleted file mode 100644
index 2cba716..0000000
--- a/arch/arm/cpu/at91-common/phy.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2012
- * Markus Hubig <mhubig@imko.de>
- * IMKO GmbH <www.imko.de>
- *
- * Copyright (C) 2013 DENX Software Engineering, hs@denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/sizes.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <watchdog.h>
-
-void at91_phy_reset(void)
-{
- unsigned long erstl;
- unsigned long start = get_timer(0);
- unsigned long const timeout = 1000; /* 1000ms */
- at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
-
- erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
- /*
- * Need to reset PHY -> 500ms reset
- * Reset PHY by pulling the NRST line for 500ms to low. To do so
- * disable user reset for low level on NRST pin and poll the NRST
- * level in reset status register.
- */
- writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
- AT91_RSTC_MR_URSTEN, &rstc->mr);
-
- writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
- /* Wait for end of hardware reset */
- while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
- /* avoid shutdown by watchdog */
- WATCHDOG_RESET();
- mdelay(10);
-
- /* timeout for not getting stuck in an endless loop */
- if (get_timer(start) >= timeout) {
- puts("*** ERROR: Timeout waiting for PHY reset!\n");
- break;
- }
- };
-
- /* Restore NRST value */
- writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
-}
diff --git a/arch/arm/cpu/at91-common/sdram.c b/arch/arm/cpu/at91-common/sdram.c
deleted file mode 100644
index 5758b06..0000000
--- a/arch/arm/cpu/at91-common/sdram.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * (C) Copyright 2014
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * Based on:
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91sam9_sdramc.h>
-#include <asm/arch/gpio.h>
-
-int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p)
-{
- struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC;
- unsigned int i;
-
- /* SDRAM feature must be in the configuration register */
- writel(p->cr, &reg->cr);
-
- /* The SDRAM memory type must be set in the Memory Device Register */
- writel(p->mdr, &reg->mdr);
-
- /*
- * The minimum pause of 200 us is provided to precede any single
- * toggle
- */
- for (i = 0; i < 1000; i++)
- ;
-
- /* A NOP command is issued to the SDRAM devices */
- writel(AT91_SDRAMC_MODE_NOP, &reg->mr);
- writel(0x00000000, sdram_address);
-
- /* An All Banks Precharge command is issued to the SDRAM devices */
- writel(AT91_SDRAMC_MODE_PRECHARGE, &reg->mr);
- writel(0x00000000, sdram_address);
-
- for (i = 0; i < 10000; i++)
- ;
-
- /* Eight auto-refresh cycles are provided */
- for (i = 0; i < 8; i++) {
- writel(AT91_SDRAMC_MODE_REFRESH, &reg->mr);
- writel(0x00000001 + i, sdram_address + 4 + 4 * i);
- }
-
- /*
- * A Mode Register set (MRS) cyscle is issued to program the
- * SDRAM parameters(TCSR, PASR, DS)
- */
- writel(AT91_SDRAMC_MODE_LMR, &reg->mr);
- writel(0xcafedede, sdram_address + 0x24);
-
- /*
- * The application must go into Normal Mode, setting Mode
- * to 0 in the Mode Register and perform a write access at
- * any location in the SDRAM.
- */
- writel(AT91_SDRAMC_MODE_NORMAL, &reg->mr);
- writel(0x00000000, sdram_address); /* Perform Normal mode */
-
- /*
- * Write the refresh rate into the count field in the SDRAMC
- * Refresh Timer Rgister.
- */
- writel(p->tr, &reg->tr);
-
- return 0;
-}
diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c
deleted file mode 100644
index aaa5eec..0000000
--- a/arch/arm/cpu/at91-common/spl.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (C) 2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_wdt.h>
-#include <asm/arch/clk.h>
-#include <spl.h>
-
-#if defined(CONFIG_AT91SAM9_WATCHDOG)
-void at91_disable_wdt(void) { }
-#else
-void at91_disable_wdt(void)
-{
- struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
-
- writel(AT91_WDT_MR_WDDIS, &wdt->mr);
-}
-#endif
-
-u32 spl_boot_device(void)
-{
-#ifdef CONFIG_SYS_USE_MMC
- return BOOT_DEVICE_MMC1;
-#elif CONFIG_SYS_USE_NANDFLASH
- return BOOT_DEVICE_NAND;
-#elif CONFIG_SYS_USE_SERIALFLASH
- return BOOT_DEVICE_SPI;
-#endif
- return BOOT_DEVICE_NONE;
-}
-
-u32 spl_boot_mode(void)
-{
- switch (spl_boot_device()) {
-#ifdef CONFIG_SYS_USE_MMC
- case BOOT_DEVICE_MMC1:
- return MMCSD_MODE_FS;
- break;
-#endif
- case BOOT_DEVICE_NONE:
- default:
- hang();
- }
-}
diff --git a/arch/arm/cpu/at91-common/spl_at91.c b/arch/arm/cpu/at91-common/spl_at91.c
deleted file mode 100644
index 89f588b..0000000
--- a/arch/arm/cpu/at91-common/spl_at91.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2014 DENX Software Engineering
- * Heiko Schocher <hs@denx.de>
- *
- * Based on:
- * Copyright (C) 2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91sam9_matrix.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_wdt.h>
-#include <asm/arch/clk.h>
-#include <spl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void enable_ext_reset(void)
-{
- struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-
- writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr);
-}
-
-void lowlevel_clock_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) {
- /* Enable Main Oscillator */
- writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor);
-
- /* Wait until Main Oscillator is stable */
- while (!(readl(&pmc->sr) & AT91_PMC_MOSCS))
- ;
- }
-
- /* After stabilization, switch to Main Oscillator */
- if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) {
- unsigned long tmp;
-
- tmp = readl(&pmc->mckr);
- tmp &= ~AT91_PMC_CSS;
- tmp |= AT91_PMC_CSS_MAIN;
- writel(tmp, &pmc->mckr);
- while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
- ;
-
- tmp &= ~AT91_PMC_PRES;
- tmp |= AT91_PMC_PRES_1;
- writel(tmp, &pmc->mckr);
- while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
- ;
- }
-
- return;
-}
-
-void __weak matrix_init(void)
-{
-}
-
-void __weak at91_spl_board_init(void)
-{
-}
-
-void spl_board_init(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- lowlevel_clock_init();
- at91_disable_wdt();
-
- /*
- * At this stage the main oscillator is supposed to be enabled
- * PCK = MCK = MOSC
- */
- writel(0x00, &pmc->pllicpr);
-
- /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
- at91_plla_init(CONFIG_SYS_AT91_PLLA);
-
- /* PCK = PLLA = 2 * MCK */
- at91_mck_init(CONFIG_SYS_MCKR);
-
- /* Switch MCK on PLLA output */
- at91_mck_init(CONFIG_SYS_MCKR_CSS);
-
-#if defined(CONFIG_SYS_AT91_PLLB)
- /* Configure PLLB */
- at91_pllb_init(CONFIG_SYS_AT91_PLLB);
-#endif
-
- /* Enable External Reset */
- enable_ext_reset();
-
- /* Initialize matrix */
- matrix_init();
-
- gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK;
- /*
- * init timer long enough for using in spl.
- */
- timer_init();
-
- /* enable clocks for all PIOs */
- at91_periph_clk_enable(ATMEL_ID_PIOA);
- at91_periph_clk_enable(ATMEL_ID_PIOB);
- at91_periph_clk_enable(ATMEL_ID_PIOC);
- /* init console */
- at91_seriald_hw_init();
- preloader_console_init();
-
- mem_init();
-
- at91_spl_board_init();
-}
diff --git a/arch/arm/cpu/at91-common/spl_atmel.c b/arch/arm/cpu/at91-common/spl_atmel.c
deleted file mode 100644
index 9cc1111..0000000
--- a/arch/arm/cpu/at91-common/spl_atmel.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (C) 2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_wdt.h>
-#include <asm/arch/clk.h>
-#include <spl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void switch_to_main_crystal_osc(void)
-{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- u32 tmp;
-
- tmp = readl(&pmc->mor);
- tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff);
- tmp &= ~AT91_PMC_MOR_KEY(0xff);
- tmp |= AT91_PMC_MOR_MOSCEN;
- tmp |= AT91_PMC_MOR_OSCOUNT(8);
- tmp |= AT91_PMC_MOR_KEY(0x37);
- writel(tmp, &pmc->mor);
- while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS))
- ;
-
- tmp = readl(&pmc->mor);
- tmp &= ~AT91_PMC_MOR_OSCBYPASS;
- tmp &= ~AT91_PMC_MOR_KEY(0xff);
- tmp |= AT91_PMC_MOR_KEY(0x37);
- writel(tmp, &pmc->mor);
-
- tmp = readl(&pmc->mor);
- tmp |= AT91_PMC_MOR_MOSCSEL;
- tmp &= ~AT91_PMC_MOR_KEY(0xff);
- tmp |= AT91_PMC_MOR_KEY(0x37);
- writel(tmp, &pmc->mor);
-
- while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS))
- ;
-
- /* Wait until MAINRDY field is set to make sure main clock is stable */
- while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY))
- ;
-
-#ifndef CONFIG_SAMA5D4
- tmp = readl(&pmc->mor);
- tmp &= ~AT91_PMC_MOR_MOSCRCEN;
- tmp &= ~AT91_PMC_MOR_KEY(0xff);
- tmp |= AT91_PMC_MOR_KEY(0x37);
- writel(tmp, &pmc->mor);
-#endif
-}
-
-__weak void matrix_init(void)
-{
- /* This only be used for sama5d4 soc now */
-}
-
-__weak void redirect_int_from_saic_to_aic(void)
-{
- /* This only be used for sama5d4 soc now */
-}
-
-void s_init(void)
-{
- switch_to_main_crystal_osc();
-
- /* disable watchdog */
- at91_disable_wdt();
-
- /* PMC configuration */
- at91_pmc_init();
-
- at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-
- matrix_init();
-
- redirect_int_from_saic_to_aic();
-
- timer_init();
-
- board_early_init_f();
-
- preloader_console_init();
-
- mem_init();
-}
diff --git a/arch/arm/cpu/at91-common/u-boot-spl.lds b/arch/arm/cpu/at91-common/u-boot-spl.lds
deleted file mode 100644
index eccca43..0000000
--- a/arch/arm/cpu/at91-common/u-boot-spl.lds
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * (C) 2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
- LENGTH = CONFIG_SPL_MAX_SIZE }
-MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
- LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- .text :
- {
- __start = .;
- *(.vectors)
- arch/arm/cpu/armv7/start.o (.text*)
- *(.text*)
- } >.sram
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
- . = ALIGN(4);
- __image_copy_end = .;
-
- .end :
- {
- *(.__end)
- } >.sram
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- } >.sdram
-}
diff --git a/arch/arm/cpu/tegra-common/Makefile b/arch/arm/cpu/tegra-common/Makefile
deleted file mode 100644
index a78869e..0000000
--- a/arch/arm/cpu/tegra-common/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ap.o
-obj-y += board.o
-obj-y += cache.o
-obj-y += clock.o
-obj-y += lowlevel_init.o
-obj-y += pinmux-common.o
-obj-y += powergate.o
-obj-y += xusb-padctl.o
-obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
-obj-$(CONFIG_TEGRA124) += vpr.o
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
deleted file mode 100644
index a17dfd1..0000000
--- a/arch/arm/cpu/tegra-common/ap.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-* (C) Copyright 2010-2014
-* NVIDIA Corporation <www.nvidia.com>
-*
- * SPDX-License-Identifier: GPL-2.0+
-*/
-
-/* Tegra AP (Application Processor) code */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch-tegra/ap.h>
-#include <asm/arch-tegra/clock.h>
-#include <asm/arch-tegra/fuse.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/scu.h>
-#include <asm/arch-tegra/tegra.h>
-#include <asm/arch-tegra/warmboot.h>
-
-int tegra_get_chip(void)
-{
- int rev;
- struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
-
- /*
- * This is undocumented, Chip ID is bits 15:8 of the register
- * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
- * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
- */
- rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
- debug("%s: CHIPID is 0x%02X\n", __func__, rev);
-
- return rev;
-}
-
-int tegra_get_sku_info(void)
-{
- int sku_id;
- struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
-
- sku_id = readl(&fuse->sku_info) & 0xff;
- debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
-
- return sku_id;
-}
-
-int tegra_get_chip_sku(void)
-{
- uint sku_id, chip_id;
-
- chip_id = tegra_get_chip();
- sku_id = tegra_get_sku_info();
-
- switch (chip_id) {
- case CHIPID_TEGRA20:
- switch (sku_id) {
- case SKU_ID_T20_7:
- case SKU_ID_T20:
- return TEGRA_SOC_T20;
- case SKU_ID_T25SE:
- case SKU_ID_AP25:
- case SKU_ID_T25:
- case SKU_ID_AP25E:
- case SKU_ID_T25E:
- return TEGRA_SOC_T25;
- }
- break;
- case CHIPID_TEGRA30:
- switch (sku_id) {
- case SKU_ID_T33:
- case SKU_ID_T30:
- case SKU_ID_TM30MQS_P_A3:
- default:
- return TEGRA_SOC_T30;
- }
- break;
- case CHIPID_TEGRA114:
- switch (sku_id) {
- case SKU_ID_T114_ENG:
- case SKU_ID_T114_1:
- default:
- return TEGRA_SOC_T114;
- }
- break;
- case CHIPID_TEGRA124:
- switch (sku_id) {
- case SKU_ID_T124_ENG:
- default:
- return TEGRA_SOC_T124;
- }
- break;
- }
-
- /* unknown chip/sku id */
- printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
- __func__, chip_id, sku_id);
- return TEGRA_SOC_UNKNOWN;
-}
-
-static void enable_scu(void)
-{
- struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
- u32 reg;
-
- /* Only enable the SCU on T20/T25 */
- if (tegra_get_chip() != CHIPID_TEGRA20)
- return;
-
- /* If SCU already setup/enabled, return */
- if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
- return;
-
- /* Invalidate all ways for all processors */
- writel(0xFFFF, &scu->scu_inv_all);
-
- /* Enable SCU - bit 0 */
- reg = readl(&scu->scu_ctrl);
- reg |= SCU_CTRL_ENABLE;
- writel(reg, &scu->scu_ctrl);
-}
-
-static u32 get_odmdata(void)
-{
- /*
- * ODMDATA is stored in the BCT in IRAM by the BootROM.
- * The BCT start and size are stored in the BIT in IRAM.
- * Read the data @ bct_start + (bct_size - 12). This works
- * on BCTs for currently supported SoCs, which are locked down.
- * If this changes in new chips, we can revisit this algorithm.
- */
-
- u32 bct_start, odmdata;
-
- bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
- odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
-
- return odmdata;
-}
-
-static void init_pmc_scratch(void)
-{
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 odmdata;
- int i;
-
- /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
- for (i = 0; i < 23; i++)
- writel(0, &pmc->pmc_scratch1+i);
-
- /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
- odmdata = get_odmdata();
- writel(odmdata, &pmc->pmc_scratch20);
-}
-
-void s_init(void)
-{
- /* Init PMC scratch memory */
- init_pmc_scratch();
-
- enable_scu();
-
- /* init the cache */
- config_cache();
-
- /* init vpr */
- config_vpr();
-}
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
deleted file mode 100644
index b6a84a5..0000000
--- a/arch/arm/cpu/tegra-common/board.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * (C) Copyright 2010-2014
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/mc.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/board.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/sys_proto.h>
-#include <asm/arch-tegra/warmboot.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-enum {
- /* UARTs which we can enable */
- UARTA = 1 << 0,
- UARTB = 1 << 1,
- UARTC = 1 << 2,
- UARTD = 1 << 3,
- UARTE = 1 << 4,
- UART_COUNT = 5,
-};
-
-/* Read the RAM size directly from the memory controller */
-unsigned int query_sdram_size(void)
-{
- struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
- u32 size_mb;
-
- size_mb = readl(&mc->mc_emem_cfg);
-#if defined(CONFIG_TEGRA20)
- debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb);
- size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024);
-#else
- debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
- size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024);
-#endif
-
-#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
- /* External memory limited to 2047 MB due to IROM/HI-VEC */
- if (size_mb == SZ_2G) size_mb -= SZ_1M;
-#endif
-
- return size_mb;
-}
-
-int dram_init(void)
-{
- /* We do not initialise DRAM here. We just query the size */
- gd->ram_size = query_sdram_size();
- return 0;
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- printf("Board: %s\n", sysinfo.board_string);
- return 0;
-}
-#endif /* CONFIG_DISPLAY_BOARDINFO */
-
-static int uart_configs[] = {
-#if defined(CONFIG_TEGRA20)
- #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
- FUNCMUX_UART1_UAA_UAB,
- #elif defined(CONFIG_TEGRA_UARTA_GPU)
- FUNCMUX_UART1_GPU,
- #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
- FUNCMUX_UART1_SDIO1,
- #else
- FUNCMUX_UART1_IRRX_IRTX,
-#endif
- FUNCMUX_UART2_UAD,
- -1,
- FUNCMUX_UART4_GMC,
- -1,
-#elif defined(CONFIG_TEGRA30)
- FUNCMUX_UART1_ULPI, /* UARTA */
- -1,
- -1,
- -1,
- -1,
-#elif defined(CONFIG_TEGRA114)
- -1,
- -1,
- -1,
- FUNCMUX_UART4_GMI, /* UARTD */
- -1,
-#else /* Tegra124 */
- FUNCMUX_UART1_KBC, /* UARTA */
- -1,
- -1,
- FUNCMUX_UART4_GPIO, /* UARTD */
- -1,
-#endif
-};
-
-/**
- * Set up the specified uarts
- *
- * @param uarts_ids Mask containing UARTs to init (UARTx)
- */
-static void setup_uarts(int uart_ids)
-{
- static enum periph_id id_for_uart[] = {
- PERIPH_ID_UART1,
- PERIPH_ID_UART2,
- PERIPH_ID_UART3,
- PERIPH_ID_UART4,
- PERIPH_ID_UART5,
- };
- size_t i;
-
- for (i = 0; i < UART_COUNT; i++) {
- if (uart_ids & (1 << i)) {
- enum periph_id id = id_for_uart[i];
-
- funcmux_select(id, uart_configs[i]);
- clock_ll_start_uart(id);
- }
- }
-}
-
-void board_init_uart_f(void)
-{
- int uart_ids = 0; /* bit mask of which UART ids to enable */
-
-#ifdef CONFIG_TEGRA_ENABLE_UARTA
- uart_ids |= UARTA;
-#endif
-#ifdef CONFIG_TEGRA_ENABLE_UARTB
- uart_ids |= UARTB;
-#endif
-#ifdef CONFIG_TEGRA_ENABLE_UARTC
- uart_ids |= UARTC;
-#endif
-#ifdef CONFIG_TEGRA_ENABLE_UARTD
- uart_ids |= UARTD;
-#endif
-#ifdef CONFIG_TEGRA_ENABLE_UARTE
- uart_ids |= UARTE;
-#endif
- setup_uarts(uart_ids);
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c
deleted file mode 100644
index 94f5bce..0000000
--- a/arch/arm/cpu/tegra-common/cache.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Tegra cache routines */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch-tegra/ap.h>
-#include <asm/arch/gp_padctrl.h>
-
-void config_cache(void)
-{
- u32 reg = 0;
-
- /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #0x41\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
-
- /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
- if (tegra_get_chip() < CHIPID_TEGRA114)
- return;
-
- /*
- * Systems with an architectural L2 cache must not use the PL310.
- * Config L2CTLR here for a data RAM latency of 3 cycles.
- */
- asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
- reg &= ~7;
- reg |= 2;
- asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
-}
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
deleted file mode 100644
index 11c7435..0000000
--- a/arch/arm/cpu/tegra-common/clock.c
+++ /dev/null
@@ -1,669 +0,0 @@
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Tegra SoC common clock control functions */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
-#include <div64.h>
-#include <fdtdec.h>
-
-/*
- * This is our record of the current clock rate of each clock. We don't
- * fill all of these in since we are only really interested in clocks which
- * we use as parents.
- */
-static unsigned pll_rate[CLOCK_ID_COUNT];
-
-/*
- * The oscillator frequency is fixed to one of four set values. Based on this
- * the other clocks are set up appropriately.
- */
-static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
- 13000000,
- 19200000,
- 12000000,
- 26000000,
-};
-
-/* return 1 if a peripheral ID is in range */
-#define clock_type_id_isvalid(id) ((id) >= 0 && \
- (id) < CLOCK_TYPE_COUNT)
-
-char pllp_valid = 1; /* PLLP is set up correctly */
-
-/* return 1 if a periphc_internal_id is in range */
-#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
- (id) < PERIPHC_COUNT)
-
-/* number of clock outputs of a PLL */
-static const u8 pll_num_clkouts[] = {
- 1, /* PLLC */
- 1, /* PLLM */
- 4, /* PLLP */
- 1, /* PLLA */
- 0, /* PLLU */
- 0, /* PLLD */
-};
-
-int clock_get_osc_bypass(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- reg = readl(&clkrst->crc_osc_ctrl);
- return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
-}
-
-/* Returns a pointer to the registers of the given pll */
-static struct clk_pll *get_pll(enum clock_id clkid)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-
- assert(clock_id_is_pll(clkid));
- return &clkrst->crc_pll[clkid];
-}
-
-int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
- u32 *divp, u32 *cpcon, u32 *lfcon)
-{
- struct clk_pll *pll = get_pll(clkid);
- u32 data;
-
- assert(clkid != CLOCK_ID_USB);
-
- /* Safety check, adds to code size but is small */
- if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
- return -1;
- data = readl(&pll->pll_base);
- *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
- *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
- *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
- data = readl(&pll->pll_misc);
- *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
- *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
-
- return 0;
-}
-
-unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
- u32 divp, u32 cpcon, u32 lfcon)
-{
- struct clk_pll *pll = get_pll(clkid);
- u32 data;
-
- /*
- * We cheat by treating all PLL (except PLLU) in the same fashion.
- * This works only because:
- * - same fields are always mapped at same offsets, except DCCON
- * - DCCON is always 0, doesn't conflict
- * - M,N, P of PLLP values are ignored for PLLP
- */
- data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
- writel(data, &pll->pll_misc);
-
- data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
- (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
-
- if (clkid == CLOCK_ID_USB)
- data |= divp << PLLU_VCO_FREQ_SHIFT;
- else
- data |= divp << PLL_DIVP_SHIFT;
- writel(data, &pll->pll_base);
-
- /* calculate the stable time */
- return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
-}
-
-void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
- unsigned divisor)
-{
- u32 *reg = get_periph_source_reg(periph_id);
- u32 value;
-
- value = readl(reg);
-
- value &= ~OUT_CLK_SOURCE_31_30_MASK;
- value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
-
- value &= ~OUT_CLK_DIVISOR_MASK;
- value |= divisor << OUT_CLK_DIVISOR_SHIFT;
-
- writel(value, reg);
-}
-
-void clock_ll_set_source(enum periph_id periph_id, unsigned source)
-{
- u32 *reg = get_periph_source_reg(periph_id);
-
- clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
- source << OUT_CLK_SOURCE_31_30_SHIFT);
-}
-
-/**
- * Given the parent's rate and the required rate for the children, this works
- * out the peripheral clock divider to use, in 7.1 binary format.
- *
- * @param divider_bits number of divider bits (8 or 16)
- * @param parent_rate clock rate of parent clock in Hz
- * @param rate required clock rate for this clock
- * @return divider which should be used
- */
-static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
- unsigned long rate)
-{
- u64 divider = parent_rate * 2;
- unsigned max_divider = 1 << divider_bits;
-
- divider += rate - 1;
- do_div(divider, rate);
-
- if ((s64)divider - 2 < 0)
- return 0;
-
- if ((s64)divider - 2 >= max_divider)
- return -1;
-
- return divider - 2;
-}
-
-int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
-{
- struct clk_pll *pll = get_pll(clkid);
- int data = 0, div = 0, offset = 0;
-
- if (!clock_id_is_pll(clkid))
- return -1;
-
- if (pllout + 1 > pll_num_clkouts[clkid])
- return -1;
-
- div = clk_get_divider(8, pll_rate[clkid], rate);
-
- if (div < 0)
- return -1;
-
- /* out2 and out4 are in the high part of the register */
- if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
- offset = 16;
-
- data = (div << PLL_OUT_RATIO_SHIFT) |
- PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
- clrsetbits_le32(&pll->pll_out[pllout >> 1],
- PLL_OUT_RATIO_MASK << offset, data << offset);
-
- return 0;
-}
-
-/**
- * Given the parent's rate and the divider in 7.1 format, this works out the
- * resulting peripheral clock rate.
- *
- * @param parent_rate clock rate of parent clock in Hz
- * @param divider which should be used in 7.1 format
- * @return effective clock rate of peripheral
- */
-static unsigned long get_rate_from_divider(unsigned long parent_rate,
- int divider)
-{
- u64 rate;
-
- rate = (u64)parent_rate * 2;
- do_div(rate, divider + 2);
- return rate;
-}
-
-unsigned long clock_get_periph_rate(enum periph_id periph_id,
- enum clock_id parent)
-{
- u32 *reg = get_periph_source_reg(periph_id);
-
- return get_rate_from_divider(pll_rate[parent],
- (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
-}
-
-/**
- * Find the best available 7.1 format divisor given a parent clock rate and
- * required child clock rate. This function assumes that a second-stage
- * divisor is available which can divide by powers of 2 from 1 to 256.
- *
- * @param divider_bits number of divider bits (8 or 16)
- * @param parent_rate clock rate of parent clock in Hz
- * @param rate required clock rate for this clock
- * @param extra_div value for the second-stage divisor (not set if this
- * function returns -1.
- * @return divider which should be used, or -1 if nothing is valid
- *
- */
-static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
- unsigned long rate, int *extra_div)
-{
- int shift;
- int best_divider = -1;
- int best_error = rate;
-
- /* try dividers from 1 to 256 and find closest match */
- for (shift = 0; shift <= 8 && best_error > 0; shift++) {
- unsigned divided_parent = parent_rate >> shift;
- int divider = clk_get_divider(divider_bits, divided_parent,
- rate);
- unsigned effective_rate = get_rate_from_divider(divided_parent,
- divider);
- int error = rate - effective_rate;
-
- /* Given a valid divider, look for the lowest error */
- if (divider != -1 && error < best_error) {
- best_error = error;
- *extra_div = 1 << shift;
- best_divider = divider;
- }
- }
-
- /* return what we found - *extra_div will already be set */
- return best_divider;
-}
-
-/**
- * Adjust peripheral PLL to use the given divider and source.
- *
- * @param periph_id peripheral to adjust
- * @param source Source number (0-3 or 0-7)
- * @param mux_bits Number of mux bits (2 or 4)
- * @param divider Required divider in 7.1 or 15.1 format
- * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
- * for this peripheral)
- */
-static int adjust_periph_pll(enum periph_id periph_id, int source,
- int mux_bits, unsigned divider)
-{
- u32 *reg = get_periph_source_reg(periph_id);
-
- clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
- divider << OUT_CLK_DIVISOR_SHIFT);
- udelay(1);
-
- /* work out the source clock and set it */
- if (source < 0)
- return -1;
-
- switch (mux_bits) {
- case MASK_BITS_31_30:
- clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
- source << OUT_CLK_SOURCE_31_30_SHIFT);
- break;
-
- case MASK_BITS_31_29:
- clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
- source << OUT_CLK_SOURCE_31_29_SHIFT);
- break;
-
- case MASK_BITS_31_28:
- clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
- source << OUT_CLK_SOURCE_31_28_SHIFT);
- break;
-
- default:
- return -1;
- }
-
- udelay(2);
- return 0;
-}
-
-unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
- enum clock_id parent, unsigned rate, int *extra_div)
-{
- unsigned effective_rate;
- int mux_bits, divider_bits, source;
- int divider;
- int xdiv = 0;
-
- /* work out the source clock and set it */
- source = get_periph_clock_source(periph_id, parent, &mux_bits,
- &divider_bits);
-
- divider = find_best_divider(divider_bits, pll_rate[parent],
- rate, &xdiv);
- if (extra_div)
- *extra_div = xdiv;
-
- assert(divider >= 0);
- if (adjust_periph_pll(periph_id, source, mux_bits, divider))
- return -1U;
- debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
- get_periph_source_reg(periph_id),
- readl(get_periph_source_reg(periph_id)));
-
- /* Check what we ended up with. This shouldn't matter though */
- effective_rate = clock_get_periph_rate(periph_id, parent);
- if (extra_div)
- effective_rate /= *extra_div;
- if (rate != effective_rate)
- debug("Requested clock rate %u not honored (got %u)\n",
- rate, effective_rate);
- return effective_rate;
-}
-
-unsigned clock_start_periph_pll(enum periph_id periph_id,
- enum clock_id parent, unsigned rate)
-{
- unsigned effective_rate;
-
- reset_set_enable(periph_id, 1);
- clock_enable(periph_id);
-
- effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
- NULL);
-
- reset_set_enable(periph_id, 0);
- return effective_rate;
-}
-
-void clock_enable(enum periph_id clkid)
-{
- clock_set_enable(clkid, 1);
-}
-
-void clock_disable(enum periph_id clkid)
-{
- clock_set_enable(clkid, 0);
-}
-
-void reset_periph(enum periph_id periph_id, int us_delay)
-{
- /* Put peripheral into reset */
- reset_set_enable(periph_id, 1);
- udelay(us_delay);
-
- /* Remove reset */
- reset_set_enable(periph_id, 0);
-
- udelay(us_delay);
-}
-
-void reset_cmplx_set_enable(int cpu, int which, int reset)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 mask;
-
- /* Form the mask, which depends on the cpu chosen (2 or 4) */
- assert(cpu >= 0 && cpu < MAX_NUM_CPU);
- mask = which << cpu;
-
- /* either enable or disable those reset for that CPU */
- if (reset)
- writel(mask, &clkrst->crc_cpu_cmplx_set);
- else
- writel(mask, &clkrst->crc_cpu_cmplx_clr);
-}
-
-unsigned clock_get_rate(enum clock_id clkid)
-{
- struct clk_pll *pll;
- u32 base;
- u32 divm;
- u64 parent_rate;
- u64 rate;
-
- parent_rate = osc_freq[clock_get_osc_freq()];
- if (clkid == CLOCK_ID_OSC)
- return parent_rate;
-
- pll = get_pll(clkid);
- base = readl(&pll->pll_base);
-
- /* Oh for bf_unpack()... */
- rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
- divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
- if (clkid == CLOCK_ID_USB)
- divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
- else
- divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
- do_div(rate, divm);
- return rate;
-}
-
-/**
- * Set the output frequency you want for each PLL clock.
- * PLL output frequencies are programmed by setting their N, M and P values.
- * The governing equations are:
- * VCO = (Fi / m) * n, Fo = VCO / (2^p)
- * where Fo is the output frequency from the PLL.
- * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
- * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
- * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
- *
- * @param n PLL feedback divider(DIVN)
- * @param m PLL input divider(DIVN)
- * @param p post divider(DIVP)
- * @param cpcon base PLL charge pump(CPCON)
- * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
- * be overriden), 1 if PLL is already correct
- */
-int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
-{
- u32 base_reg;
- u32 misc_reg;
- struct clk_pll *pll;
-
- pll = get_pll(clkid);
-
- base_reg = readl(&pll->pll_base);
-
- /* Set BYPASS, m, n and p to PLL_BASE */
- base_reg &= ~PLL_DIVM_MASK;
- base_reg |= m << PLL_DIVM_SHIFT;
-
- base_reg &= ~PLL_DIVN_MASK;
- base_reg |= n << PLL_DIVN_SHIFT;
-
- base_reg &= ~PLL_DIVP_MASK;
- base_reg |= p << PLL_DIVP_SHIFT;
-
- if (clkid == CLOCK_ID_PERIPH) {
- /*
- * If the PLL is already set up, check that it is correct
- * and record this info for clock_verify() to check.
- */
- if (base_reg & PLL_BASE_OVRRIDE_MASK) {
- base_reg |= PLL_ENABLE_MASK;
- if (base_reg != readl(&pll->pll_base))
- pllp_valid = 0;
- return pllp_valid ? 1 : -1;
- }
- base_reg |= PLL_BASE_OVRRIDE_MASK;
- }
-
- base_reg |= PLL_BYPASS_MASK;
- writel(base_reg, &pll->pll_base);
-
- /* Set cpcon to PLL_MISC */
- misc_reg = readl(&pll->pll_misc);
- misc_reg &= ~PLL_CPCON_MASK;
- misc_reg |= cpcon << PLL_CPCON_SHIFT;
- writel(misc_reg, &pll->pll_misc);
-
- /* Enable PLL */
- base_reg |= PLL_ENABLE_MASK;
- writel(base_reg, &pll->pll_base);
-
- /* Disable BYPASS */
- base_reg &= ~PLL_BYPASS_MASK;
- writel(base_reg, &pll->pll_base);
-
- return 0;
-}
-
-void clock_ll_start_uart(enum periph_id periph_id)
-{
- /* Assert UART reset and enable clock */
- reset_set_enable(periph_id, 1);
- clock_enable(periph_id);
- clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
-
- /* wait for 2us */
- udelay(2);
-
- /* De-assert reset to UART */
- reset_set_enable(periph_id, 0);
-}
-
-#ifdef CONFIG_OF_CONTROL
-int clock_decode_periph_id(const void *blob, int node)
-{
- enum periph_id id;
- u32 cell[2];
- int err;
-
- err = fdtdec_get_int_array(blob, node, "clocks", cell,
- ARRAY_SIZE(cell));
- if (err)
- return -1;
- id = clk_id_to_periph_id(cell[1]);
- assert(clock_periph_id_isvalid(id));
- return id;
-}
-#endif /* CONFIG_OF_CONTROL */
-
-int clock_verify(void)
-{
- struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
- u32 reg = readl(&pll->pll_base);
-
- if (!pllp_valid) {
- printf("Warning: PLLP %x is not correct\n", reg);
- return -1;
- }
- debug("PLLP %x is correct\n", reg);
- return 0;
-}
-
-void clock_init(void)
-{
- pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
- pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
- pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
- pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
- pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
- pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
- debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
- debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
- debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
- debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
- debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
-
- /* Do any special system timer/TSC setup */
- arch_timer_init();
-}
-
-static void set_avp_clock_source(u32 src)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 val;
-
- val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
- (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
- (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
- (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
- (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
- writel(val, &clkrst->crc_sclk_brst_pol);
- udelay(3);
-}
-
-/*
- * This function is useful on Tegra30, and any later SoCs that have compatible
- * PLLP configuration registers.
- */
-void tegra30_set_up_pllp(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- /*
- * Based on the Tegra TRM, the system clock (which is the AVP clock) can
- * run up to 275MHz. On power on, the default sytem clock source is set
- * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
- * 408MHz which is beyond system clock's upper limit.
- *
- * The fix is to set the system clock to CLK_M before initializing PLLP,
- * and then switch back to PLLP_OUT4, which has an appropriate divider
- * configured, after PLLP has been configured
- */
- set_avp_clock_source(SCLK_SOURCE_CLKM);
-
- /*
- * PLLP output frequency set to 408Mhz
- * PLLC output frequency set to 228Mhz
- */
- switch (clock_get_osc_freq()) {
- case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
- break;
-
- case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
- break;
-
- case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
- break;
- case CLOCK_OSC_FREQ_19_2:
- default:
- /*
- * These are not supported. It is too early to print a
- * message and the UART likely won't work anyway due to the
- * oscillator being wrong.
- */
- break;
- }
-
- /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
-
- /* OUT1, 2 */
- /* Assert RSTN before enable */
- reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
- writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
- /* Set divisor and reenable */
- reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
- | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
- | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
- | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
- writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
-
- /* OUT3, 4 */
- /* Assert RSTN before enable */
- reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
- writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
- /* Set divisor and reenable */
- reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
- | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
- | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
- | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
- writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
-
- set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
-}
diff --git a/arch/arm/cpu/tegra-common/lowlevel_init.S b/arch/arm/cpu/tegra-common/lowlevel_init.S
deleted file mode 100644
index a211bb3..0000000
--- a/arch/arm/cpu/tegra-common/lowlevel_init.S
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * SoC-specific setup info
- *
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-#include <linux/linkage.h>
-
- .align 5
-ENTRY(reset_cpu)
- ldr r1, rstctl @ get addr for global reset
- @ reg
- ldr r3, [r1]
- orr r3, r3, #0x10
- str r3, [r1] @ force reset
- mov r0, r0
-_loop_forever:
- b _loop_forever
-rstctl:
- .word PRM_RSTCTRL
-ENDPROC(reset_cpu)
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
deleted file mode 100644
index 6e3ab0c..0000000
--- a/arch/arm/cpu/tegra-common/pinmux-common.c
+++ /dev/null
@@ -1,527 +0,0 @@
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
-
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) \
- (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
-
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) \
- (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
-
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) \
- (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
-
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) \
- (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
-
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) \
- (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) \
- (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
-
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-#ifdef TEGRA_PMX_HAS_RCV_SEL
-/* return 1 if a pin_rcv_sel_is in range */
-#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
- (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
- ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
-
-#define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
-
-#if defined(CONFIG_TEGRA20)
-
-#define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
-#define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
-
-#define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
-#define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
-
-#define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
-#define TRI_SHIFT(grp) ((grp) % 32)
-
-#else
-
-#define REG(pin) _R(0x3000 + ((pin) * 4))
-
-#define MUX_REG(pin) REG(pin)
-#define MUX_SHIFT(pin) 0
-
-#define PULL_REG(pin) REG(pin)
-#define PULL_SHIFT(pin) 2
-
-#define TRI_REG(pin) REG(pin)
-#define TRI_SHIFT(pin) 4
-
-#endif /* CONFIG_TEGRA20 */
-
-#define DRV_REG(group) _R(0x868 + ((group) * 4))
-
-#define IO_SHIFT 5
-#define OD_SHIFT 6
-#define LOCK_SHIFT 7
-#define IO_RESET_SHIFT 8
-#define RCV_SEL_SHIFT 9
-
-#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
-/* This register/field only exists on Tegra114 and later */
-#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
-#define CLAMP_INPUTS_WHEN_TRISTATED 1
-
-void pinmux_set_tristate_input_clamping(void)
-{
- u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
- u32 val;
-
- val = readl(reg);
- val |= CLAMP_INPUTS_WHEN_TRISTATED;
- writel(val, reg);
-}
-#endif
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
- u32 *reg = MUX_REG(pin);
- int i, mux = -1;
- u32 val;
-
- if (func == PMUX_FUNC_DEFAULT)
- return;
-
- /* Error check on pin and func */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_func_isvalid(func));
-
- if (func >= PMUX_FUNC_RSVD1) {
- mux = (func - PMUX_FUNC_RSVD1) & 3;
- } else {
- /* Search for the appropriate function */
- for (i = 0; i < 4; i++) {
- if (tegra_soc_pingroups[pin].funcs[i] == func) {
- mux = i;
- break;
- }
- }
- }
- assert(mux != -1);
-
- val = readl(reg);
- val &= ~(3 << MUX_SHIFT(pin));
- val |= (mux << MUX_SHIFT(pin));
- writel(val, reg);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
- u32 *reg = PULL_REG(pin);
- u32 val;
-
- /* Error check on pin and pupd */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_pupd_isvalid(pupd));
-
- val = readl(reg);
- val &= ~(3 << PULL_SHIFT(pin));
- val |= (pupd << PULL_SHIFT(pin));
- writel(val, reg);
-}
-
-static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
-{
- u32 *reg = TRI_REG(pin);
- u32 val;
-
- /* Error check on pin */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_tristate_isvalid(tri));
-
- val = readl(reg);
- if (tri == PMUX_TRI_TRISTATE)
- val |= (1 << TRI_SHIFT(pin));
- else
- val &= ~(1 << TRI_SHIFT(pin));
- writel(val, reg);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
- pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
-}
-
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
- u32 *reg = REG(pin);
- u32 val;
-
- if (io == PMUX_PIN_NONE)
- return;
-
- /* Error check on pin and io */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_io_isvalid(io));
-
- val = readl(reg);
- if (io == PMUX_PIN_INPUT)
- val |= (io & 1) << IO_SHIFT;
- else
- val &= ~(1 << IO_SHIFT);
- writel(val, reg);
-}
-
-static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
- u32 *reg = REG(pin);
- u32 val;
-
- if (lock == PMUX_PIN_LOCK_DEFAULT)
- return;
-
- /* Error check on pin and lock */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_lock_isvalid(lock));
-
- val = readl(reg);
- if (lock == PMUX_PIN_LOCK_ENABLE) {
- val |= (1 << LOCK_SHIFT);
- } else {
- if (val & (1 << LOCK_SHIFT))
- printf("%s: Cannot clear LOCK bit!\n", __func__);
- val &= ~(1 << LOCK_SHIFT);
- }
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
- u32 *reg = REG(pin);
- u32 val;
-
- if (od == PMUX_PIN_OD_DEFAULT)
- return;
-
- /* Error check on pin and od */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_od_isvalid(od));
-
- val = readl(reg);
- if (od == PMUX_PIN_OD_ENABLE)
- val |= (1 << OD_SHIFT);
- else
- val &= ~(1 << OD_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_set_ioreset(enum pmux_pingrp pin,
- enum pmux_pin_ioreset ioreset)
-{
- u32 *reg = REG(pin);
- u32 val;
-
- if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
- return;
-
- /* Error check on pin and ioreset */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_ioreset_isvalid(ioreset));
-
- val = readl(reg);
- if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
- val |= (1 << IO_RESET_SHIFT);
- else
- val &= ~(1 << IO_RESET_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-#ifdef TEGRA_PMX_HAS_RCV_SEL
-static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
- enum pmux_pin_rcv_sel rcv_sel)
-{
- u32 *reg = REG(pin);
- u32 val;
-
- if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
- return;
-
- /* Error check on pin and rcv_sel */
- assert(pmux_pingrp_isvalid(pin));
- assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
-
- val = readl(reg);
- if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
- val |= (1 << RCV_SEL_SHIFT);
- else
- val &= ~(1 << RCV_SEL_SHIFT);
- writel(val, reg);
-
- return;
-}
-#endif /* TEGRA_PMX_HAS_RCV_SEL */
-#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
-
-static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
-{
- enum pmux_pingrp pin = config->pingrp;
-
- pinmux_set_func(pin, config->func);
- pinmux_set_pullupdown(pin, config->pull);
- pinmux_set_tristate(pin, config->tristate);
-#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
- pinmux_set_io(pin, config->io);
- pinmux_set_lock(pin, config->lock);
- pinmux_set_od(pin, config->od);
- pinmux_set_ioreset(pin, config->ioreset);
-#ifdef TEGRA_PMX_HAS_RCV_SEL
- pinmux_set_rcv_sel(pin, config->rcv_sel);
-#endif
-#endif
-}
-
-void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
- int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_pingrp(&config[i]);
-}
-
-#ifdef TEGRA_PMX_HAS_DRVGRPS
-
-#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
-
-#define pmux_slw_isvalid(slw) \
- (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
-
-#define pmux_drv_isvalid(drv) \
- (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
-
-#define pmux_lpmd_isvalid(lpm) \
- (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
-
-#define pmux_schmt_isvalid(schmt) \
- (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
-
-#define pmux_hsm_isvalid(hsm) \
- (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
-
-#define HSM_SHIFT 2
-#define SCHMT_SHIFT 3
-#define LPMD_SHIFT 4
-#define LPMD_MASK (3 << LPMD_SHIFT)
-#define DRVDN_SHIFT 12
-#define DRVDN_MASK (0x7F << DRVDN_SHIFT)
-#define DRVUP_SHIFT 20
-#define DRVUP_MASK (0x7F << DRVUP_SHIFT)
-#define SLWR_SHIFT 28
-#define SLWR_MASK (3 << SLWR_SHIFT)
-#define SLWF_SHIFT 30
-#define SLWF_MASK (3 << SLWF_SHIFT)
-
-static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwf == PMUX_SLWF_NONE)
- return;
-
- /* Error check on pad and slwf */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_slw_isvalid(slwf));
-
- val = readl(reg);
- val &= ~SLWF_MASK;
- val |= (slwf << SLWF_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (slwr == PMUX_SLWR_NONE)
- return;
-
- /* Error check on pad and slwr */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_slw_isvalid(slwr));
-
- val = readl(reg);
- val &= ~SLWR_MASK;
- val |= (slwr << SLWR_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvup == PMUX_DRVUP_NONE)
- return;
-
- /* Error check on pad and drvup */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_drv_isvalid(drvup));
-
- val = readl(reg);
- val &= ~DRVUP_MASK;
- val |= (drvup << DRVUP_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (drvdn == PMUX_DRVDN_NONE)
- return;
-
- /* Error check on pad and drvdn */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_drv_isvalid(drvdn));
-
- val = readl(reg);
- val &= ~DRVDN_MASK;
- val |= (drvdn << DRVDN_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (lpmd == PMUX_LPMD_NONE)
- return;
-
- /* Error check pad and lpmd value */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_lpmd_isvalid(lpmd));
-
- val = readl(reg);
- val &= ~LPMD_MASK;
- val |= (lpmd << LPMD_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (schmt == PMUX_SCHMT_NONE)
- return;
-
- /* Error check pad */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_schmt_isvalid(schmt));
-
- val = readl(reg);
- if (schmt == PMUX_SCHMT_ENABLE)
- val |= (1 << SCHMT_SHIFT);
- else
- val &= ~(1 << SCHMT_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
-{
- u32 *reg = DRV_REG(grp);
- u32 val;
-
- /* NONE means unspecified/do not change/use POR value */
- if (hsm == PMUX_HSM_NONE)
- return;
-
- /* Error check pad */
- assert(pmux_drvgrp_isvalid(grp));
- assert(pmux_hsm_isvalid(hsm));
-
- val = readl(reg);
- if (hsm == PMUX_HSM_ENABLE)
- val |= (1 << HSM_SHIFT);
- else
- val &= ~(1 << HSM_SHIFT);
- writel(val, reg);
-
- return;
-}
-
-static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
-{
- enum pmux_drvgrp grp = config->drvgrp;
-
- pinmux_set_drvup_slwf(grp, config->slwf);
- pinmux_set_drvdn_slwr(grp, config->slwr);
- pinmux_set_drvup(grp, config->drvup);
- pinmux_set_drvdn(grp, config->drvdn);
- pinmux_set_lpmd(grp, config->lpmd);
- pinmux_set_schmt(grp, config->schmt);
- pinmux_set_hsm(grp, config->hsm);
-}
-
-void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
- int len)
-{
- int i;
-
- for (i = 0; i < len; i++)
- pinmux_config_drvgrp(&config[i]);
-}
-#endif /* TEGRA_PMX_HAS_DRVGRPS */
diff --git a/arch/arm/cpu/tegra-common/powergate.c b/arch/arm/cpu/tegra-common/powergate.c
deleted file mode 100644
index 439cff3..0000000
--- a/arch/arm/cpu/tegra-common/powergate.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <errno.h>
-
-#include <asm/io.h>
-#include <asm/types.h>
-
-#include <asm/arch/powergate.h>
-#include <asm/arch/tegra.h>
-
-#define PWRGATE_TOGGLE 0x30
-#define PWRGATE_TOGGLE_START (1 << 8)
-
-#define REMOVE_CLAMPING 0x34
-
-#define PWRGATE_STATUS 0x38
-
-static int tegra_powergate_set(enum tegra_powergate id, bool state)
-{
- u32 value, mask = state ? (1 << id) : 0, old_mask;
- unsigned long start, timeout = 25;
-
- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
- old_mask = value & (1 << id);
-
- if (mask == old_mask)
- return 0;
-
- writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
-
- start = get_timer(0);
-
- while (get_timer(start) < timeout) {
- value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
- if ((value & (1 << id)) == mask)
- return 0;
- }
-
- return -ETIMEDOUT;
-}
-
-static int tegra_powergate_power_on(enum tegra_powergate id)
-{
- return tegra_powergate_set(id, true);
-}
-
-int tegra_powergate_power_off(enum tegra_powergate id)
-{
- return tegra_powergate_set(id, false);
-}
-
-static int tegra_powergate_remove_clamping(enum tegra_powergate id)
-{
- unsigned long value;
-
- /*
- * The REMOVE_CLAMPING register has the bits for the PCIE and VDEC
- * partitions reversed. This was originally introduced on Tegra20 but
- * has since been carried forward for backwards-compatibility.
- */
- if (id == TEGRA_POWERGATE_VDEC)
- value = 1 << TEGRA_POWERGATE_PCIE;
- else if (id == TEGRA_POWERGATE_PCIE)
- value = 1 << TEGRA_POWERGATE_VDEC;
- else
- value = 1 << id;
-
- writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
-
- return 0;
-}
-
-int tegra_powergate_sequence_power_up(enum tegra_powergate id,
- enum periph_id periph)
-{
- int err;
-
- reset_set_enable(periph, 1);
-
- err = tegra_powergate_power_on(id);
- if (err < 0)
- return err;
-
- clock_enable(periph);
-
- udelay(10);
-
- err = tegra_powergate_remove_clamping(id);
- if (err < 0)
- return err;
-
- udelay(10);
-
- reset_set_enable(periph, 0);
-
- return 0;
-}
diff --git a/arch/arm/cpu/tegra-common/sys_info.c b/arch/arm/cpu/tegra-common/sys_info.c
deleted file mode 100644
index 5933c35..0000000
--- a/arch/arm/cpu/tegra-common/sys_info.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/ctype.h>
-
-static void upstring(char *s)
-{
- while (*s) {
- *s = toupper(*s);
- s++;
- }
-}
-
-/* Print CPU information */
-int print_cpuinfo(void)
-{
- char soc_name[10];
-
- strncpy(soc_name, CONFIG_SYS_SOC, 10);
- upstring(soc_name);
- puts(soc_name);
- puts("\n");
-
- /* TBD: Add printf of major/minor rev info, stepping, etc. */
- return 0;
-}
diff --git a/arch/arm/cpu/tegra-common/vpr.c b/arch/arm/cpu/tegra-common/vpr.c
deleted file mode 100644
index f695811..0000000
--- a/arch/arm/cpu/tegra-common/vpr.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Tegra vpr routines */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch/mc.h>
-
-/* Configures VPR. Right now, all we do is turn it off. */
-void config_vpr(void)
-{
- struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
-
- /* Turn VPR off */
- writel(0, &mc->mc_video_protect_size_mb);
- writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
- &mc->mc_video_protect_reg_ctrl);
- /* read back to ensure the write went through */
- readl(&mc->mc_video_protect_reg_ctrl);
-}
diff --git a/arch/arm/cpu/tegra-common/xusb-padctl.c b/arch/arm/cpu/tegra-common/xusb-padctl.c
deleted file mode 100644
index 65f8d2e..0000000
--- a/arch/arm/cpu/tegra-common/xusb-padctl.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <errno.h>
-
-#include <asm/arch-tegra/xusb-padctl.h>
-
-struct tegra_xusb_phy * __weak tegra_xusb_phy_get(unsigned int type)
-{
- return NULL;
-}
-
-int __weak tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
-{
- return -ENOSYS;
-}
-
-int __weak tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
-{
- return -ENOSYS;
-}
-
-int __weak tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
-{
- return -ENOSYS;
-}
-
-int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
-{
- return -ENOSYS;
-}
-
-void __weak tegra_xusb_padctl_init(const void *fdt)
-{
-}
diff --git a/arch/arm/cpu/tegra114-common/Makefile b/arch/arm/cpu/tegra114-common/Makefile
deleted file mode 100644
index d959b57..0000000
--- a/arch/arm/cpu/tegra114-common/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-obj-y += clock.o funcmux.o pinmux.o
diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c
deleted file mode 100644
index d5194e1..0000000
--- a/arch/arm/cpu/tegra114-common/clock.c
+++ /dev/null
@@ -1,669 +0,0 @@
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Tegra114 Clock control functions */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sysctr.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
-#include <div64.h>
-#include <fdtdec.h>
-
-/*
- * Clock types that we can use as a source. The Tegra114 has muxes for the
- * peripheral clocks, and in most cases there are four options for the clock
- * source. This gives us a clock 'type' and exploits what commonality exists
- * in the device.
- *
- * Letters are obvious, except for T which means CLK_M, and S which means the
- * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
- * datasheet) and PLL_M are different things. The former is the basic
- * clock supplied to the SOC from an external oscillator. The latter is the
- * memory clock PLL.
- *
- * See definitions in clock_id in the header file.
- */
-enum clock_type_id {
- CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
- CLOCK_TYPE_MCPA, /* and so on */
- CLOCK_TYPE_MCPT,
- CLOCK_TYPE_PCM,
- CLOCK_TYPE_PCMT,
- CLOCK_TYPE_PCMT16,
- CLOCK_TYPE_PDCT,
- CLOCK_TYPE_ACPT,
- CLOCK_TYPE_ASPTE,
- CLOCK_TYPE_PMDACD2T,
- CLOCK_TYPE_PCST,
-
- CLOCK_TYPE_COUNT,
- CLOCK_TYPE_NONE = -1, /* invalid clock type */
-};
-
-enum {
- CLOCK_MAX_MUX = 8 /* number of source options for each clock */
-};
-
-/*
- * Clock source mux for each clock type. This just converts our enum into
- * a list of mux sources for use by the code.
- *
- * Note:
- * The extra column in each clock source array is used to store the mask
- * bits in its register for the source.
- */
-#define CLK(x) CLOCK_ID_ ## x
-static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
- { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
- CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_29},
- { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
- CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
- MASK_BITS_31_29},
- { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_28}
-};
-
-/*
- * Clock type for each peripheral clock source. We put the name in each
- * record just so it is easy to match things up
- */
-#define TYPE(name, type) type
-static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
- /* 0x00 */
- TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
- TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
-
- /* 0x08 */
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
- TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
-
- /* 0x10 */
- TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
-
- /* 0x18 */
- TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
- TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
-
- /* 0x20 */
- TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
-
- /* 0x28 */
- TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
-
- /* 0x30 */
- TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
-
- /* 0x38h */ /* Jumps to reg offset 0x3B0h */
- TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
- TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
-
- /* 0x40 */
- TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
- TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
- TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
- TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
- TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
-
- /* 0x48 */
- TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
- TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
- TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
- TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
-
- /* 0x50 */
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
- TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
-};
-
-/*
- * This array translates a periph_id to a periphc_internal_id
- *
- * Not present/matched up:
- * uint vi_sensor; _VI_SENSOR_0, 0x1A8
- * SPDIF - which is both 0x08 and 0x0c
- *
- */
-#define NONE(name) (-1)
-#define OFFSET(name, value) PERIPHC_ ## name
-static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
- /* Low word: 31:0 */
- NONE(CPU),
- NONE(COP),
- NONE(TRIGSYS),
- NONE(RESERVED3),
- NONE(RTC),
- NONE(TMR),
- PERIPHC_UART1,
- PERIPHC_UART2, /* and vfir 0x68 */
-
- /* 8 */
- NONE(GPIO),
- PERIPHC_SDMMC2,
- NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
- PERIPHC_I2S1,
- PERIPHC_I2C1,
- PERIPHC_NDFLASH,
- PERIPHC_SDMMC1,
- PERIPHC_SDMMC4,
-
- /* 16 */
- NONE(RESERVED16),
- PERIPHC_PWM,
- PERIPHC_I2S2,
- PERIPHC_EPP,
- PERIPHC_VI,
- PERIPHC_G2D,
- NONE(USBD),
- NONE(ISP),
-
- /* 24 */
- PERIPHC_G3D,
- NONE(RESERVED25),
- PERIPHC_DISP2,
- PERIPHC_DISP1,
- PERIPHC_HOST1X,
- NONE(VCP),
- PERIPHC_I2S0,
- NONE(CACHE2),
-
- /* Middle word: 63:32 */
- NONE(MEM),
- NONE(AHBDMA),
- NONE(APBDMA),
- NONE(RESERVED35),
- NONE(RESERVED36),
- NONE(STAT_MON),
- NONE(RESERVED38),
- NONE(RESERVED39),
-
- /* 40 */
- NONE(KFUSE),
- NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
- PERIPHC_NOR,
- NONE(RESERVED43),
- PERIPHC_SBC2,
- NONE(RESERVED45),
- PERIPHC_SBC3,
- PERIPHC_I2C5,
-
- /* 48 */
- NONE(DSI),
- PERIPHC_TVO, /* also CVE 0x40 */
- PERIPHC_MIPI,
- PERIPHC_HDMI,
- NONE(CSI),
- PERIPHC_TVDAC,
- PERIPHC_I2C2,
- PERIPHC_UART3,
-
- /* 56 */
- NONE(RESERVED56),
- PERIPHC_EMC,
- NONE(USB2),
- NONE(USB3),
- PERIPHC_MPE,
- PERIPHC_VDE,
- NONE(BSEA),
- NONE(BSEV),
-
- /* Upper word 95:64 */
- PERIPHC_SPEEDO,
- PERIPHC_UART4,
- PERIPHC_UART5,
- PERIPHC_I2C3,
- PERIPHC_SBC4,
- PERIPHC_SDMMC3,
- NONE(PCIE),
- PERIPHC_OWR,
-
- /* 72 */
- NONE(AFI),
- PERIPHC_CSITE,
- NONE(PCIEXCLK),
- NONE(AVPUCQ),
- NONE(RESERVED76),
- NONE(RESERVED77),
- NONE(RESERVED78),
- NONE(DTV),
-
- /* 80 */
- PERIPHC_NANDSPEED,
- PERIPHC_I2CSLOW,
- NONE(DSIB),
- NONE(RESERVED83),
- NONE(IRAMA),
- NONE(IRAMB),
- NONE(IRAMC),
- NONE(IRAMD),
-
- /* 88 */
- NONE(CRAM2),
- NONE(RESERVED89),
- NONE(MDOUBLER),
- NONE(RESERVED91),
- NONE(SUSOUT),
- NONE(RESERVED93),
- NONE(RESERVED94),
- NONE(RESERVED95),
-
- /* V word: 31:0 */
- NONE(CPUG),
- NONE(CPULP),
- PERIPHC_G3D2,
- PERIPHC_MSELECT,
- PERIPHC_TSENSOR,
- PERIPHC_I2S3,
- PERIPHC_I2S4,
- PERIPHC_I2C4,
-
- /* 08 */
- PERIPHC_SBC5,
- PERIPHC_SBC6,
- PERIPHC_AUDIO,
- NONE(APBIF),
- PERIPHC_DAM0,
- PERIPHC_DAM1,
- PERIPHC_DAM2,
- PERIPHC_HDA2CODEC2X,
-
- /* 16 */
- NONE(ATOMICS),
- NONE(RESERVED17),
- NONE(RESERVED18),
- NONE(RESERVED19),
- NONE(RESERVED20),
- NONE(RESERVED21),
- NONE(RESERVED22),
- PERIPHC_ACTMON,
-
- /* 24 */
- NONE(RESERVED24),
- NONE(RESERVED25),
- NONE(RESERVED26),
- NONE(RESERVED27),
- PERIPHC_SATA,
- PERIPHC_HDA,
- NONE(RESERVED30),
- NONE(RESERVED31),
-
- /* W word: 31:0 */
- NONE(HDA2HDMICODEC),
- NONE(RESERVED1_SATACOLD),
- NONE(RESERVED2_PCIERX0),
- NONE(RESERVED3_PCIERX1),
- NONE(RESERVED4_PCIERX2),
- NONE(RESERVED5_PCIERX3),
- NONE(RESERVED6_PCIERX4),
- NONE(RESERVED7_PCIERX5),
-
- /* 40 */
- NONE(CEC),
- NONE(PCIE2_IOBIST),
- NONE(EMC_IOBIST),
- NONE(HDMI_IOBIST),
- NONE(SATA_IOBIST),
- NONE(MIPI_IOBIST),
- NONE(EMC1_IOBIST),
- NONE(XUSB),
-
- /* 48 */
- NONE(CILAB),
- NONE(CILCD),
- NONE(CILE),
- NONE(DSIA_LP),
- NONE(DSIB_LP),
- NONE(RESERVED21_ENTROPY),
- NONE(RESERVED22_W),
- NONE(RESERVED23_W),
-
- /* 56 */
- NONE(RESERVED24_W),
- NONE(AMX0),
- NONE(ADX0),
- NONE(DVFS),
- NONE(XUSB_SS),
- NONE(EMC_DLL),
- NONE(MC1),
- NONE(EMC1),
-};
-
-/*
- * Get the oscillator frequency, from the corresponding hardware configuration
- * field. Note that T30/T114 support 3 new higher freqs, but we map back
- * to the old T20 freqs. Support for the higher oscillators is TBD.
- */
-enum clock_osc_freq clock_get_osc_freq(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- reg = readl(&clkrst->crc_osc_ctrl);
- reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
-
- if (reg & 1) /* one of the newer freqs */
- printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
-
- return reg >> 2; /* Map to most common (T20) freqs */
-}
-
-/* Returns a pointer to the clock source register for a peripheral */
-u32 *get_periph_source_reg(enum periph_id periph_id)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- enum periphc_internal_id internal_id;
-
- /* Coresight is a special case */
- if (periph_id == PERIPH_ID_CSI)
- return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
-
- assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
- internal_id = periph_id_to_internal_id[periph_id];
- assert(internal_id != -1);
- if (internal_id >= PERIPHC_VW_FIRST) {
- internal_id -= PERIPHC_VW_FIRST;
- return &clkrst->crc_clk_src_vw[internal_id];
- } else
- return &clkrst->crc_clk_src[internal_id];
-}
-
-/**
- * Given a peripheral ID and the required source clock, this returns which
- * value should be programmed into the source mux for that peripheral.
- *
- * There is special code here to handle the one source type with 5 sources.
- *
- * @param periph_id peripheral to start
- * @param source PLL id of required parent clock
- * @param mux_bits Set to number of bits in mux register: 2 or 4
- * @param divider_bits Set to number of divider bits (8 or 16)
- * @return mux value (0-4, or -1 if not found)
- */
-int get_periph_clock_source(enum periph_id periph_id,
- enum clock_id parent, int *mux_bits, int *divider_bits)
-{
- enum clock_type_id type;
- enum periphc_internal_id internal_id;
- int mux;
-
- assert(clock_periph_id_isvalid(periph_id));
-
- internal_id = periph_id_to_internal_id[periph_id];
- assert(periphc_internal_id_isvalid(internal_id));
-
- type = clock_periph_type[internal_id];
- assert(clock_type_id_isvalid(type));
-
- *mux_bits = clock_source[type][CLOCK_MAX_MUX];
-
- if (type == CLOCK_TYPE_PCMT16)
- *divider_bits = 16;
- else
- *divider_bits = 8;
-
- for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
- if (clock_source[type][mux] == parent)
- return mux;
-
- /* if we get here, either us or the caller has made a mistake */
- printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
- parent);
- return -1;
-}
-
-void clock_set_enable(enum periph_id periph_id, int enable)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *clk;
- u32 reg;
-
- /* Enable/disable the clock to this peripheral */
- assert(clock_periph_id_isvalid(periph_id));
- if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
- clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
- else
- clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
- reg = readl(clk);
- if (enable)
- reg |= PERIPH_MASK(periph_id);
- else
- reg &= ~PERIPH_MASK(periph_id);
- writel(reg, clk);
-}
-
-void reset_set_enable(enum periph_id periph_id, int enable)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *reset;
- u32 reg;
-
- /* Enable/disable reset to the peripheral */
- assert(clock_periph_id_isvalid(periph_id));
- if (periph_id < PERIPH_ID_VW_FIRST)
- reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
- else
- reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
- reg = readl(reset);
- if (enable)
- reg |= PERIPH_MASK(periph_id);
- else
- reg &= ~PERIPH_MASK(periph_id);
- writel(reg, reset);
-}
-
-#ifdef CONFIG_OF_CONTROL
-/*
- * Convert a device tree clock ID to our peripheral ID. They are mostly
- * the same but we are very cautious so we check that a valid clock ID is
- * provided.
- *
- * @param clk_id Clock ID according to tegra114 device tree binding
- * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
- */
-enum periph_id clk_id_to_periph_id(int clk_id)
-{
- if (clk_id > PERIPH_ID_COUNT)
- return PERIPH_ID_NONE;
-
- switch (clk_id) {
- case PERIPH_ID_RESERVED3:
- case PERIPH_ID_RESERVED16:
- case PERIPH_ID_RESERVED24:
- case PERIPH_ID_RESERVED35:
- case PERIPH_ID_RESERVED43:
- case PERIPH_ID_RESERVED45:
- case PERIPH_ID_RESERVED56:
- case PERIPH_ID_RESERVED76:
- case PERIPH_ID_RESERVED77:
- case PERIPH_ID_RESERVED78:
- case PERIPH_ID_RESERVED83:
- case PERIPH_ID_RESERVED89:
- case PERIPH_ID_RESERVED91:
- case PERIPH_ID_RESERVED93:
- case PERIPH_ID_RESERVED94:
- case PERIPH_ID_RESERVED95:
- return PERIPH_ID_NONE;
- default:
- return clk_id;
- }
-}
-#endif /* CONFIG_OF_CONTROL */
-
-void clock_early_init(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-
- tegra30_set_up_pllp();
-
- /*
- * PLLC output frequency set to 600Mhz
- * PLLD output frequency set to 925Mhz
- */
- switch (clock_get_osc_freq()) {
- case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
- clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
- break;
-
- case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
- clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
- break;
-
- case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
- clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
- break;
- case CLOCK_OSC_FREQ_19_2:
- default:
- /*
- * These are not supported. It is too early to print a
- * message and the UART likely won't work anyway due to the
- * oscillator being wrong.
- */
- break;
- }
-
- /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
- writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
-
- /* PLLC_MISC: Set LOCK_ENABLE */
- writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
- udelay(2);
-
- /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
- writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
- udelay(2);
-}
-
-void arch_timer_init(void)
-{
- struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
- u32 freq, val;
-
- freq = clock_get_rate(CLOCK_ID_OSC);
- debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
-
- /* ARM CNTFRQ */
- asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
-
- /* Only T114 has the System Counter regs */
- debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
- writel(freq, &sysctr->cntfid0);
-
- val = readl(&sysctr->cntcr);
- val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
- writel(val, &sysctr->cntcr);
- debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
-}
diff --git a/arch/arm/cpu/tegra114-common/funcmux.c b/arch/arm/cpu/tegra114-common/funcmux.c
deleted file mode 100644
index 52441c7..0000000
--- a/arch/arm/cpu/tegra114-common/funcmux.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Tegra114 high-level function multiplexing */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-
-int funcmux_select(enum periph_id id, int config)
-{
- int bad_config = config != FUNCMUX_DEFAULT;
-
- switch (id) {
- case PERIPH_ID_UART4:
- switch (config) {
- case FUNCMUX_UART4_GMI:
- pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7,
- PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0,
- PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1,
- PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7,
- PMUX_FUNC_UARTD);
-
- pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT);
- pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT);
- pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT);
- pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT);
-
- pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7);
- pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0);
- pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1);
- pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7);
- break;
- }
- break;
-
- /* Add other periph IDs here as needed */
-
- default:
- debug("%s: invalid periph_id %d", __func__, id);
- return -1;
- }
-
- if (bad_config) {
- debug("%s: invalid config %d for periph_id %d", __func__,
- config, id);
- return -1;
- }
- return 0;
-}
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
deleted file mode 100644
index 3e5acb9..0000000
--- a/arch/arm/cpu/tegra114-common/pinmux.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-#define PIN(pin, f0, f1, f2, f3) \
- { \
- .funcs = { \
- PMUX_FUNC_##f0, \
- PMUX_FUNC_##f1, \
- PMUX_FUNC_##f2, \
- PMUX_FUNC_##f3, \
- }, \
- }
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra114_pingroups[] = {
- /* pin, f0, f1, f2, f3 */
- /* Offset 0x3000 */
- PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI),
- PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_SCLK_PP3, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(PV0, USB, RSVD2, RSVD3, RSVD4),
- PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
- PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
- PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
- PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
- PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
- PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3068 */
- PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3110 */
- PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3164 */
- PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4),
- PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4),
- PIN(UART2_RTS_N_PJ6, UARTA, UARTB, RSVD3, SPI4),
- PIN(UART2_CTS_N_PJ5, UARTA, UARTB, RSVD3, SPI4),
- PIN(UART3_TXD_PW6, UARTC, RSVD2, RSVD3, SPI4),
- PIN(UART3_RXD_PW7, UARTC, RSVD2, RSVD3, SPI4),
- PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, SPI4),
- PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, DISPLAYA),
- PIN(PU0, OWR, UARTA, RSVD3, RSVD4),
- PIN(PU1, RSVD1, UARTA, RSVD3, RSVD4),
- PIN(PU2, RSVD1, UARTA, RSVD3, RSVD4),
- PIN(PU3, PWM0, UARTA, DISPLAYA, DISPLAYB),
- PIN(PU4, PWM1, UARTA, DISPLAYA, DISPLAYB),
- PIN(PU5, PWM2, UARTA, DISPLAYA, DISPLAYB),
- PIN(PU6, PWM3, UARTA, USB, DISPLAYB),
- PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(DAP4_FS_PP4, I2S3, RSVD2, DTV, RSVD4),
- PIN(DAP4_DIN_PP5, I2S3, RSVD2, RSVD3, RSVD4),
- PIN(DAP4_DOUT_PP6, I2S3, RSVD2, DTV, RSVD4),
- PIN(DAP4_SCLK_PP7, I2S3, RSVD2, RSVD3, RSVD4),
- PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
- PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
- PIN(GMI_IORDY_PI5, SDMMC2, RSVD2, GMI, TRACE),
- PIN(GMI_WAIT_PI7, SPI4, NAND, GMI, DTV),
- PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, TRACE),
- PIN(GMI_CLK_PK1, SDMMC2, NAND, GMI, TRACE),
- PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, USB),
- PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, SOC),
- PIN(GMI_CS2_N_PK3, SDMMC2, NAND, GMI, TRACE),
- PIN(GMI_CS3_N_PK4, SDMMC2, NAND, GMI, GMI_ALT),
- PIN(GMI_CS4_N_PK2, USB, NAND, GMI, TRACE),
- PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SPI4),
- PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, SDMMC2),
- PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, SPI4),
- PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, SPI4),
- PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, SPI4),
- PIN(GMI_AD8_PH0, PWM0, NAND, GMI, DTV),
- PIN(GMI_AD9_PH1, PWM1, NAND, GMI, CLDVFS),
- PIN(GMI_AD10_PH2, PWM2, NAND, GMI, CLDVFS),
- PIN(GMI_AD11_PH3, PWM3, NAND, GMI, USB),
- PIN(GMI_AD12_PH4, SDMMC2, NAND, GMI, RSVD4),
- PIN(GMI_AD13_PH5, SDMMC2, NAND, GMI, RSVD4),
- PIN(GMI_AD14_PH6, SDMMC2, NAND, GMI, DTV),
- PIN(GMI_AD15_PH7, SDMMC2, NAND, GMI, DTV),
- PIN(GMI_A16_PJ7, UARTD, TRACE, GMI, GMI_ALT),
- PIN(GMI_A17_PB0, UARTD, RSVD2, GMI, TRACE),
- PIN(GMI_A18_PB1, UARTD, RSVD2, GMI, TRACE),
- PIN(GMI_A19_PK7, UARTD, SPI4, GMI, TRACE),
- PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, SPI4),
- PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, SOC),
- PIN(GMI_DQS_P_PJ3, SDMMC2, NAND, GMI, TRACE),
- PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4),
- PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4),
- PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4),
- PIN_RESERVED,
- /* Offset 0x3284 */
- PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, RSVD4),
- PIN(PCC1, I2S4, RSVD2, RSVD3, RSVD4),
- PIN(PBB0, I2S4, VI, VI_ALT1, VI_ALT3),
- PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, RSVD4),
- PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, RSVD4),
- PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, RSVD4),
- PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, RSVD4),
- PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, RSVD4),
- PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, RSVD4),
- PIN(PBB7, I2S4, RSVD2, RSVD3, RSVD4),
- PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
- PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW3_PR3, KBC, DISPLAYA, RSVD3, DISPLAYB),
- PIN(KB_ROW4_PR4, KBC, DISPLAYA, SPI2, DISPLAYB),
- PIN(KB_ROW5_PR5, KBC, DISPLAYA, SPI2, DISPLAYB),
- PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB),
- PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA),
- PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA),
- PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA),
- PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x32fc */
- PIN(KB_COL0_PQ0, KBC, USB, SPI2, EMC_DLL),
- PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, EMC_DLL),
- PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA),
- PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA),
- PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC1, RSVD4),
- PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, RSVD4),
- PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4),
- PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
- PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4),
- PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4),
- PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4),
- PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4),
- PIN(OWR, OWR, RSVD2, RSVD3, RSVD4),
- PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4),
- PIN(CLK1_REQ_PEE2, DAP, DAP1, RSVD3, RSVD4),
- PIN(CLK1_OUT_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4),
- PIN(SPDIF_IN_PK6, SPDIF, USB, RSVD3, RSVD4),
- PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, RSVD4),
- PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, RSVD4),
- PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, RSVD4),
- PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, RSVD4),
- PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, RSVD4),
- PIN(DVFS_PWM_PX0, SPI6, CLDVFS, RSVD3, RSVD4),
- PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, RSVD3, RSVD4),
- PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, RSVD3, RSVD4),
- PIN(DVFS_CLK_PX2, SPI6, CLDVFS, RSVD3, RSVD4),
- PIN(GPIO_X4_AUD_PX4, RSVD1, SPI1, SPI2, DAP2),
- PIN(GPIO_X5_AUD_PX5, RSVD1, SPI1, SPI2, RSVD4),
- PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, RSVD4),
- PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3390 */
- PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3),
- PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3),
- PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3),
- PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3),
- PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3),
- PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x33e0 */
- PIN(HDMI_CEC_PEE3, CEC, SDMMC3, RSVD3, SOC),
- PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
- PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4),
- PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1),
- PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1),
- PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4),
- PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN(GMI_CLK_LB, SDMMC2, NAND, GMI, RSVD4),
- PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups;
diff --git a/arch/arm/cpu/tegra124-common/Makefile b/arch/arm/cpu/tegra124-common/Makefile
deleted file mode 100644
index 7b59fb1..0000000
--- a/arch/arm/cpu/tegra124-common/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2013-2014
-# NVIDIA Corporation <www.nvidia.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += clock.o
-obj-y += funcmux.o
-obj-y += pinmux.o
-obj-y += xusb-padctl.o
diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/cpu/tegra124-common/clock.c
deleted file mode 100644
index fc8bd19..0000000
--- a/arch/arm/cpu/tegra124-common/clock.c
+++ /dev/null
@@ -1,935 +0,0 @@
-/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Tegra124 Clock control functions */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sysctr.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
-#include <div64.h>
-#include <fdtdec.h>
-
-/*
- * Clock types that we can use as a source. The Tegra124 has muxes for the
- * peripheral clocks, and in most cases there are four options for the clock
- * source. This gives us a clock 'type' and exploits what commonality exists
- * in the device.
- *
- * Letters are obvious, except for T which means CLK_M, and S which means the
- * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
- * datasheet) and PLL_M are different things. The former is the basic
- * clock supplied to the SOC from an external oscillator. The latter is the
- * memory clock PLL.
- *
- * See definitions in clock_id in the header file.
- */
-enum clock_type_id {
- CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
- CLOCK_TYPE_MCPA, /* and so on */
- CLOCK_TYPE_MCPT,
- CLOCK_TYPE_PCM,
- CLOCK_TYPE_PCMT,
- CLOCK_TYPE_PDCT,
- CLOCK_TYPE_ACPT,
- CLOCK_TYPE_ASPTE,
- CLOCK_TYPE_PMDACD2T,
- CLOCK_TYPE_PCST,
-
- CLOCK_TYPE_PC2CC3M,
- CLOCK_TYPE_PC2CC3S_T,
- CLOCK_TYPE_PC2CC3M_T,
- CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
- CLOCK_TYPE_MC2CC3P_A,
- CLOCK_TYPE_M,
- CLOCK_TYPE_MCPTM2C2C3,
- CLOCK_TYPE_PC2CC3T_S,
- CLOCK_TYPE_AC2CC3P_TS2,
-
- CLOCK_TYPE_COUNT,
- CLOCK_TYPE_NONE = -1, /* invalid clock type */
-};
-
-enum {
- CLOCK_MAX_MUX = 8 /* number of source options for each clock */
-};
-
-/*
- * Clock source mux for each clock type. This just converts our enum into
- * a list of mux sources for use by the code.
- *
- * Note:
- * The extra column in each clock source array is used to store the mask
- * bits in its register for the source.
- */
-#define CLK(x) CLOCK_ID_ ## x
-static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
- { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
- CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_29},
- { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
- CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
- MASK_BITS_31_29},
- { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_28},
-
- /* Additional clock types on Tegra114+ */
- /* CLOCK_TYPE_PC2CC3M */
- { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_PC2CC3S_T */
- { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_PC2CC3M_T */
- { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
- { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_MC2CC3P_A */
- { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_M */
- { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- /* CLOCK_TYPE_MCPTM2C2C3 */
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
- CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_PC2CC3T_S */
- { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
- MASK_BITS_31_29},
- /* CLOCK_TYPE_AC2CC3P_TS2 */
- { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
- CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
- MASK_BITS_31_29},
-};
-
-/*
- * Clock type for each peripheral clock source. We put the name in each
- * record just so it is easy to match things up
- */
-#define TYPE(name, type) type
-static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
- /* 0x00 */
- TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
- TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
- TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
-
- /* 0x08 */
- TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
- TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
- TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
- TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
-
- /* 0x10 */
- TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
- TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
-
- /* 0x18 */
- TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
-
- /* 0x20 */
- TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
- TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
- TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
- TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
-
- /* 0x28 */
- TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
- TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
- TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
-
- /* 0x30 */
- TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
-
- /* 0x38 */
- TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
- TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
-
- /* 0x40 */
- TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
- TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
- TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
- TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
-
- /* 0x48 */
- TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
- TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
-
- /* 0x50 */
- TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
- TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
- TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
- TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
-
- /* 0x58 */
- TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
- TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
-
- /* 0x60 */
- TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
-
- /* 0x68 */
- TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE),
-
- /* 0x70 */
- TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
-
- /* 0x78 */
- TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
- TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2),
- TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
-};
-
-/*
- * This array translates a periph_id to a periphc_internal_id
- *
- * Not present/matched up:
- * uint vi_sensor; _VI_SENSOR_0, 0x1A8
- * SPDIF - which is both 0x08 and 0x0c
- *
- */
-#define NONE(name) (-1)
-#define OFFSET(name, value) PERIPHC_ ## name
-static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
- /* Low word: 31:0 */
- NONE(CPU),
- NONE(COP),
- NONE(TRIGSYS),
- NONE(ISPB),
- NONE(RESERVED4),
- NONE(TMR),
- PERIPHC_UART1,
- PERIPHC_UART2, /* and vfir 0x68 */
-
- /* 8 */
- NONE(GPIO),
- PERIPHC_SDMMC2,
- PERIPHC_SPDIF_IN,
- PERIPHC_I2S1,
- PERIPHC_I2C1,
- NONE(RESERVED13),
- PERIPHC_SDMMC1,
- PERIPHC_SDMMC4,
-
- /* 16 */
- NONE(TCW),
- PERIPHC_PWM,
- PERIPHC_I2S2,
- NONE(RESERVED19),
- PERIPHC_VI,
- NONE(RESERVED21),
- NONE(USBD),
- NONE(ISP),
-
- /* 24 */
- NONE(RESERVED24),
- NONE(RESERVED25),
- PERIPHC_DISP2,
- PERIPHC_DISP1,
- PERIPHC_HOST1X,
- NONE(VCP),
- PERIPHC_I2S0,
- NONE(CACHE2),
-
- /* Middle word: 63:32 */
- NONE(MEM),
- NONE(AHBDMA),
- NONE(APBDMA),
- NONE(RESERVED35),
- NONE(RESERVED36),
- NONE(STAT_MON),
- NONE(RESERVED38),
- NONE(FUSE),
-
- /* 40 */
- NONE(KFUSE),
- PERIPHC_SBC1, /* SBCx = SPIx */
- PERIPHC_NOR,
- NONE(RESERVED43),
- PERIPHC_SBC2,
- NONE(XIO),
- PERIPHC_SBC3,
- PERIPHC_I2C5,
-
- /* 48 */
- NONE(DSI),
- NONE(RESERVED49),
- PERIPHC_HSI,
- PERIPHC_HDMI,
- NONE(CSI),
- NONE(RESERVED53),
- PERIPHC_I2C2,
- PERIPHC_UART3,
-
- /* 56 */
- NONE(MIPI_CAL),
- PERIPHC_EMC,
- NONE(USB2),
- NONE(USB3),
- NONE(RESERVED60),
- PERIPHC_VDE,
- NONE(BSEA),
- NONE(BSEV),
-
- /* Upper word 95:64 */
- NONE(RESERVED64),
- PERIPHC_UART4,
- PERIPHC_UART5,
- PERIPHC_I2C3,
- PERIPHC_SBC4,
- PERIPHC_SDMMC3,
- NONE(PCIE),
- PERIPHC_OWR,
-
- /* 72 */
- NONE(AFI),
- PERIPHC_CSITE,
- NONE(PCIEXCLK),
- NONE(AVPUCQ),
- NONE(LA),
- NONE(TRACECLKIN),
- NONE(SOC_THERM),
- NONE(DTV),
-
- /* 80 */
- NONE(RESERVED80),
- PERIPHC_I2CSLOW,
- NONE(DSIB),
- PERIPHC_TSEC,
- NONE(RESERVED84),
- NONE(RESERVED85),
- NONE(RESERVED86),
- NONE(EMUCIF),
-
- /* 88 */
- NONE(RESERVED88),
- NONE(XUSB_HOST),
- NONE(RESERVED90),
- PERIPHC_MSENC,
- NONE(RESERVED92),
- NONE(RESERVED93),
- NONE(RESERVED94),
- NONE(XUSB_DEV),
-
- /* V word: 31:0 */
- NONE(CPUG),
- NONE(CPULP),
- NONE(V_RESERVED2),
- PERIPHC_MSELECT,
- NONE(V_RESERVED4),
- PERIPHC_I2S3,
- PERIPHC_I2S4,
- PERIPHC_I2C4,
-
- /* 104 */
- PERIPHC_SBC5,
- PERIPHC_SBC6,
- PERIPHC_AUDIO,
- NONE(APBIF),
- PERIPHC_DAM0,
- PERIPHC_DAM1,
- PERIPHC_DAM2,
- PERIPHC_HDA2CODEC2X,
-
- /* 112 */
- NONE(ATOMICS),
- NONE(V_RESERVED17),
- NONE(V_RESERVED18),
- NONE(V_RESERVED19),
- NONE(V_RESERVED20),
- NONE(V_RESERVED21),
- NONE(V_RESERVED22),
- PERIPHC_ACTMON,
-
- /* 120 */
- NONE(EXTPERIPH1),
- NONE(EXTPERIPH2),
- NONE(EXTPERIPH3),
- NONE(OOB),
- PERIPHC_SATA,
- PERIPHC_HDA,
- NONE(TZRAM),
- NONE(SE),
-
- /* W word: 31:0 */
- NONE(HDA2HDMICODEC),
- NONE(SATACOLD),
- NONE(W_RESERVED2),
- NONE(W_RESERVED3),
- NONE(W_RESERVED4),
- NONE(W_RESERVED5),
- NONE(W_RESERVED6),
- NONE(W_RESERVED7),
-
- /* 136 */
- NONE(CEC),
- NONE(W_RESERVED9),
- NONE(W_RESERVED10),
- NONE(W_RESERVED11),
- NONE(W_RESERVED12),
- NONE(W_RESERVED13),
- NONE(XUSB_PADCTL),
- NONE(W_RESERVED15),
-
- /* 144 */
- NONE(W_RESERVED16),
- NONE(W_RESERVED17),
- NONE(W_RESERVED18),
- NONE(W_RESERVED19),
- NONE(W_RESERVED20),
- NONE(ENTROPY),
- NONE(DDS),
- NONE(W_RESERVED23),
-
- /* 152 */
- NONE(DP2),
- NONE(AMX0),
- NONE(ADX0),
- NONE(DVFS),
- NONE(XUSB_SS),
- NONE(W_RESERVED29),
- NONE(W_RESERVED30),
- NONE(W_RESERVED31),
-
- /* X word: 31:0 */
- NONE(SPARE),
- NONE(X_RESERVED1),
- NONE(X_RESERVED2),
- NONE(X_RESERVED3),
- NONE(CAM_MCLK),
- NONE(CAM_MCLK2),
- PERIPHC_I2C6,
- NONE(X_RESERVED7),
-
- /* 168 */
- NONE(X_RESERVED8),
- NONE(X_RESERVED9),
- NONE(X_RESERVED10),
- NONE(VIM2_CLK),
- NONE(X_RESERVED12),
- NONE(X_RESERVED13),
- NONE(EMC_DLL),
- NONE(X_RESERVED15),
-
- /* 176 */
- NONE(HDMI_AUDIO),
- NONE(CLK72MHZ),
- NONE(VIC),
- NONE(X_RESERVED19),
- NONE(ADX1),
- NONE(DPAUX),
- NONE(SOR0),
- NONE(X_RESERVED23),
-
- /* 184 */
- NONE(GPU),
- NONE(AMX1),
- NONE(X_RESERVED26),
- NONE(X_RESERVED27),
- NONE(X_RESERVED28),
- NONE(X_RESERVED29),
- NONE(X_RESERVED30),
- NONE(X_RESERVED31),
-};
-
-/*
- * Get the oscillator frequency, from the corresponding hardware configuration
- * field. Note that Tegra30+ support 3 new higher freqs, but we map back
- * to the old T20 freqs. Support for the higher oscillators is TBD.
- */
-enum clock_osc_freq clock_get_osc_freq(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- reg = readl(&clkrst->crc_osc_ctrl);
- reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
-
- if (reg & 1) /* one of the newer freqs */
- printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
-
- return reg >> 2; /* Map to most common (T20) freqs */
-}
-
-/* Returns a pointer to the clock source register for a peripheral */
-u32 *get_periph_source_reg(enum periph_id periph_id)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- enum periphc_internal_id internal_id;
-
- /* Coresight is a special case */
- if (periph_id == PERIPH_ID_CSI)
- return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
-
- assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
- internal_id = periph_id_to_internal_id[periph_id];
- assert(internal_id != -1);
- if (internal_id >= PERIPHC_VW_FIRST) {
- internal_id -= PERIPHC_VW_FIRST;
- return &clkrst->crc_clk_src_vw[internal_id];
- } else {
- return &clkrst->crc_clk_src[internal_id];
- }
-}
-
-/**
- * Given a peripheral ID and the required source clock, this returns which
- * value should be programmed into the source mux for that peripheral.
- *
- * There is special code here to handle the one source type with 5 sources.
- *
- * @param periph_id peripheral to start
- * @param source PLL id of required parent clock
- * @param mux_bits Set to number of bits in mux register: 2 or 4
- * @param divider_bits Set to number of divider bits (8 or 16)
- * @return mux value (0-4, or -1 if not found)
- */
-int get_periph_clock_source(enum periph_id periph_id,
- enum clock_id parent, int *mux_bits, int *divider_bits)
-{
- enum clock_type_id type;
- enum periphc_internal_id internal_id;
- int mux;
-
- assert(clock_periph_id_isvalid(periph_id));
-
- internal_id = periph_id_to_internal_id[periph_id];
- assert(periphc_internal_id_isvalid(internal_id));
-
- type = clock_periph_type[internal_id];
- assert(clock_type_id_isvalid(type));
-
- *mux_bits = clock_source[type][CLOCK_MAX_MUX];
-
- if (type == CLOCK_TYPE_PC2CC3M_T16)
- *divider_bits = 16;
- else
- *divider_bits = 8;
-
- for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
- if (clock_source[type][mux] == parent)
- return mux;
-
- /* if we get here, either us or the caller has made a mistake */
- printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
- parent);
- return -1;
-}
-
-void clock_set_enable(enum periph_id periph_id, int enable)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *clk;
- u32 reg;
-
- /* Enable/disable the clock to this peripheral */
- assert(clock_periph_id_isvalid(periph_id));
- if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
- clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
- else
- clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
- reg = readl(clk);
- if (enable)
- reg |= PERIPH_MASK(periph_id);
- else
- reg &= ~PERIPH_MASK(periph_id);
- writel(reg, clk);
-}
-
-void reset_set_enable(enum periph_id periph_id, int enable)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *reset;
- u32 reg;
-
- /* Enable/disable reset to the peripheral */
- assert(clock_periph_id_isvalid(periph_id));
- if (periph_id < PERIPH_ID_VW_FIRST)
- reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
- else
- reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
- reg = readl(reset);
- if (enable)
- reg |= PERIPH_MASK(periph_id);
- else
- reg &= ~PERIPH_MASK(periph_id);
- writel(reg, reset);
-}
-
-#ifdef CONFIG_OF_CONTROL
-/*
- * Convert a device tree clock ID to our peripheral ID. They are mostly
- * the same but we are very cautious so we check that a valid clock ID is
- * provided.
- *
- * @param clk_id Clock ID according to tegra124 device tree binding
- * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
- */
-enum periph_id clk_id_to_periph_id(int clk_id)
-{
- if (clk_id > PERIPH_ID_COUNT)
- return PERIPH_ID_NONE;
-
- switch (clk_id) {
- case PERIPH_ID_RESERVED4:
- case PERIPH_ID_RESERVED25:
- case PERIPH_ID_RESERVED35:
- case PERIPH_ID_RESERVED36:
- case PERIPH_ID_RESERVED38:
- case PERIPH_ID_RESERVED43:
- case PERIPH_ID_RESERVED49:
- case PERIPH_ID_RESERVED53:
- case PERIPH_ID_RESERVED64:
- case PERIPH_ID_RESERVED84:
- case PERIPH_ID_RESERVED85:
- case PERIPH_ID_RESERVED86:
- case PERIPH_ID_RESERVED88:
- case PERIPH_ID_RESERVED90:
- case PERIPH_ID_RESERVED92:
- case PERIPH_ID_RESERVED93:
- case PERIPH_ID_RESERVED94:
- case PERIPH_ID_V_RESERVED2:
- case PERIPH_ID_V_RESERVED4:
- case PERIPH_ID_V_RESERVED17:
- case PERIPH_ID_V_RESERVED18:
- case PERIPH_ID_V_RESERVED19:
- case PERIPH_ID_V_RESERVED20:
- case PERIPH_ID_V_RESERVED21:
- case PERIPH_ID_V_RESERVED22:
- case PERIPH_ID_W_RESERVED2:
- case PERIPH_ID_W_RESERVED3:
- case PERIPH_ID_W_RESERVED4:
- case PERIPH_ID_W_RESERVED5:
- case PERIPH_ID_W_RESERVED6:
- case PERIPH_ID_W_RESERVED7:
- case PERIPH_ID_W_RESERVED9:
- case PERIPH_ID_W_RESERVED10:
- case PERIPH_ID_W_RESERVED11:
- case PERIPH_ID_W_RESERVED12:
- case PERIPH_ID_W_RESERVED13:
- case PERIPH_ID_W_RESERVED15:
- case PERIPH_ID_W_RESERVED16:
- case PERIPH_ID_W_RESERVED17:
- case PERIPH_ID_W_RESERVED18:
- case PERIPH_ID_W_RESERVED19:
- case PERIPH_ID_W_RESERVED20:
- case PERIPH_ID_W_RESERVED23:
- case PERIPH_ID_W_RESERVED29:
- case PERIPH_ID_W_RESERVED30:
- case PERIPH_ID_W_RESERVED31:
- return PERIPH_ID_NONE;
- default:
- return clk_id;
- }
-}
-#endif /* CONFIG_OF_CONTROL */
-
-void clock_early_init(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-
- tegra30_set_up_pllp();
-
- /*
- * PLLC output frequency set to 600Mhz
- * PLLD output frequency set to 925Mhz
- */
- switch (clock_get_osc_freq()) {
- case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
- clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
- break;
-
- case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
- clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
- break;
-
- case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
- clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
- break;
- case CLOCK_OSC_FREQ_19_2:
- default:
- /*
- * These are not supported. It is too early to print a
- * message and the UART likely won't work anyway due to the
- * oscillator being wrong.
- */
- break;
- }
-
- /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
- writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
-
- /* PLLC_MISC: Set LOCK_ENABLE */
- writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
- udelay(2);
-
- /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
- writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
- udelay(2);
-}
-
-void arch_timer_init(void)
-{
- struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
- u32 freq, val;
-
- freq = clock_get_rate(CLOCK_ID_OSC);
- debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
-
- /* ARM CNTFRQ */
- asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
-
- /* Only Tegra114+ has the System Counter regs */
- debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
- writel(freq, &sysctr->cntfid0);
-
- val = readl(&sysctr->cntcr);
- val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
- writel(val, &sysctr->cntcr);
- debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
-}
-
-#define PLLE_SS_CNTL 0x68
-#define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
-#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
-#define PLLE_SS_CNTL_SSCINVERT (1 << 15)
-#define PLLE_SS_CNTL_SSCCENTER (1 << 14)
-#define PLLE_SS_CNTL_SSCBYP (1 << 12)
-#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
-#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
-#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
-
-#define PLLE_BASE 0x0e8
-#define PLLE_BASE_ENABLE (1 << 30)
-#define PLLE_BASE_LOCK_OVERRIDE (1 << 29)
-#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
-#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
-#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
-
-#define PLLE_MISC 0x0ec
-#define PLLE_MISC_IDDQ_SWCTL (1 << 14)
-#define PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
-#define PLLE_MISC_LOCK_ENABLE (1 << 9)
-#define PLLE_MISC_PTS (1 << 8)
-#define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
-#define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
-
-#define PLLE_AUX 0x48c
-#define PLLE_AUX_SEQ_ENABLE (1 << 24)
-#define PLLE_AUX_ENABLE_SWCTL (1 << 4)
-
-int tegra_plle_enable(void)
-{
- unsigned int m = 1, n = 200, cpcon = 13;
- u32 value;
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
- value &= ~PLLE_BASE_LOCK_OVERRIDE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
- value |= PLLE_AUX_ENABLE_SWCTL;
- value &= ~PLLE_AUX_SEQ_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
- udelay(1);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- value |= PLLE_MISC_IDDQ_SWCTL;
- value &= ~PLLE_MISC_IDDQ_OVERRIDE;
- value |= PLLE_MISC_LOCK_ENABLE;
- value |= PLLE_MISC_PTS;
- value |= PLLE_MISC_VREG_BG_CTRL(3);
- value |= PLLE_MISC_VREG_CTRL(2);
- writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
- udelay(5);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
- PLLE_SS_CNTL_BYPASS_SS;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
- value &= ~PLLE_BASE_PLDIV_CML(0xf);
- value &= ~PLLE_BASE_NDIV(0xff);
- value &= ~PLLE_BASE_MDIV(0xff);
- value |= PLLE_BASE_PLDIV_CML(cpcon);
- value |= PLLE_BASE_NDIV(n);
- value |= PLLE_BASE_MDIV(m);
- writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- udelay(1);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
- value |= PLLE_BASE_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- /* wait for lock */
- udelay(300);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value &= ~PLLE_SS_CNTL_SSCINVERT;
- value &= ~PLLE_SS_CNTL_SSCCENTER;
-
- value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
- value &= ~PLLE_SS_CNTL_SSCINC(0xff);
- value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
-
- value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
- value |= PLLE_SS_CNTL_SSCINC(0x01);
- value |= PLLE_SS_CNTL_SSCMAX(0x25);
-
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value &= ~PLLE_SS_CNTL_SSCBYP;
- value &= ~PLLE_SS_CNTL_BYPASS_SS;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- udelay(1);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value &= ~PLLE_SS_CNTL_INTERP_RESET;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- udelay(1);
-
- return 0;
-}
diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/cpu/tegra124-common/funcmux.c
deleted file mode 100644
index cced787..0000000
--- a/arch/arm/cpu/tegra124-common/funcmux.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Tegra124 high-level function multiplexing */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-
-int funcmux_select(enum periph_id id, int config)
-{
- int bad_config = config != FUNCMUX_DEFAULT;
-
- switch (id) {
- case PERIPH_ID_UART4:
- switch (config) {
- case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
- pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
- pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
-
- pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
- pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
- pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
- pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
-
- pinmux_tristate_disable(PMUX_PINGRP_PJ7);
- pinmux_tristate_disable(PMUX_PINGRP_PB0);
- pinmux_tristate_disable(PMUX_PINGRP_PB1);
- pinmux_tristate_disable(PMUX_PINGRP_PK7);
- break;
- }
- break;
-
- case PERIPH_ID_UART1:
- switch (config) {
- case FUNCMUX_UART1_KBC:
- pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
- PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
- PMUX_FUNC_UARTA);
-
- pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
- pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
-
- pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
- pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
- break;
- }
- break;
-
- /* Add other periph IDs here as needed */
-
- default:
- debug("%s: invalid periph_id %d", __func__, id);
- return -1;
- }
-
- if (bad_config) {
- debug("%s: invalid config %d for periph_id %d", __func__,
- config, id);
- return -1;
- }
- return 0;
-}
diff --git a/arch/arm/cpu/tegra124-common/pinmux.c b/arch/arm/cpu/tegra124-common/pinmux.c
deleted file mode 100644
index c6685ea..0000000
--- a/arch/arm/cpu/tegra124-common/pinmux.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-#define PIN(pin, f0, f1, f2, f3) \
- { \
- .funcs = { \
- PMUX_FUNC_##f0, \
- PMUX_FUNC_##f1, \
- PMUX_FUNC_##f2, \
- PMUX_FUNC_##f3, \
- }, \
- }
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra124_pingroups[] = {
- /* pin, f0, f1, f2, f3 */
- /* Offset 0x3000 */
- PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI),
- PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI),
- PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB),
- PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, RSVD4),
- PIN(DAP3_SCLK_PP3, I2S2, SPI5, RSVD3, DISPLAYB),
- PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
- PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
- PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
- PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
- PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
- PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3068 */
- PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3110 */
- PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3164 */
- PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4),
- PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4),
- PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4),
- PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4),
- PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, SPI4),
- PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, SPI4),
- PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, GMI),
- PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, GMI),
- PIN(PU0, OWR, UARTA, GMI, RSVD4),
- PIN(PU1, RSVD1, UARTA, GMI, RSVD4),
- PIN(PU2, RSVD1, UARTA, GMI, RSVD4),
- PIN(PU3, PWM0, UARTA, GMI, DISPLAYB),
- PIN(PU4, PWM1, UARTA, GMI, DISPLAYB),
- PIN(PU5, PWM2, UARTA, GMI, DISPLAYB),
- PIN(PU6, PWM3, UARTA, RSVD3, GMI),
- PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(DAP4_FS_PP4, I2S3, GMI, DTV, RSVD4),
- PIN(DAP4_DIN_PP5, I2S3, GMI, RSVD3, RSVD4),
- PIN(DAP4_DOUT_PP6, I2S3, GMI, DTV, RSVD4),
- PIN(DAP4_SCLK_PP7, I2S3, GMI, RSVD3, RSVD4),
- PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
- PIN(PC7, RSVD1, RSVD2, GMI, GMI_ALT),
- PIN(PI5, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(PI7, RSVD1, TRACE, GMI, DTV),
- PIN(PK0, RSVD1, SDMMC3, GMI, SOC),
- PIN(PK1, SDMMC2, TRACE, GMI, RSVD4),
- PIN(PJ0, RSVD1, RSVD2, GMI, USB),
- PIN(PJ2, RSVD1, RSVD2, GMI, SOC),
- PIN(PK3, SDMMC2, TRACE, GMI, CCLA),
- PIN(PK4, SDMMC2, RSVD2, GMI, GMI_ALT),
- PIN(PK2, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PI3, RSVD1, RSVD2, GMI, SPI4),
- PIN(PI6, RSVD1, RSVD2, GMI, SDMMC2),
- PIN(PG0, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PG1, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PG2, RSVD1, TRACE, GMI, RSVD4),
- PIN(PG3, RSVD1, TRACE, GMI, RSVD4),
- PIN(PG4, RSVD1, TMDS, GMI, SPI4),
- PIN(PG5, RSVD1, RSVD2, GMI, SPI4),
- PIN(PG6, RSVD1, RSVD2, GMI, SPI4),
- PIN(PG7, RSVD1, RSVD2, GMI, SPI4),
- PIN(PH0, PWM0, TRACE, GMI, DTV),
- PIN(PH1, PWM1, TMDS, GMI, DISPLAYA),
- PIN(PH2, PWM2, TMDS, GMI, CLDVFS),
- PIN(PH3, PWM3, SPI4, GMI, CLDVFS),
- PIN(PH4, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(PH5, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(PH6, SDMMC2, TRACE, GMI, DTV),
- PIN(PH7, SDMMC2, TRACE, GMI, DTV),
- PIN(PJ7, UARTD, RSVD2, GMI, GMI_ALT),
- PIN(PB0, UARTD, RSVD2, GMI, RSVD4),
- PIN(PB1, UARTD, RSVD2, GMI, RSVD4),
- PIN(PK7, UARTD, RSVD2, GMI, RSVD4),
- PIN(PI0, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PI1, RSVD1, RSVD2, GMI, RSVD4),
- PIN(PI2, SDMMC2, TRACE, GMI, RSVD4),
- PIN(PI4, SPI4, TRACE, GMI, DISPLAYA),
- PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4),
- PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4),
- PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, RSVD3, RSVD4),
- PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4),
- PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4),
- PIN_RESERVED,
- /* Offset 0x3284 */
- PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC2),
- PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC2),
- PIN(PBB0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT),
- PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC2),
- PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC2),
- PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC2),
- PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC2),
- PIN(PBB5, VGP5, DISPLAYA, RSVD3, SDMMC2),
- PIN(PBB6, I2S4, RSVD2, DISPLAYB, SDMMC2),
- PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC2),
- PIN(PCC2, I2S4, RSVD2, SDMMC3, SDMMC2),
- PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW3_PR3, KBC, DISPLAYA, SYS, DISPLAYB),
- PIN(KB_ROW4_PR4, KBC, DISPLAYA, RSVD3, DISPLAYB),
- PIN(KB_ROW5_PR5, KBC, DISPLAYA, RSVD3, DISPLAYB),
- PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB),
- PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA),
- PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA),
- PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA),
- PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA),
- PIN(KB_ROW11_PS3, KBC, RSVD2, RSVD3, IRDA),
- PIN(KB_ROW12_PS4, KBC, RSVD2, RSVD3, IRDA),
- PIN(KB_ROW13_PS5, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_ROW14_PS6, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_ROW15_PS7, KBC, SOC, RSVD3, RSVD4),
- PIN(KB_COL0_PQ0, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4),
- PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA),
- PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA),
- PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC3, RSVD4),
- PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, UARTD),
- PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, UARTD),
- PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4),
- PIN_RESERVED,
- /* Offset 0x3324 */
- PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4),
- PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4),
- PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4),
- PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4),
- PIN(OWR, OWR, RSVD2, RSVD3, RSVD4),
- PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4),
- PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SATA),
- PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4),
- PIN(DAP_MCLK1_REQ_PEE2, DAP, DAP1, SATA, RSVD4),
- PIN(DAP_MCLK1_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4),
- PIN(SPDIF_IN_PK6, SPDIF, RSVD2, RSVD3, I2C3),
- PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, I2C3),
- PIN(DAP2_FS_PA2, I2S1, HDA, GMI, RSVD4),
- PIN(DAP2_DIN_PA4, I2S1, HDA, GMI, RSVD4),
- PIN(DAP2_DOUT_PA5, I2S1, HDA, GMI, RSVD4),
- PIN(DAP2_SCLK_PA3, I2S1, HDA, GMI, RSVD4),
- PIN(DVFS_PWM_PX0, SPI6, CLDVFS, GMI, RSVD4),
- PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, GMI, RSVD4),
- PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, GMI, RSVD4),
- PIN(DVFS_CLK_PX2, SPI6, CLDVFS, GMI, RSVD4),
- PIN(GPIO_X4_AUD_PX4, GMI, SPI1, SPI2, DAP2),
- PIN(GPIO_X5_AUD_PX5, GMI, SPI1, SPI2, RSVD4),
- PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, GMI),
- PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3390 */
- PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3),
- PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3),
- PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3),
- PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3),
- PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3),
- PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x33bc */
- PIN(PEX_L0_RST_N_PDD1, PE0, RSVD2, RSVD3, RSVD4),
- PIN(PEX_L0_CLKREQ_N_PDD2, PE0, RSVD2, RSVD3, RSVD4),
- PIN(PEX_WAKE_N_PDD3, PE, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- /* Offset 0x33cc */
- PIN(PEX_L1_RST_N_PDD5, PE1, RSVD2, RSVD3, RSVD4),
- PIN(PEX_L1_CLKREQ_N_PDD6, PE1, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x33e0 */
- PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
- PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4),
- PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1),
- PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1),
- PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4),
- PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4),
- PIN(GMI_CLK_LB, SDMMC2, RSVD2, GMI, RSVD4),
- PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
- PIN(KB_ROW16_PT0, KBC, RSVD2, RSVD3, UARTC),
- PIN(KB_ROW17_PT1, KBC, RSVD2, RSVD3, UARTC),
- PIN(USB_VBUS_EN2_PFF1, USB, RSVD2, RSVD3, RSVD4),
- PIN(PFF2, SATA, RSVD2, RSVD3, RSVD4),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- PIN_RESERVED,
- /* Offset 0x3430 */
- PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
diff --git a/arch/arm/cpu/tegra124-common/xusb-padctl.c b/arch/arm/cpu/tegra124-common/xusb-padctl.c
deleted file mode 100644
index 43af883..0000000
--- a/arch/arm/cpu/tegra124-common/xusb-padctl.c
+++ /dev/null
@@ -1,716 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
-
-#include <common.h>
-#include <errno.h>
-#include <fdtdec.h>
-#include <malloc.h>
-
-#include <asm/io.h>
-
-#include <asm/arch/clock.h>
-#include <asm/arch-tegra/xusb-padctl.h>
-
-#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
-
-#define XUSB_PADCTL_ELPG_PROGRAM 0x01c
-#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
-#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
-#define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
-
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
-
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
-#define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
-
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
-#define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
-
-#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
-#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
-#define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
-
-enum tegra124_function {
- TEGRA124_FUNC_SNPS,
- TEGRA124_FUNC_XUSB,
- TEGRA124_FUNC_UART,
- TEGRA124_FUNC_PCIE,
- TEGRA124_FUNC_USB3,
- TEGRA124_FUNC_SATA,
- TEGRA124_FUNC_RSVD,
-};
-
-static const char *const tegra124_functions[] = {
- "snps",
- "xusb",
- "uart",
- "pcie",
- "usb3",
- "sata",
- "rsvd",
-};
-
-static const unsigned int tegra124_otg_functions[] = {
- TEGRA124_FUNC_SNPS,
- TEGRA124_FUNC_XUSB,
- TEGRA124_FUNC_UART,
- TEGRA124_FUNC_RSVD,
-};
-
-static const unsigned int tegra124_usb_functions[] = {
- TEGRA124_FUNC_SNPS,
- TEGRA124_FUNC_XUSB,
-};
-
-static const unsigned int tegra124_pci_functions[] = {
- TEGRA124_FUNC_PCIE,
- TEGRA124_FUNC_USB3,
- TEGRA124_FUNC_SATA,
- TEGRA124_FUNC_RSVD,
-};
-
-struct tegra_xusb_padctl_lane {
- const char *name;
-
- unsigned int offset;
- unsigned int shift;
- unsigned int mask;
- unsigned int iddq;
-
- const unsigned int *funcs;
- unsigned int num_funcs;
-};
-
-#define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
- { \
- .name = _name, \
- .offset = _offset, \
- .shift = _shift, \
- .mask = _mask, \
- .iddq = _iddq, \
- .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
- .funcs = tegra124_##_funcs##_functions, \
- }
-
-static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
- TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
- TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
- TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
- TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
- TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
- TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
- TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
- TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
- TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
- TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
- TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
- TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
-};
-
-struct tegra_xusb_phy_ops {
- int (*prepare)(struct tegra_xusb_phy *phy);
- int (*enable)(struct tegra_xusb_phy *phy);
- int (*disable)(struct tegra_xusb_phy *phy);
- int (*unprepare)(struct tegra_xusb_phy *phy);
-};
-
-struct tegra_xusb_phy {
- const struct tegra_xusb_phy_ops *ops;
-
- struct tegra_xusb_padctl *padctl;
-};
-
-struct tegra_xusb_padctl_pin {
- const struct tegra_xusb_padctl_lane *lane;
-
- unsigned int func;
- int iddq;
-};
-
-#define MAX_GROUPS 3
-#define MAX_PINS 6
-
-struct tegra_xusb_padctl_group {
- const char *name;
-
- const char *pins[MAX_PINS];
- unsigned int num_pins;
-
- const char *func;
- int iddq;
-};
-
-struct tegra_xusb_padctl_config {
- const char *name;
-
- struct tegra_xusb_padctl_group groups[MAX_GROUPS];
- unsigned int num_groups;
-};
-
-struct tegra_xusb_padctl {
- struct fdt_resource regs;
-
- unsigned int enable;
-
- struct tegra_xusb_phy phys[2];
-
- const struct tegra_xusb_padctl_lane *lanes;
- unsigned int num_lanes;
-
- const char *const *functions;
- unsigned int num_functions;
-
- struct tegra_xusb_padctl_config config;
-};
-
-static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
- unsigned long offset)
-{
- return readl(padctl->regs.start + offset);
-}
-
-static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
- u32 value, unsigned long offset)
-{
- writel(value, padctl->regs.start + offset);
-}
-
-static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
-{
- u32 value;
-
- if (padctl->enable++ > 0)
- return 0;
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- udelay(100);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- udelay(100);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- return 0;
-}
-
-static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
-{
- u32 value;
-
- if (padctl->enable == 0) {
- error("tegra-xusb-padctl: unbalanced enable/disable");
- return 0;
- }
-
- if (--padctl->enable > 0)
- return 0;
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- udelay(100);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- udelay(100);
-
- value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
- value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
- padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
-
- return 0;
-}
-
-static int phy_prepare(struct tegra_xusb_phy *phy)
-{
- return tegra_xusb_padctl_enable(phy->padctl);
-}
-
-static int phy_unprepare(struct tegra_xusb_phy *phy)
-{
- return tegra_xusb_padctl_disable(phy->padctl);
-}
-
-static int pcie_phy_enable(struct tegra_xusb_phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy->padctl;
- int err = -ETIMEDOUT;
- unsigned long start;
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
- value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
- XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
- XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
-
- start = get_timer(0);
-
- while (get_timer(start) < 50) {
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
- err = 0;
- break;
- }
- }
-
- return err;
-}
-
-static int pcie_phy_disable(struct tegra_xusb_phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy->padctl;
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
-
- return 0;
-}
-
-static int sata_phy_enable(struct tegra_xusb_phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy->padctl;
- int err = -ETIMEDOUT;
- unsigned long start;
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
- value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- start = get_timer(0);
-
- while (get_timer(start) < 50) {
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
- err = 0;
- break;
- }
- }
-
- return err;
-}
-
-static int sata_phy_disable(struct tegra_xusb_phy *phy)
-{
- struct tegra_xusb_padctl *padctl = phy->padctl;
- u32 value;
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
- value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
- value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
- value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
- padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
-
- return 0;
-}
-
-static const struct tegra_xusb_phy_ops pcie_phy_ops = {
- .prepare = phy_prepare,
- .enable = pcie_phy_enable,
- .disable = pcie_phy_disable,
- .unprepare = phy_unprepare,
-};
-
-static const struct tegra_xusb_phy_ops sata_phy_ops = {
- .prepare = phy_prepare,
- .enable = sata_phy_enable,
- .disable = sata_phy_disable,
- .unprepare = phy_unprepare,
-};
-
-static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
- .phys = {
- [0] = {
- .ops = &pcie_phy_ops,
- },
- [1] = {
- .ops = &sata_phy_ops,
- },
- },
-};
-
-static const struct tegra_xusb_padctl_lane *
-tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
-{
- unsigned int i;
-
- for (i = 0; i < padctl->num_lanes; i++)
- if (strcmp(name, padctl->lanes[i].name) == 0)
- return &padctl->lanes[i];
-
- return NULL;
-}
-
-static int
-tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
- struct tegra_xusb_padctl_group *group,
- const void *fdt, int node)
-{
- unsigned int i;
- int len, err;
-
- group->name = fdt_get_name(fdt, node, &len);
-
- len = fdt_count_strings(fdt, node, "nvidia,lanes");
- if (len < 0) {
- error("tegra-xusb-padctl: failed to parse \"nvidia,lanes\" property");
- return -EINVAL;
- }
-
- group->num_pins = len;
-
- for (i = 0; i < group->num_pins; i++) {
- err = fdt_get_string_index(fdt, node, "nvidia,lanes", i,
- &group->pins[i]);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to read string from \"nvidia,lanes\" property");
- return -EINVAL;
- }
- }
-
- group->num_pins = len;
-
- err = fdt_get_string(fdt, node, "nvidia,function", &group->func);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to parse \"nvidia,func\" property");
- return -EINVAL;
- }
-
- group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1);
-
- return 0;
-}
-
-static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
- const char *name)
-{
- unsigned int i;
-
- for (i = 0; i < padctl->num_functions; i++)
- if (strcmp(name, padctl->functions[i]) == 0)
- return i;
-
- return -ENOENT;
-}
-
-static int
-tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
- const struct tegra_xusb_padctl_lane *lane,
- const char *name)
-{
- unsigned int i;
- int func;
-
- func = tegra_xusb_padctl_find_function(padctl, name);
- if (func < 0)
- return func;
-
- for (i = 0; i < lane->num_funcs; i++)
- if (lane->funcs[i] == func)
- return i;
-
- return -ENOENT;
-}
-
-static int
-tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
- const struct tegra_xusb_padctl_group *group)
-{
- unsigned int i;
-
- for (i = 0; i < group->num_pins; i++) {
- const struct tegra_xusb_padctl_lane *lane;
- unsigned int func;
- u32 value;
-
- lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
- if (!lane) {
- error("tegra-xusb-padctl: no lane for pin %s",
- group->pins[i]);
- continue;
- }
-
- func = tegra_xusb_padctl_lane_find_function(padctl, lane,
- group->func);
- if (func < 0) {
- error("tegra-xusb-padctl: function %s invalid for lane %s: %d",
- group->func, lane->name, func);
- continue;
- }
-
- value = padctl_readl(padctl, lane->offset);
-
- /* set pin function */
- value &= ~(lane->mask << lane->shift);
- value |= func << lane->shift;
-
- /*
- * Set IDDQ if supported on the lane and specified in the
- * configuration.
- */
- if (lane->iddq > 0 && group->iddq >= 0) {
- if (group->iddq != 0)
- value &= ~(1 << lane->iddq);
- else
- value |= 1 << lane->iddq;
- }
-
- padctl_writel(padctl, value, lane->offset);
- }
-
- return 0;
-}
-
-static int
-tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
- struct tegra_xusb_padctl_config *config)
-{
- unsigned int i;
-
- for (i = 0; i < config->num_groups; i++) {
- const struct tegra_xusb_padctl_group *group;
- int err;
-
- group = &config->groups[i];
-
- err = tegra_xusb_padctl_group_apply(padctl, group);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to apply group %s: %d",
- group->name, err);
- continue;
- }
- }
-
- return 0;
-}
-
-static int
-tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
- struct tegra_xusb_padctl_config *config,
- const void *fdt, int node)
-{
- int subnode;
-
- config->name = fdt_get_name(fdt, node, NULL);
-
- fdt_for_each_subnode(fdt, subnode, node) {
- struct tegra_xusb_padctl_group *group;
- int err;
-
- group = &config->groups[config->num_groups];
-
- err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt,
- subnode);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to parse group %s",
- group->name);
- return err;
- }
-
- config->num_groups++;
- }
-
- return 0;
-}
-
-static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
- const void *fdt, int node)
-{
- int subnode, err;
-
- err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
- if (err < 0) {
- error("tegra-xusb-padctl: registers not found");
- return err;
- }
-
- fdt_for_each_subnode(fdt, subnode, node) {
- struct tegra_xusb_padctl_config *config = &padctl->config;
-
- err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
- subnode);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to parse entry %s: %d",
- config->name, err);
- continue;
- }
- }
-
- return 0;
-}
-
-static int process_nodes(const void *fdt, int nodes[], unsigned int count)
-{
- unsigned int i;
-
- for (i = 0; i < count; i++) {
- enum fdt_compat_id id;
- int err;
-
- if (!fdtdec_get_is_enabled(fdt, nodes[i]))
- continue;
-
- id = fdtdec_lookup(fdt, nodes[i]);
- switch (id) {
- case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
- break;
-
- default:
- error("tegra-xusb-padctl: unsupported compatible: %s",
- fdtdec_get_compatible(id));
- continue;
- }
-
- padctl->num_lanes = ARRAY_SIZE(tegra124_lanes);
- padctl->lanes = tegra124_lanes;
-
- padctl->num_functions = ARRAY_SIZE(tegra124_functions);
- padctl->functions = tegra124_functions;
-
- err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to parse DT: %d",
- err);
- continue;
- }
-
- /* deassert XUSB padctl reset */
- reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
-
- err = tegra_xusb_padctl_config_apply(padctl, &padctl->config);
- if (err < 0) {
- error("tegra-xusb-padctl: failed to apply pinmux: %d",
- err);
- continue;
- }
-
- /* only a single instance is supported */
- break;
- }
-
- return 0;
-}
-
-struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
-{
- struct tegra_xusb_phy *phy = NULL;
-
- switch (type) {
- case TEGRA_XUSB_PADCTL_PCIE:
- phy = &padctl->phys[0];
- phy->padctl = padctl;
- break;
-
- case TEGRA_XUSB_PADCTL_SATA:
- phy = &padctl->phys[1];
- phy->padctl = padctl;
- break;
- }
-
- return phy;
-}
-
-int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
-{
- if (phy && phy->ops && phy->ops->prepare)
- return phy->ops->prepare(phy);
-
- return phy ? -ENOSYS : -EINVAL;
-}
-
-int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
-{
- if (phy && phy->ops && phy->ops->enable)
- return phy->ops->enable(phy);
-
- return phy ? -ENOSYS : -EINVAL;
-}
-
-int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
-{
- if (phy && phy->ops && phy->ops->disable)
- return phy->ops->disable(phy);
-
- return phy ? -ENOSYS : -EINVAL;
-}
-
-int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
-{
- if (phy && phy->ops && phy->ops->unprepare)
- return phy->ops->unprepare(phy);
-
- return phy ? -ENOSYS : -EINVAL;
-}
-
-void tegra_xusb_padctl_init(const void *fdt)
-{
- int count, nodes[1];
-
- count = fdtdec_find_aliases_for_id(fdt, "padctl",
- COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
- nodes, ARRAY_SIZE(nodes));
- if (process_nodes(fdt, nodes, count))
- return;
-}
diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile
deleted file mode 100644
index 0e4b3fc..0000000
--- a/arch/arm/cpu/tegra20-common/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# The AVP is ARMv4T architecture so we must use special compiler
-# flags for any startup files it might use.
-CFLAGS_warmboot_avp.o += -march=armv4t
-
-obj-y += clock.o funcmux.o pinmux.o
-obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
-obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
-obj-$(CONFIG_TEGRA_PMU) += pmu.o
diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c
deleted file mode 100644
index 7b9e10c..0000000
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ /dev/null
@@ -1,687 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Tegra20 Clock control functions */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
-#include <div64.h>
-#include <fdtdec.h>
-
-/*
- * Clock types that we can use as a source. The Tegra20 has muxes for the
- * peripheral clocks, and in most cases there are four options for the clock
- * source. This gives us a clock 'type' and exploits what commonality exists
- * in the device.
- *
- * Letters are obvious, except for T which means CLK_M, and S which means the
- * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
- * datasheet) and PLL_M are different things. The former is the basic
- * clock supplied to the SOC from an external oscillator. The latter is the
- * memory clock PLL.
- *
- * See definitions in clock_id in the header file.
- */
-enum clock_type_id {
- CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
- CLOCK_TYPE_MCPA, /* and so on */
- CLOCK_TYPE_MCPT,
- CLOCK_TYPE_PCM,
- CLOCK_TYPE_PCMT,
- CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
- CLOCK_TYPE_PCXTS,
- CLOCK_TYPE_PDCT,
-
- CLOCK_TYPE_COUNT,
- CLOCK_TYPE_NONE = -1, /* invalid clock type */
-};
-
-enum {
- CLOCK_MAX_MUX = 4 /* number of source options for each clock */
-};
-
-/*
- * Clock source mux for each clock type. This just converts our enum into
- * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
- * is special as it has 5 sources. Since it also has a different number of
- * bits in its register for the source, we just handle it with a special
- * case in the code.
- */
-#define CLK(x) CLOCK_ID_ ## x
-static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
- { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
- { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
- { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
-};
-
-/*
- * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
- * not in the header file since it is for purely internal use - we want
- * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
- * confusion bewteen PERIPH_ID_... and PERIPHC_...
- *
- * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
- * confusing.
- *
- * Note to SOC vendors: perhaps define a unified numbering for peripherals and
- * use it for reset, clock enable, clock source/divider and even pinmuxing
- * if you can.
- */
-enum periphc_internal_id {
- /* 0x00 */
- PERIPHC_I2S1,
- PERIPHC_I2S2,
- PERIPHC_SPDIF_OUT,
- PERIPHC_SPDIF_IN,
- PERIPHC_PWM,
- PERIPHC_SPI1,
- PERIPHC_SPI2,
- PERIPHC_SPI3,
-
- /* 0x08 */
- PERIPHC_XIO,
- PERIPHC_I2C1,
- PERIPHC_DVC_I2C,
- PERIPHC_TWC,
- PERIPHC_0c,
- PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
- PERIPHC_DISP1,
- PERIPHC_DISP2,
-
- /* 0x10 */
- PERIPHC_CVE,
- PERIPHC_IDE0,
- PERIPHC_VI,
- PERIPHC_1c,
- PERIPHC_SDMMC1,
- PERIPHC_SDMMC2,
- PERIPHC_G3D,
- PERIPHC_G2D,
-
- /* 0x18 */
- PERIPHC_NDFLASH,
- PERIPHC_SDMMC4,
- PERIPHC_VFIR,
- PERIPHC_EPP,
- PERIPHC_MPE,
- PERIPHC_MIPI,
- PERIPHC_UART1,
- PERIPHC_UART2,
-
- /* 0x20 */
- PERIPHC_HOST1X,
- PERIPHC_21,
- PERIPHC_TVO,
- PERIPHC_HDMI,
- PERIPHC_24,
- PERIPHC_TVDAC,
- PERIPHC_I2C2,
- PERIPHC_EMC,
-
- /* 0x28 */
- PERIPHC_UART3,
- PERIPHC_29,
- PERIPHC_VI_SENSOR,
- PERIPHC_2b,
- PERIPHC_2c,
- PERIPHC_SPI4,
- PERIPHC_I2C3,
- PERIPHC_SDMMC3,
-
- /* 0x30 */
- PERIPHC_UART4,
- PERIPHC_UART5,
- PERIPHC_VDE,
- PERIPHC_OWR,
- PERIPHC_NOR,
- PERIPHC_CSITE,
-
- PERIPHC_COUNT,
-
- PERIPHC_NONE = -1,
-};
-
-/*
- * Clock type for each peripheral clock source. We put the name in each
- * record just so it is easy to match things up
- */
-#define TYPE(name, type) type
-static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
- /* 0x00 */
- TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
- TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
- TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
-
- /* 0x08 */
- TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
-
- /* 0x10 */
- TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
-
- /* 0x18 */
- TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
-
- /* 0x20 */
- TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
-
- /* 0x28 */
- TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
-
- /* 0x30 */
- TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
-};
-
-/*
- * This array translates a periph_id to a periphc_internal_id
- *
- * Not present/matched up:
- * uint vi_sensor; _VI_SENSOR_0, 0x1A8
- * SPDIF - which is both 0x08 and 0x0c
- *
- */
-#define NONE(name) (-1)
-#define OFFSET(name, value) PERIPHC_ ## name
-static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
- /* Low word: 31:0 */
- NONE(CPU),
- NONE(RESERVED1),
- NONE(RESERVED2),
- NONE(AC97),
- NONE(RTC),
- NONE(TMR),
- PERIPHC_UART1,
- PERIPHC_UART2, /* and vfir 0x68 */
-
- /* 0x08 */
- NONE(GPIO),
- PERIPHC_SDMMC2,
- NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
- PERIPHC_I2S1,
- PERIPHC_I2C1,
- PERIPHC_NDFLASH,
- PERIPHC_SDMMC1,
- PERIPHC_SDMMC4,
-
- /* 0x10 */
- PERIPHC_TWC,
- PERIPHC_PWM,
- PERIPHC_I2S2,
- PERIPHC_EPP,
- PERIPHC_VI,
- PERIPHC_G2D,
- NONE(USBD),
- NONE(ISP),
-
- /* 0x18 */
- PERIPHC_G3D,
- PERIPHC_IDE0,
- PERIPHC_DISP2,
- PERIPHC_DISP1,
- PERIPHC_HOST1X,
- NONE(VCP),
- NONE(RESERVED30),
- NONE(CACHE2),
-
- /* Middle word: 63:32 */
- NONE(MEM),
- NONE(AHBDMA),
- NONE(APBDMA),
- NONE(RESERVED35),
- NONE(KBC),
- NONE(STAT_MON),
- NONE(PMC),
- NONE(FUSE),
-
- /* 0x28 */
- NONE(KFUSE),
- NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
- PERIPHC_NOR,
- PERIPHC_SPI1,
- PERIPHC_SPI2,
- PERIPHC_XIO,
- PERIPHC_SPI3,
- PERIPHC_DVC_I2C,
-
- /* 0x30 */
- NONE(DSI),
- PERIPHC_TVO, /* also CVE 0x40 */
- PERIPHC_MIPI,
- PERIPHC_HDMI,
- PERIPHC_CSITE,
- PERIPHC_TVDAC,
- PERIPHC_I2C2,
- PERIPHC_UART3,
-
- /* 0x38 */
- NONE(RESERVED56),
- PERIPHC_EMC,
- NONE(USB2),
- NONE(USB3),
- PERIPHC_MPE,
- PERIPHC_VDE,
- NONE(BSEA),
- NONE(BSEV),
-
- /* Upper word 95:64 */
- NONE(SPEEDO),
- PERIPHC_UART4,
- PERIPHC_UART5,
- PERIPHC_I2C3,
- PERIPHC_SPI4,
- PERIPHC_SDMMC3,
- NONE(PCIE),
- PERIPHC_OWR,
-
- /* 0x48 */
- NONE(AFI),
- NONE(CORESIGHT),
- NONE(PCIEXCLK),
- NONE(AVPUCQ),
- NONE(RESERVED76),
- NONE(RESERVED77),
- NONE(RESERVED78),
- NONE(RESERVED79),
-
- /* 0x50 */
- NONE(RESERVED80),
- NONE(RESERVED81),
- NONE(RESERVED82),
- NONE(RESERVED83),
- NONE(IRAMA),
- NONE(IRAMB),
- NONE(IRAMC),
- NONE(IRAMD),
-
- /* 0x58 */
- NONE(CRAM2),
-};
-
-/*
- * Get the oscillator frequency, from the corresponding hardware configuration
- * field. T20 has 4 frequencies that it supports.
- */
-enum clock_osc_freq clock_get_osc_freq(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- reg = readl(&clkrst->crc_osc_ctrl);
- return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
-}
-
-/* Returns a pointer to the clock source register for a peripheral */
-u32 *get_periph_source_reg(enum periph_id periph_id)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- enum periphc_internal_id internal_id;
-
- assert(clock_periph_id_isvalid(periph_id));
- internal_id = periph_id_to_internal_id[periph_id];
- assert(internal_id != -1);
- return &clkrst->crc_clk_src[internal_id];
-}
-
-/**
- * Given a peripheral ID and the required source clock, this returns which
- * value should be programmed into the source mux for that peripheral.
- *
- * There is special code here to handle the one source type with 5 sources.
- *
- * @param periph_id peripheral to start
- * @param source PLL id of required parent clock
- * @param mux_bits Set to number of bits in mux register: 2 or 4
- * @param divider_bits Set to number of divider bits (8 or 16)
- * @return mux value (0-4, or -1 if not found)
- */
-int get_periph_clock_source(enum periph_id periph_id,
- enum clock_id parent, int *mux_bits, int *divider_bits)
-{
- enum clock_type_id type;
- enum periphc_internal_id internal_id;
- int mux;
-
- assert(clock_periph_id_isvalid(periph_id));
-
- internal_id = periph_id_to_internal_id[periph_id];
- assert(periphc_internal_id_isvalid(internal_id));
-
- type = clock_periph_type[internal_id];
- assert(clock_type_id_isvalid(type));
-
- /*
- * Special cases here for the clock with a 4-bit source mux and I2C
- * with its 16-bit divisor
- */
- if (type == CLOCK_TYPE_PCXTS)
- *mux_bits = MASK_BITS_31_28;
- else
- *mux_bits = MASK_BITS_31_30;
- if (type == CLOCK_TYPE_PCMT16)
- *divider_bits = 16;
- else
- *divider_bits = 8;
-
- for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
- if (clock_source[type][mux] == parent)
- return mux;
-
- /*
- * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
- * which is not in our table. If not, then they are asking for a
- * source which this peripheral can't access through its mux.
- */
- assert(type == CLOCK_TYPE_PCXTS);
- assert(parent == CLOCK_ID_SFROM32KHZ);
- if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
- return 4; /* mux value for this clock */
-
- /* if we get here, either us or the caller has made a mistake */
- printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
- parent);
- return -1;
-}
-
-void clock_set_enable(enum periph_id periph_id, int enable)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
- u32 reg;
-
- /* Enable/disable the clock to this peripheral */
- assert(clock_periph_id_isvalid(periph_id));
- reg = readl(clk);
- if (enable)
- reg |= PERIPH_MASK(periph_id);
- else
- reg &= ~PERIPH_MASK(periph_id);
- writel(reg, clk);
-}
-
-void reset_set_enable(enum periph_id periph_id, int enable)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
- u32 reg;
-
- /* Enable/disable reset to the peripheral */
- assert(clock_periph_id_isvalid(periph_id));
- reg = readl(reset);
- if (enable)
- reg |= PERIPH_MASK(periph_id);
- else
- reg &= ~PERIPH_MASK(periph_id);
- writel(reg, reset);
-}
-
-#ifdef CONFIG_OF_CONTROL
-/*
- * Convert a device tree clock ID to our peripheral ID. They are mostly
- * the same but we are very cautious so we check that a valid clock ID is
- * provided.
- *
- * @param clk_id Clock ID according to tegra20 device tree binding
- * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
- */
-enum periph_id clk_id_to_periph_id(int clk_id)
-{
- if (clk_id > PERIPH_ID_COUNT)
- return PERIPH_ID_NONE;
-
- switch (clk_id) {
- case PERIPH_ID_RESERVED1:
- case PERIPH_ID_RESERVED2:
- case PERIPH_ID_RESERVED30:
- case PERIPH_ID_RESERVED35:
- case PERIPH_ID_RESERVED56:
- case PERIPH_ID_PCIEXCLK:
- case PERIPH_ID_RESERVED76:
- case PERIPH_ID_RESERVED77:
- case PERIPH_ID_RESERVED78:
- case PERIPH_ID_RESERVED79:
- case PERIPH_ID_RESERVED80:
- case PERIPH_ID_RESERVED81:
- case PERIPH_ID_RESERVED82:
- case PERIPH_ID_RESERVED83:
- case PERIPH_ID_RESERVED91:
- return PERIPH_ID_NONE;
- default:
- return clk_id;
- }
-}
-#endif /* CONFIG_OF_CONTROL */
-
-void clock_early_init(void)
-{
- /*
- * PLLP output frequency set to 216MHz
- * PLLC output frequency set to 600Mhz
- *
- * TODO: Can we calculate these values instead of hard-coding?
- */
- switch (clock_get_osc_freq()) {
- case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
- break;
-
- case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
- break;
-
- case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
- clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
- clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
- break;
- case CLOCK_OSC_FREQ_19_2:
- default:
- /*
- * These are not supported. It is too early to print a
- * message and the UART likely won't work anyway due to the
- * oscillator being wrong.
- */
- break;
- }
-}
-
-void arch_timer_init(void)
-{
-}
-
-#define PMC_SATA_PWRGT 0x1ac
-#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
-#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
-
-#define PLLE_SS_CNTL 0x68
-#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
-#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
-#define PLLE_SS_CNTL_SSCBYP (1 << 12)
-#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
-#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
-#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
-
-#define PLLE_BASE 0x0e8
-#define PLLE_BASE_ENABLE_CML (1 << 31)
-#define PLLE_BASE_ENABLE (1 << 30)
-#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
-#define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
-#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
-#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
-
-#define PLLE_MISC 0x0ec
-#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
-#define PLLE_MISC_PLL_READY (1 << 15)
-#define PLLE_MISC_LOCK (1 << 11)
-#define PLLE_MISC_LOCK_ENABLE (1 << 9)
-#define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
-
-static int tegra_plle_train(void)
-{
- unsigned int timeout = 2000;
- unsigned long value;
-
- value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
- value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
- writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
-
- value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
- value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
- writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
-
- value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
- value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
- writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
-
- do {
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- if (value & PLLE_MISC_PLL_READY)
- break;
-
- udelay(100);
- } while (--timeout);
-
- if (timeout == 0) {
- error("timeout waiting for PLLE to become ready");
- return -ETIMEDOUT;
- }
-
- return 0;
-}
-
-int tegra_plle_enable(void)
-{
- unsigned int timeout = 1000;
- u32 value;
- int err;
-
- /* disable PLLE clock */
- value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
- value &= ~PLLE_BASE_ENABLE_CML;
- value &= ~PLLE_BASE_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- /* clear lock enable and setup field */
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- value &= ~PLLE_MISC_LOCK_ENABLE;
- value &= ~PLLE_MISC_SETUP_BASE(0xffff);
- value &= ~PLLE_MISC_SETUP_EXT(0x3);
- writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- if ((value & PLLE_MISC_PLL_READY) == 0) {
- err = tegra_plle_train();
- if (err < 0) {
- error("failed to train PLLE: %d", err);
- return err;
- }
- }
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- value |= PLLE_MISC_SETUP_BASE(0x7);
- value |= PLLE_MISC_LOCK_ENABLE;
- value |= PLLE_MISC_SETUP_EXT(0);
- writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
- PLLE_SS_CNTL_BYPASS_SS;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
- value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- do {
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- if (value & PLLE_MISC_LOCK)
- break;
-
- udelay(2);
- } while (--timeout);
-
- if (timeout == 0) {
- error("timeout waiting for PLLE to lock");
- return -ETIMEDOUT;
- }
-
- udelay(50);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
- value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
-
- value &= ~PLLE_SS_CNTL_SSCINC(0xff);
- value |= PLLE_SS_CNTL_SSCINC(0x01);
-
- value &= ~PLLE_SS_CNTL_SSCBYP;
- value &= ~PLLE_SS_CNTL_INTERP_RESET;
- value &= ~PLLE_SS_CNTL_BYPASS_SS;
-
- value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
- value |= PLLE_SS_CNTL_SSCMAX(0x24);
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- return 0;
-}
diff --git a/arch/arm/cpu/tegra20-common/crypto.c b/arch/arm/cpu/tegra20-common/crypto.c
deleted file mode 100644
index ec95d7c..0000000
--- a/arch/arm/cpu/tegra20-common/crypto.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/errno.h>
-#include "crypto.h"
-#include "aes.h"
-
-static u8 zero_key[16];
-
-#define AES_CMAC_CONST_RB 0x87 /* from RFC 4493, Figure 2.2 */
-
-enum security_op {
- SECURITY_SIGN = 1 << 0, /* Sign the data */
- SECURITY_ENCRYPT = 1 << 1, /* Encrypt the data */
-};
-
-/**
- * Shift a vector left by one bit
- *
- * \param in Input vector
- * \param out Output vector
- * \param size Length of vector in bytes
- */
-static void left_shift_vector(u8 *in, u8 *out, int size)
-{
- int carry = 0;
- int i;
-
- for (i = size - 1; i >= 0; i--) {
- out[i] = (in[i] << 1) | carry;
- carry = in[i] >> 7; /* get most significant bit */
- }
-}
-
-/**
- * Sign a block of data, putting the result into dst.
- *
- * \param key Input AES key, length AES_KEY_LENGTH
- * \param key_schedule Expanded key to use
- * \param src Source data of length 'num_aes_blocks' blocks
- * \param dst Destination buffer, length AES_KEY_LENGTH
- * \param num_aes_blocks Number of AES blocks to encrypt
- */
-static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst,
- u32 num_aes_blocks)
-{
- u8 tmp_data[AES_KEY_LENGTH];
- u8 left[AES_KEY_LENGTH];
- u8 k1[AES_KEY_LENGTH];
- u8 *cbc_chain_data;
- unsigned i;
-
- cbc_chain_data = zero_key; /* Convenient array of 0's for IV */
-
- /* compute K1 constant needed by AES-CMAC calculation */
- for (i = 0; i < AES_KEY_LENGTH; i++)
- tmp_data[i] = 0;
-
- aes_cbc_encrypt_blocks(key_schedule, tmp_data, left, 1);
-
- left_shift_vector(left, k1, sizeof(left));
-
- if ((left[0] >> 7) != 0) /* get MSB of L */
- k1[AES_KEY_LENGTH-1] ^= AES_CMAC_CONST_RB;
-
- /* compute the AES-CMAC value */
- for (i = 0; i < num_aes_blocks; i++) {
- /* Apply the chain data */
- aes_apply_cbc_chain_data(cbc_chain_data, src, tmp_data);
-
- /* for the final block, XOR K1 into the IV */
- if (i == num_aes_blocks - 1)
- aes_apply_cbc_chain_data(tmp_data, k1, tmp_data);
-
- /* encrypt the AES block */
- aes_encrypt(tmp_data, key_schedule, dst);
-
- debug("sign_obj: block %d of %d\n", i, num_aes_blocks);
-
- /* Update pointers for next loop. */
- cbc_chain_data = dst;
- src += AES_KEY_LENGTH;
- }
-}
-
-/**
- * Encrypt and sign a block of data (depending on security mode).
- *
- * \param key Input AES key, length AES_KEY_LENGTH
- * \param oper Security operations mask to perform (enum security_op)
- * \param src Source data
- * \param length Size of source data
- * \param sig_dst Destination address for signature, AES_KEY_LENGTH bytes
- */
-static int encrypt_and_sign(u8 *key, enum security_op oper, u8 *src,
- u32 length, u8 *sig_dst)
-{
- u32 num_aes_blocks;
- u8 key_schedule[AES_EXPAND_KEY_LENGTH];
-
- debug("encrypt_and_sign: length = %d\n", length);
-
- /*
- * The only need for a key is for signing/checksum purposes, so
- * if not encrypting, expand a key of 0s.
- */
- aes_expand_key(oper & SECURITY_ENCRYPT ? key : zero_key, key_schedule);
-
- num_aes_blocks = (length + AES_KEY_LENGTH - 1) / AES_KEY_LENGTH;
-
- if (oper & SECURITY_ENCRYPT) {
- /* Perform this in place, resulting in src being encrypted. */
- debug("encrypt_and_sign: begin encryption\n");
- aes_cbc_encrypt_blocks(key_schedule, src, src, num_aes_blocks);
- debug("encrypt_and_sign: end encryption\n");
- }
-
- if (oper & SECURITY_SIGN) {
- /* encrypt the data, overwriting the result in signature. */
- debug("encrypt_and_sign: begin signing\n");
- sign_object(key, key_schedule, src, sig_dst, num_aes_blocks);
- debug("encrypt_and_sign: end signing\n");
- }
-
- return 0;
-}
-
-int sign_data_block(u8 *source, unsigned length, u8 *signature)
-{
- return encrypt_and_sign(zero_key, SECURITY_SIGN, source,
- length, signature);
-}
diff --git a/arch/arm/cpu/tegra20-common/crypto.h b/arch/arm/cpu/tegra20-common/crypto.h
deleted file mode 100644
index f59b927..0000000
--- a/arch/arm/cpu/tegra20-common/crypto.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _CRYPTO_H_
-#define _CRYPTO_H_
-
-/**
- * Sign a block of data
- *
- * \param source Source data
- * \param length Size of source data
- * \param signature Destination address for signature, AES_KEY_LENGTH bytes
- */
-int sign_data_block(u8 *source, unsigned length, u8 *signature);
-
-#endif /* #ifndef _CRYPTO_H_ */
diff --git a/arch/arm/cpu/tegra20-common/emc.c b/arch/arm/cpu/tegra20-common/emc.c
deleted file mode 100644
index ed2462a..0000000
--- a/arch/arm/cpu/tegra20-common/emc.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <asm/io.h>
-#include <asm/arch-tegra/ap.h>
-#include <asm/arch-tegra/apb_misc.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/emc.h>
-#include <asm/arch/tegra.h>
-
-/*
- * The EMC registers have shadow registers. When the EMC clock is updated
- * in the clock controller, the shadow registers are copied to the active
- * registers, allowing glitchless memory bus frequency changes.
- * This function updates the shadow registers for a new clock frequency,
- * and relies on the clock lock on the emc clock to avoid races between
- * multiple frequency changes
- */
-
-/*
- * This table defines the ordering of the registers provided to
- * tegra_set_mmc()
- * TODO: Convert to fdt version once available
- */
-static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
- 0x2c, /* RC */
- 0x30, /* RFC */
- 0x34, /* RAS */
- 0x38, /* RP */
- 0x3c, /* R2W */
- 0x40, /* W2R */
- 0x44, /* R2P */
- 0x48, /* W2P */
- 0x4c, /* RD_RCD */
- 0x50, /* WR_RCD */
- 0x54, /* RRD */
- 0x58, /* REXT */
- 0x5c, /* WDV */
- 0x60, /* QUSE */
- 0x64, /* QRST */
- 0x68, /* QSAFE */
- 0x6c, /* RDV */
- 0x70, /* REFRESH */
- 0x74, /* BURST_REFRESH_NUM */
- 0x78, /* PDEX2WR */
- 0x7c, /* PDEX2RD */
- 0x80, /* PCHG2PDEN */
- 0x84, /* ACT2PDEN */
- 0x88, /* AR2PDEN */
- 0x8c, /* RW2PDEN */
- 0x90, /* TXSR */
- 0x94, /* TCKE */
- 0x98, /* TFAW */
- 0x9c, /* TRPAB */
- 0xa0, /* TCLKSTABLE */
- 0xa4, /* TCLKSTOP */
- 0xa8, /* TREFBW */
- 0xac, /* QUSE_EXTRA */
- 0x114, /* FBIO_CFG6 */
- 0xb0, /* ODT_WRITE */
- 0xb4, /* ODT_READ */
- 0x104, /* FBIO_CFG5 */
- 0x2bc, /* CFG_DIG_DLL */
- 0x2c0, /* DLL_XFORM_DQS */
- 0x2c4, /* DLL_XFORM_QUSE */
- 0x2e0, /* ZCAL_REF_CNT */
- 0x2e4, /* ZCAL_WAIT_CNT */
- 0x2a8, /* AUTO_CAL_INTERVAL */
- 0x2d0, /* CFG_CLKTRIM_0 */
- 0x2d4, /* CFG_CLKTRIM_1 */
- 0x2d8, /* CFG_CLKTRIM_2 */
-};
-
-struct emc_ctlr *emc_get_controller(const void *blob)
-{
- fdt_addr_t addr;
- int node;
-
- node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
- if (node > 0) {
- addr = fdtdec_get_addr(blob, node, "reg");
- if (addr != FDT_ADDR_T_NONE)
- return (struct emc_ctlr *)addr;
- }
- return NULL;
-}
-
-/* Error codes we use */
-enum {
- ERR_NO_EMC_NODE = -10,
- ERR_NO_EMC_REG,
- ERR_NO_FREQ,
- ERR_FREQ_NOT_FOUND,
- ERR_BAD_REGS,
- ERR_NO_RAM_CODE,
- ERR_RAM_CODE_NOT_FOUND,
-};
-
-/**
- * Find EMC tables for the given ram code.
- *
- * The tegra EMC binding has two options, one using the ram code and one not.
- * We detect which is in use by looking for the nvidia,use-ram-code property.
- * If this is not present, then the EMC tables are directly below 'node',
- * otherwise we select the correct emc-tables subnode based on the 'ram_code'
- * value.
- *
- * @param blob Device tree blob
- * @param node EMC node (nvidia,tegra20-emc compatible string)
- * @param ram_code RAM code to select (0-3, or -1 if unknown)
- * @return 0 if ok, otherwise a -ve ERR_ code (see enum above)
- */
-static int find_emc_tables(const void *blob, int node, int ram_code)
-{
- int need_ram_code;
- int depth;
- int offset;
-
- /* If we are using RAM codes, scan through the tables for our code */
- need_ram_code = fdtdec_get_bool(blob, node, "nvidia,use-ram-code");
- if (!need_ram_code)
- return node;
- if (ram_code == -1) {
- debug("%s: RAM code required but not supplied\n", __func__);
- return ERR_NO_RAM_CODE;
- }
-
- offset = node;
- depth = 0;
- do {
- /*
- * Sadly there is no compatible string so we cannot use
- * fdtdec_next_compatible_subnode().
- */
- offset = fdt_next_node(blob, offset, &depth);
- if (depth <= 0)
- break;
-
- /* Make sure this is a direct subnode */
- if (depth != 1)
- continue;
- if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL)))
- continue;
-
- if (fdtdec_get_int(blob, offset, "nvidia,ram-code", -1)
- == ram_code)
- return offset;
- } while (1);
-
- debug("%s: Could not find tables for RAM code %d\n", __func__,
- ram_code);
- return ERR_RAM_CODE_NOT_FOUND;
-}
-
-/**
- * Decode the EMC node of the device tree, returning a pointer to the emc
- * controller and the table to be used for the given rate.
- *
- * @param blob Device tree blob
- * @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
- * @param emcp Returns address of EMC controller registers
- * @param tablep Returns pointer to table to program into EMC. There are
- * TEGRA_EMC_NUM_REGS entries, destined for offsets as per the
- * emc_reg_addr array.
- * @return 0 if ok, otherwise a -ve error code which will allow someone to
- * figure out roughly what went wrong by looking at this code.
- */
-static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
- const u32 **tablep)
-{
- struct apb_misc_pp_ctlr *pp =
- (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
- int ram_code;
- int depth;
- int node;
-
- ram_code = (readl(&pp->strapping_opt_a) & RAM_CODE_MASK)
- >> RAM_CODE_SHIFT;
- /*
- * The EMC clock rate is twice the bus rate, and the bus rate is
- * measured in kHz
- */
- rate = rate / 2 / 1000;
-
- node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
- if (node < 0) {
- debug("%s: No EMC node found in FDT\n", __func__);
- return ERR_NO_EMC_NODE;
- }
- *emcp = (struct emc_ctlr *)fdtdec_get_addr(blob, node, "reg");
- if (*emcp == (struct emc_ctlr *)FDT_ADDR_T_NONE) {
- debug("%s: No EMC node reg property\n", __func__);
- return ERR_NO_EMC_REG;
- }
-
- /* Work out the parent node which contains our EMC tables */
- node = find_emc_tables(blob, node, ram_code & 3);
- if (node < 0)
- return node;
-
- depth = 0;
- for (;;) {
- int node_rate;
-
- node = fdtdec_next_compatible_subnode(blob, node,
- COMPAT_NVIDIA_TEGRA20_EMC_TABLE, &depth);
- if (node < 0)
- break;
- node_rate = fdtdec_get_int(blob, node, "clock-frequency", -1);
- if (node_rate == -1) {
- debug("%s: Missing clock-frequency\n", __func__);
- return ERR_NO_FREQ; /* we expect this property */
- }
-
- if (node_rate == rate)
- break;
- }
- if (node < 0) {
- debug("%s: No node found for clock frequency %d\n", __func__,
- rate);
- return ERR_FREQ_NOT_FOUND;
- }
-
- *tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers",
- TEGRA_EMC_NUM_REGS);
- if (!*tablep) {
- debug("%s: node '%s' array missing / wrong size\n", __func__,
- fdt_get_name(blob, node, NULL));
- return ERR_BAD_REGS;
- }
-
- /* All seems well */
- return 0;
-}
-
-int tegra_set_emc(const void *blob, unsigned rate)
-{
- struct emc_ctlr *emc;
- const u32 *table = NULL;
- int err, i;
-
- err = decode_emc(blob, rate, &emc, &table);
- if (err) {
- debug("Warning: no valid EMC (%d), memory timings unset\n",
- err);
- return err;
- }
-
- debug("%s: Table found, setting EMC values as follows:\n", __func__);
- for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) {
- u32 value = fdt32_to_cpu(table[i]);
- u32 addr = (uintptr_t)emc + emc_reg_addr[i];
-
- debug(" %#x: %#x\n", addr, value);
- writel(value, addr);
- }
-
- /* trigger emc with new settings */
- clock_adjust_periph_pll_div(PERIPH_ID_EMC, CLOCK_ID_MEMORY,
- clock_get_rate(CLOCK_ID_MEMORY), NULL);
- debug("EMC clock set to %lu\n",
- clock_get_periph_rate(PERIPH_ID_EMC, CLOCK_ID_MEMORY));
-
- return 0;
-}
diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c
deleted file mode 100644
index 0df4a07..0000000
--- a/arch/arm/cpu/tegra20-common/funcmux.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Tegra20 high-level function multiplexing */
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-
-/*
- * The PINMUX macro is used to set up pinmux tables.
- */
-#define PINMUX(grp, mux, pupd, tri) \
- {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
-
-static const struct pmux_pingrp_config disp1_default[] = {
- PINMUX(LDI, DISPA, NORMAL, NORMAL),
- PINMUX(LHP0, DISPA, NORMAL, NORMAL),
- PINMUX(LHP1, DISPA, NORMAL, NORMAL),
- PINMUX(LHP2, DISPA, NORMAL, NORMAL),
- PINMUX(LHS, DISPA, NORMAL, NORMAL),
- PINMUX(LM0, RSVD4, NORMAL, NORMAL),
- PINMUX(LPP, DISPA, NORMAL, NORMAL),
- PINMUX(LPW0, DISPA, NORMAL, NORMAL),
- PINMUX(LPW2, DISPA, NORMAL, NORMAL),
- PINMUX(LSC0, DISPA, NORMAL, NORMAL),
- PINMUX(LSPI, DISPA, NORMAL, NORMAL),
- PINMUX(LVP1, DISPA, NORMAL, NORMAL),
- PINMUX(LVS, DISPA, NORMAL, NORMAL),
- PINMUX(SLXD, SPDIF, NORMAL, NORMAL),
-};
-
-
-int funcmux_select(enum periph_id id, int config)
-{
- int bad_config = config != FUNCMUX_DEFAULT;
-
- switch (id) {
- case PERIPH_ID_UART1:
- switch (config) {
- case FUNCMUX_UART1_IRRX_IRTX:
- pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PMUX_PINGRP_IRRX);
- pinmux_tristate_disable(PMUX_PINGRP_IRTX);
- break;
- case FUNCMUX_UART1_UAA_UAB:
- pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PMUX_PINGRP_UAA);
- pinmux_tristate_disable(PMUX_PINGRP_UAB);
- bad_config = 0;
- break;
- case FUNCMUX_UART1_GPU:
- pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PMUX_PINGRP_GPU);
- bad_config = 0;
- break;
- case FUNCMUX_UART1_SDIO1:
- pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
- bad_config = 0;
- break;
- }
- if (!bad_config) {
- /*
- * Tegra appears to boot with function UARTA pre-
- * selected on mux group SDB. If two mux groups are
- * both set to the same function, it's unclear which
- * group's pins drive the RX signals into the HW.
- * For UARTA, SDB certainly overrides group IRTX in
- * practice. To solve this, configure some alternative
- * function on SDB to avoid the conflict. Also, tri-
- * state the group to avoid driving any signal onto it
- * until we know what's connected.
- */
- pinmux_tristate_enable(PMUX_PINGRP_SDB);
- pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
- }
- break;
-
- case PERIPH_ID_UART2:
- if (config == FUNCMUX_UART2_UAD) {
- pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB);
- pinmux_tristate_disable(PMUX_PINGRP_UAD);
- }
- break;
-
- case PERIPH_ID_UART4:
- if (config == FUNCMUX_UART4_GMC) {
- pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD);
- pinmux_tristate_disable(PMUX_PINGRP_GMC);
- }
- break;
-
- case PERIPH_ID_DVC_I2C:
- /* there is only one selection, pinmux_config is ignored */
- if (config == FUNCMUX_DVC_I2CP) {
- pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C);
- pinmux_tristate_disable(PMUX_PINGRP_I2CP);
- }
- break;
-
- case PERIPH_ID_I2C1:
- /* support pinmux_config of 0 for now, */
- if (config == FUNCMUX_I2C1_RM) {
- pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C);
- pinmux_tristate_disable(PMUX_PINGRP_RM);
- }
- break;
- case PERIPH_ID_I2C2: /* I2C2 */
- switch (config) {
- case FUNCMUX_I2C2_DDC: /* DDC pin group, select I2C2 */
- pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2);
- /* PTA to HDMI */
- pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI);
- pinmux_tristate_disable(PMUX_PINGRP_DDC);
- break;
- case FUNCMUX_I2C2_PTA: /* PTA pin group, select I2C2 */
- pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2);
- /* set DDC_SEL to RSVDx (RSVD2 works for now) */
- pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2);
- pinmux_tristate_disable(PMUX_PINGRP_PTA);
- bad_config = 0;
- break;
- }
- break;
- case PERIPH_ID_I2C3: /* I2C3 */
- /* support pinmux_config of 0 for now */
- if (config == FUNCMUX_I2C3_DTF) {
- pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3);
- pinmux_tristate_disable(PMUX_PINGRP_DTF);
- }
- break;
-
- case PERIPH_ID_SDMMC1:
- if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
- pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
- pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
- }
- break;
-
- case PERIPH_ID_SDMMC2:
- if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
- pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2);
- pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2);
-
- pinmux_tristate_disable(PMUX_PINGRP_DTA);
- pinmux_tristate_disable(PMUX_PINGRP_DTD);
- }
- break;
-
- case PERIPH_ID_SDMMC3:
- switch (config) {
- case FUNCMUX_SDMMC3_SDB_SLXA_8BIT:
- pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3);
- pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3);
- pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3);
- pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3);
-
- pinmux_tristate_disable(PMUX_PINGRP_SLXA);
- pinmux_tristate_disable(PMUX_PINGRP_SLXC);
- pinmux_tristate_disable(PMUX_PINGRP_SLXD);
- pinmux_tristate_disable(PMUX_PINGRP_SLXK);
- /* fall through */
-
- case FUNCMUX_SDMMC3_SDB_4BIT:
- pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
- pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3);
- pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3);
-
- pinmux_tristate_disable(PMUX_PINGRP_SDB);
- pinmux_tristate_disable(PMUX_PINGRP_SDC);
- pinmux_tristate_disable(PMUX_PINGRP_SDD);
- bad_config = 0;
- break;
- }
- break;
-
- case PERIPH_ID_SDMMC4:
- switch (config) {
- case FUNCMUX_SDMMC4_ATC_ATD_8BIT:
- pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4);
- pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4);
-
- pinmux_tristate_disable(PMUX_PINGRP_ATC);
- pinmux_tristate_disable(PMUX_PINGRP_ATD);
- break;
-
- case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT:
- pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
- pinmux_tristate_disable(PMUX_PINGRP_GME);
- /* fall through */
-
- case FUNCMUX_SDMMC4_ATB_GMA_4_BIT:
- pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
- pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
-
- pinmux_tristate_disable(PMUX_PINGRP_ATB);
- pinmux_tristate_disable(PMUX_PINGRP_GMA);
- bad_config = 0;
- break;
- }
- break;
-
- case PERIPH_ID_KBC:
- if (config == FUNCMUX_DEFAULT) {
- enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA,
- PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC,
- PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE,
- PMUX_PINGRP_KBCF};
- int i;
-
- for (i = 0; i < ARRAY_SIZE(grp); i++) {
- pinmux_tristate_disable(grp[i]);
- pinmux_set_func(grp[i], PMUX_FUNC_KBC);
- pinmux_set_pullupdown(grp[i], PMUX_PULL_UP);
- }
- }
- break;
-
- case PERIPH_ID_USB2:
- if (config == FUNCMUX_USB2_ULPI) {
- pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI);
- pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI);
- pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI);
-
- pinmux_tristate_disable(PMUX_PINGRP_UAA);
- pinmux_tristate_disable(PMUX_PINGRP_UAB);
- pinmux_tristate_disable(PMUX_PINGRP_UDA);
- }
- break;
-
- case PERIPH_ID_SPI1:
- if (config == FUNCMUX_SPI1_GMC_GMD) {
- pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
- pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
-
- pinmux_tristate_disable(PMUX_PINGRP_GMC);
- pinmux_tristate_disable(PMUX_PINGRP_GMD);
- }
- break;
-
- case PERIPH_ID_NDFLASH:
- switch (config) {
- case FUNCMUX_NDFLASH_ATC:
- pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND);
- pinmux_tristate_disable(PMUX_PINGRP_ATC);
- break;
- case FUNCMUX_NDFLASH_KBC_8_BIT:
- pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND);
- pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND);
- pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND);
- pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND);
- pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND);
-
- pinmux_tristate_disable(PMUX_PINGRP_KBCA);
- pinmux_tristate_disable(PMUX_PINGRP_KBCC);
- pinmux_tristate_disable(PMUX_PINGRP_KBCD);
- pinmux_tristate_disable(PMUX_PINGRP_KBCE);
- pinmux_tristate_disable(PMUX_PINGRP_KBCF);
-
- bad_config = 0;
- break;
- }
- break;
- case PERIPH_ID_DISP1:
- if (config == FUNCMUX_DEFAULT) {
- int i;
-
- for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) {
- pinmux_set_func(i, PMUX_FUNC_DISPA);
- pinmux_tristate_disable(i);
- pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
- }
- pinmux_config_pingrp_table(disp1_default,
- ARRAY_SIZE(disp1_default));
- }
- break;
-
- default:
- debug("%s: invalid periph_id %d", __func__, id);
- return -1;
- }
-
- if (bad_config) {
- debug("%s: invalid config %d for periph_id %d", __func__,
- config, id);
- return -1;
- }
-
- return 0;
-}
diff --git a/arch/arm/cpu/tegra20-common/pinmux.c b/arch/arm/cpu/tegra20-common/pinmux.c
deleted file mode 100644
index e484f99..0000000
--- a/arch/arm/cpu/tegra20-common/pinmux.c
+++ /dev/null
@@ -1,425 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* Tegra20 pin multiplexing functions */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-/*
- * This defines the order of the pin mux control bits in the registers. For
- * some reason there is no correspendence between the tristate, pin mux and
- * pullup/pulldown registers.
- */
-enum pmux_ctlid {
- /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
- MUXCTL_UAA,
- MUXCTL_UAB,
- MUXCTL_UAC,
- MUXCTL_UAD,
- MUXCTL_UDA,
- MUXCTL_RESERVED5,
- MUXCTL_ATE,
- MUXCTL_RM,
-
- MUXCTL_ATB,
- MUXCTL_RESERVED9,
- MUXCTL_ATD,
- MUXCTL_ATC,
- MUXCTL_ATA,
- MUXCTL_KBCF,
- MUXCTL_KBCE,
- MUXCTL_SDMMC1,
-
- /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
- MUXCTL_GMA,
- MUXCTL_GMC,
- MUXCTL_HDINT,
- MUXCTL_SLXA,
- MUXCTL_OWC,
- MUXCTL_SLXC,
- MUXCTL_SLXD,
- MUXCTL_SLXK,
-
- MUXCTL_UCA,
- MUXCTL_UCB,
- MUXCTL_DTA,
- MUXCTL_DTB,
- MUXCTL_RESERVED28,
- MUXCTL_DTC,
- MUXCTL_DTD,
- MUXCTL_DTE,
-
- /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
- MUXCTL_DDC,
- MUXCTL_CDEV1,
- MUXCTL_CDEV2,
- MUXCTL_CSUS,
- MUXCTL_I2CP,
- MUXCTL_KBCA,
- MUXCTL_KBCB,
- MUXCTL_KBCC,
-
- MUXCTL_IRTX,
- MUXCTL_IRRX,
- MUXCTL_DAP1,
- MUXCTL_DAP2,
- MUXCTL_DAP3,
- MUXCTL_DAP4,
- MUXCTL_GMB,
- MUXCTL_GMD,
-
- /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
- MUXCTL_GME,
- MUXCTL_GPV,
- MUXCTL_GPU,
- MUXCTL_SPDO,
- MUXCTL_SPDI,
- MUXCTL_SDB,
- MUXCTL_SDC,
- MUXCTL_SDD,
-
- MUXCTL_SPIH,
- MUXCTL_SPIG,
- MUXCTL_SPIF,
- MUXCTL_SPIE,
- MUXCTL_SPID,
- MUXCTL_SPIC,
- MUXCTL_SPIB,
- MUXCTL_SPIA,
-
- /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
- MUXCTL_LPW0,
- MUXCTL_LPW1,
- MUXCTL_LPW2,
- MUXCTL_LSDI,
- MUXCTL_LSDA,
- MUXCTL_LSPI,
- MUXCTL_LCSN,
- MUXCTL_LDC,
-
- MUXCTL_LSCK,
- MUXCTL_LSC0,
- MUXCTL_LSC1,
- MUXCTL_LHS,
- MUXCTL_LVS,
- MUXCTL_LM0,
- MUXCTL_LM1,
- MUXCTL_LVP0,
-
- /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
- MUXCTL_LD0,
- MUXCTL_LD1,
- MUXCTL_LD2,
- MUXCTL_LD3,
- MUXCTL_LD4,
- MUXCTL_LD5,
- MUXCTL_LD6,
- MUXCTL_LD7,
-
- MUXCTL_LD8,
- MUXCTL_LD9,
- MUXCTL_LD10,
- MUXCTL_LD11,
- MUXCTL_LD12,
- MUXCTL_LD13,
- MUXCTL_LD14,
- MUXCTL_LD15,
-
- /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
- MUXCTL_LD16,
- MUXCTL_LD17,
- MUXCTL_LHP1,
- MUXCTL_LHP2,
- MUXCTL_LVP1,
- MUXCTL_LHP0,
- MUXCTL_RESERVED102,
- MUXCTL_LPP,
-
- MUXCTL_LDI,
- MUXCTL_PMC,
- MUXCTL_CRTP,
- MUXCTL_PTA,
- MUXCTL_RESERVED108,
- MUXCTL_KBCD,
- MUXCTL_GPU7,
- MUXCTL_DTF,
-
- MUXCTL_NONE = -1,
-};
-
-/*
- * And this defines the order of the pullup/pulldown controls which are again
- * in a different order
- */
-enum pmux_pullid {
- /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
- PUCTL_ATA,
- PUCTL_ATB,
- PUCTL_ATC,
- PUCTL_ATD,
- PUCTL_ATE,
- PUCTL_DAP1,
- PUCTL_DAP2,
- PUCTL_DAP3,
-
- PUCTL_DAP4,
- PUCTL_DTA,
- PUCTL_DTB,
- PUCTL_DTC,
- PUCTL_DTD,
- PUCTL_DTE,
- PUCTL_DTF,
- PUCTL_GPV,
-
- /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
- PUCTL_RM,
- PUCTL_I2CP,
- PUCTL_PTA,
- PUCTL_GPU7,
- PUCTL_KBCA,
- PUCTL_KBCB,
- PUCTL_KBCC,
- PUCTL_KBCD,
-
- PUCTL_SPDI,
- PUCTL_SPDO,
- PUCTL_GPSLXAU,
- PUCTL_CRTP,
- PUCTL_SLXC,
- PUCTL_SLXD,
- PUCTL_SLXK,
-
- /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
- PUCTL_CDEV1,
- PUCTL_CDEV2,
- PUCTL_SPIA,
- PUCTL_SPIB,
- PUCTL_SPIC,
- PUCTL_SPID,
- PUCTL_SPIE,
- PUCTL_SPIF,
-
- PUCTL_SPIG,
- PUCTL_SPIH,
- PUCTL_IRTX,
- PUCTL_IRRX,
- PUCTL_GME,
- PUCTL_RESERVED45,
- PUCTL_XM2D,
- PUCTL_XM2C,
-
- /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
- PUCTL_UAA,
- PUCTL_UAB,
- PUCTL_UAC,
- PUCTL_UAD,
- PUCTL_UCA,
- PUCTL_UCB,
- PUCTL_LD17,
- PUCTL_LD19_18,
-
- PUCTL_LD21_20,
- PUCTL_LD23_22,
- PUCTL_LS,
- PUCTL_LC,
- PUCTL_CSUS,
- PUCTL_DDRC,
- PUCTL_SDC,
- PUCTL_SDD,
-
- /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
- PUCTL_KBCF,
- PUCTL_KBCE,
- PUCTL_PMCA,
- PUCTL_PMCB,
- PUCTL_PMCC,
- PUCTL_PMCD,
- PUCTL_PMCE,
- PUCTL_CK32,
-
- PUCTL_UDA,
- PUCTL_SDMMC1,
- PUCTL_GMA,
- PUCTL_GMB,
- PUCTL_GMC,
- PUCTL_GMD,
- PUCTL_DDC,
- PUCTL_OWC,
-
- PUCTL_NONE = -1
-};
-
-/* Convenient macro for defining pin group properties */
-#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
- { \
- .funcs = { \
- PMUX_FUNC_ ## f0, \
- PMUX_FUNC_ ## f1, \
- PMUX_FUNC_ ## f2, \
- PMUX_FUNC_ ## f3, \
- }, \
- .ctl_id = mux, \
- .pull_id = pupd \
- }
-
-/* A normal pin group where the mux name and pull-up name match */
-#define PIN(pingrp, f0, f1, f2, f3) \
- PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
-
-/* A pin group where the pull-up name doesn't have a 1-1 mapping */
-#define PINP(pingrp, f0, f1, f2, f3, pupd) \
- PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
-
-/* A pin group number which is not used */
-#define PIN_RESERVED \
- PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
-
-#define DRVGRP(drvgrp) \
- PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
-
-static const struct pmux_pingrp_desc tegra20_pingroups[] = {
- PIN(ATA, IDE, NAND, GMI, RSVD4),
- PIN(ATB, IDE, NAND, GMI, SDIO4),
- PIN(ATC, IDE, NAND, GMI, SDIO4),
- PIN(ATD, IDE, NAND, GMI, SDIO4),
- PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC),
- PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
- PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
- PIN(DAP1, DAP1, RSVD2, GMI, SDIO2),
-
- PIN(DAP2, DAP2, TWC, RSVD3, GMI),
- PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4),
- PIN(DAP4, DAP4, RSVD2, GMI, RSVD4),
- PIN(DTA, RSVD1, SDIO2, VI, RSVD4),
- PIN(DTB, RSVD1, RSVD2, VI, SPI1),
- PIN(DTC, RSVD1, RSVD2, VI, RSVD4),
- PIN(DTD, RSVD1, SDIO2, VI, RSVD4),
- PIN(DTE, RSVD1, RSVD2, VI, SPI1),
-
- PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU),
- PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
- PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4),
- PIN(IRTX, UARTA, UARTB, GMI, SPI4),
- PIN(IRRX, UARTA, UARTB, GMI, SPI4),
- PIN(KBCB, KBC, NAND, SDIO2, MIO),
- PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL),
- PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE),
-
- PIN(PTA, I2C2, HDMI, GMI, RSVD4),
- PIN(RM, I2C, RSVD2, RSVD3, RSVD4),
- PIN(KBCE, KBC, NAND, OWR, RSVD4),
- PIN(KBCF, KBC, NAND, TRACE, MIO),
- PIN(GMA, UARTE, SPI3, GMI, SDIO4),
- PIN(GMC, UARTD, SPI4, GMI, SFLASH),
- PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),
- PIN(OWC, OWR, RSVD2, RSVD3, RSVD4),
-
- PIN(GME, RSVD1, DAP5, GMI, SDIO4),
- PIN(SDC, PWM, TWC, SDIO3, SPI3),
- PIN(SDD, UARTA, PWM, SDIO3, SPI3),
- PIN_RESERVED,
- PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
- PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2),
- PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2),
- PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
-
- PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2),
- PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2),
- PIN(SPIA, SPI1, SPI2, SPI3, GMI),
- PIN(SPIB, SPI1, SPI2, SPI3, GMI),
- PIN(SPIC, SPI1, SPI2, SPI3, GMI),
- PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI),
- PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI),
- PIN(SPIF, SPI3, SPI1, SPI2, RSVD4),
-
- PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C),
- PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C),
- PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI),
- PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI),
- PIN(UAC, OWR, RSVD2, RSVD3, RSVD4),
- PIN(UAD, UARTB, SPDIF, UARTA, SPI4),
- PIN(UCA, UARTC, RSVD2, GMI, RSVD4),
- PIN(UCB, UARTC, PWM, GMI, RSVD4),
-
- PIN_RESERVED,
- PIN(ATE, IDE, NAND, GMI, RSVD4),
- PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL),
- PIN_RESERVED,
- PIN_RESERVED,
- PIN(GMB, IDE, NAND, GMI, GMI_INT),
- PIN(GMD, RSVD1, NAND, GMI, SFLASH),
- PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4),
-
- /* 64 */
- PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17),
-
- PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17),
-
- PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17),
- PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17),
- PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
- PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
- PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
- PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC),
- PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
- PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC),
-
- PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC),
- PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC),
- PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC),
- PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC),
- PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),
- PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),
- PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),
- PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),
-
- /* 96 */
- PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC),
- PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS),
- PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS),
- PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS),
- PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS),
- PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS),
- PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
- PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC),
-
- PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
- PIN_RESERVED,
- PIN(KBCD, KBC, NAND, SDIO2, MIO),
- PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4),
- PIN(DTF, I2C3, RSVD2, VI, RSVD4),
- PIN(UDA, SPI1, RSVD2, UARTD, ULPI),
- PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4),
- PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE),
-
- /* these pin groups only have pullup and pull down control */
- DRVGRP(CK32),
- DRVGRP(DDRC),
- DRVGRP(PMCA),
- DRVGRP(PMCB),
- DRVGRP(PMCC),
- DRVGRP(PMCD),
- DRVGRP(PMCE),
- DRVGRP(XM2C),
- DRVGRP(XM2D),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;
diff --git a/arch/arm/cpu/tegra20-common/pmu.c b/arch/arm/cpu/tegra20-common/pmu.c
deleted file mode 100644
index a774246..0000000
--- a/arch/arm/cpu/tegra20-common/pmu.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <tps6586x.h>
-#include <asm/io.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/ap.h>
-#include <asm/arch-tegra/tegra_i2c.h>
-#include <asm/arch-tegra/sys_proto.h>
-
-#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */
-#define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */
-
-#define VDD_CORE_NOMINAL_T20 0x16 /* 1.275v */
-#define VDD_CPU_NOMINAL_T20 0x0f /* 1.1v */
-
-#define VDD_RELATION 0x02 /* 50mv */
-#define VDD_TRANSITION_STEP 0x06 /* 150mv */
-#define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */
-
-#define PMI_I2C_ADDRESS 0x34 /* chip requires this address */
-
-int pmu_set_nominal(void)
-{
- struct udevice *bus, *dev;
- int core, cpu;
- int ret;
-
- /* by default, the table has been filled with T25 settings */
- switch (tegra_get_chip_sku()) {
- case TEGRA_SOC_T20:
- core = VDD_CORE_NOMINAL_T20;
- cpu = VDD_CPU_NOMINAL_T20;
- break;
- case TEGRA_SOC_T25:
- core = VDD_CORE_NOMINAL_T25;
- cpu = VDD_CPU_NOMINAL_T25;
- break;
- default:
- debug("%s: Unknown SKU id\n", __func__);
- return -1;
- }
-
- ret = tegra_i2c_get_dvc_bus(&bus);
- if (ret) {
- debug("%s: Cannot find DVC I2C bus\n", __func__);
- return ret;
- }
- ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, 1, &dev);
- if (ret) {
- debug("%s: Cannot find DVC I2C chip\n", __func__);
- return ret;
- }
-
- tps6586x_init(dev);
- tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
- return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
- VDD_TRANSITION_RATE, VDD_RELATION);
-}
diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c
deleted file mode 100644
index 5fdc4bb..0000000
--- a/arch/arm/cpu/tegra20-common/warmboot.c
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * (C) Copyright 2010 - 2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/emc.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/sdram_param.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/ap.h>
-#include <asm/arch-tegra/apb_misc.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/fuse.h>
-#include <asm/arch-tegra/warmboot.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_TEGRA_CLOCK_SCALING
-#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
-#endif
-
-/*
- * This is the place in SRAM where the SDRAM parameters are stored. There
- * are 4 blocks, one for each RAM code
- */
-#define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
-
-/* TODO: If we later add support for the Misc GP controller, refactor this */
-union xm2cfga_reg {
- struct {
- u32 reserved0:2;
- u32 hsm_en:1;
- u32 reserved1:2;
- u32 preemp_en:1;
- u32 vref_en:1;
- u32 reserved2:5;
- u32 cal_drvdn:5;
- u32 reserved3:3;
- u32 cal_drvup:5;
- u32 reserved4:3;
- u32 cal_drvdn_slwr:2;
- u32 cal_drvup_slwf:2;
- };
- u32 word;
-};
-
-union xm2cfgd_reg {
- struct {
- u32 reserved0:2;
- u32 hsm_en:1;
- u32 schmt_en:1;
- u32 lpmd:2;
- u32 vref_en:1;
- u32 reserved1:5;
- u32 cal_drvdn:5;
- u32 reserved2:3;
- u32 cal_drvup:5;
- u32 reserved3:3;
- u32 cal_drvdn_slwr:2;
- u32 cal_drvup_slwf:2;
- };
- u32 word;
-};
-
-/*
- * TODO: This register is not documented in the TRM yet. We could move this
- * into the EMC and give it a proper interface, but not while it is
- * undocumented.
- */
-union fbio_spare_reg {
- struct {
- u32 reserved:24;
- u32 cfg_wb0:8;
- };
- u32 word;
-};
-
-/* We pack the resume information into these unions for later */
-union scratch2_reg {
- struct {
- u32 pllm_base_divm:5;
- u32 pllm_base_divn:10;
- u32 pllm_base_divp:3;
- u32 pllm_misc_lfcon:4;
- u32 pllm_misc_cpcon:4;
- u32 gp_xm2cfga_padctrl_preemp:1;
- u32 gp_xm2cfgd_padctrl_schmt:1;
- u32 osc_ctrl_xobp:1;
- u32 memory_type:3;
- };
- u32 word;
-};
-
-union scratch4_reg {
- struct {
- u32 emc_clock_divider:8;
- u32 pllm_stable_time:8;
- u32 pllx_stable_time:8;
- u32 emc_fbio_spare_cfg_wb0:8;
- };
- u32 word;
-};
-
-union scratch24_reg {
- struct {
- u32 emc_auto_cal_wait:8;
- u32 emc_pin_program_wait:8;
- u32 warmboot_wait:8;
- u32 reserved:8;
- };
- u32 word;
-};
-
-int warmboot_save_sdram_params(void)
-{
- u32 ram_code;
- struct sdram_params sdram;
- struct apb_misc_pp_ctlr *apb_misc =
- (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
- struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
- union scratch2_reg scratch2;
- union scratch4_reg scratch4;
- union scratch24_reg scratch24;
- union xm2cfga_reg xm2cfga;
- union xm2cfgd_reg xm2cfgd;
- union fbio_spare_reg fbio_spare;
-
- /* get ram code that is used as index to array sdram_params in BCT */
- ram_code = (readl(&apb_misc->strapping_opt_a) >>
- STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
- memcpy(&sdram,
- (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
- sizeof(sdram));
-
- xm2cfga.word = readl(&gp->xm2cfga);
- xm2cfgd.word = readl(&gp->xm2cfgd);
-
- scratch2.word = 0;
- scratch2.osc_ctrl_xobp = clock_get_osc_bypass();
-
- /* Get the memory PLL settings */
- {
- u32 divm, divn, divp, cpcon, lfcon;
-
- if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
- &cpcon, &lfcon))
- return -1;
- scratch2.pllm_base_divm = divm;
- scratch2.pllm_base_divn = divn;
- scratch2.pllm_base_divp = divp;
- scratch2.pllm_misc_cpcon = cpcon;
- scratch2.pllm_misc_lfcon = lfcon;
- }
-
- scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en;
- scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en;
- scratch2.memory_type = sdram.memory_type;
- writel(scratch2.word, &pmc->pmc_scratch2);
-
- /* collect data from various sources for pmc_scratch4 */
- fbio_spare.word = readl(&emc->fbio_spare);
- scratch4.word = 0;
- scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0;
- scratch4.emc_clock_divider = sdram.emc_clock_divider;
- scratch4.pllm_stable_time = -1;
- scratch4.pllx_stable_time = -1;
- writel(scratch4.word, &pmc->pmc_scratch4);
-
- /* collect various data from sdram for pmc_scratch24 */
- scratch24.word = 0;
- scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait;
- scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait;
- scratch24.warmboot_wait = sdram.warm_boot_wait;
- writel(scratch24.word, &pmc->pmc_scratch24);
-
- return 0;
-}
-
-static u32 get_major_version(void)
-{
- u32 major_id;
- struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
-
- major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
- HIDREV_MAJORPREV_SHIFT;
- return major_id;
-}
-
-static int is_production_mode_fuse_set(struct fuse_regs *fuse)
-{
- return readl(&fuse->production_mode);
-}
-
-static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse)
-{
- return readl(&fuse->security_mode);
-}
-
-static int is_failure_analysis_mode(struct fuse_regs *fuse)
-{
- return readl(&fuse->fa);
-}
-
-static int ap20_is_odm_production_mode(void)
-{
- struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
-
- if (!is_failure_analysis_mode(fuse) &&
- is_odm_production_mode_fuse_set(fuse))
- return 1;
- else
- return 0;
-}
-
-static int ap20_is_production_mode(void)
-{
- struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
-
- if (get_major_version() == 0)
- return 1;
-
- if (!is_failure_analysis_mode(fuse) &&
- is_production_mode_fuse_set(fuse) &&
- !is_odm_production_mode_fuse_set(fuse))
- return 1;
- else
- return 0;
-}
-
-static enum fuse_operating_mode fuse_get_operation_mode(void)
-{
- u32 chip_id;
- struct apb_misc_gp_ctlr *gp =
- (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
-
- chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
- HIDREV_CHIPID_SHIFT;
- if (chip_id == CHIPID_TEGRA20) {
- if (ap20_is_odm_production_mode()) {
- printf("!! odm_production_mode is not supported !!\n");
- return MODE_UNDEFINED;
- } else
- if (ap20_is_production_mode())
- return MODE_PRODUCTION;
- else
- return MODE_UNDEFINED;
- }
- return MODE_UNDEFINED;
-}
-
-static void determine_crypto_options(int *is_encrypted, int *is_signed,
- int *use_zero_key)
-{
- switch (fuse_get_operation_mode()) {
- case MODE_PRODUCTION:
- *is_encrypted = 0;
- *is_signed = 1;
- *use_zero_key = 1;
- break;
- case MODE_UNDEFINED:
- default:
- *is_encrypted = 0;
- *is_signed = 0;
- *use_zero_key = 0;
- break;
- }
-}
-
-static int sign_wb_code(u32 start, u32 length, int use_zero_key)
-{
- int err;
- u8 *source; /* Pointer to source */
- u8 *hash;
-
- /* Calculate AES block parameters. */
- source = (u8 *)(start + offsetof(struct wb_header, random_aes_block));
- length -= offsetof(struct wb_header, random_aes_block);
- hash = (u8 *)(start + offsetof(struct wb_header, hash));
- err = sign_data_block(source, length, hash);
-
- return err;
-}
-
-int warmboot_prepare_code(u32 seg_address, u32 seg_length)
-{
- int err = 0;
- u32 length; /* length of the signed/encrypt code */
- struct wb_header *dst_header; /* Pointer to dest WB header */
- int is_encrypted; /* Segment is encrypted */
- int is_signed; /* Segment is signed */
- int use_zero_key; /* Use key of all zeros */
-
- /* Determine crypto options. */
- determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key);
-
- /* Get the actual code limits. */
- length = roundup(((u32)wb_end - (u32)wb_start), 16);
-
- /*
- * The region specified by seg_address must be in SDRAM and must be
- * nonzero in length.
- */
- if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE ||
- seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) {
- err = -EFAULT;
- goto fail;
- }
-
- /* Things must be 16-byte aligned. */
- if ((seg_length & 0xF) || (seg_address & 0xF)) {
- err = -EINVAL;
- goto fail;
- }
-
- /* Will the code fit? (destination includes wb_header + wb code) */
- if (seg_length < (length + sizeof(struct wb_header))) {
- err = -EINVAL;
- goto fail;
- }
-
- dst_header = (struct wb_header *)seg_address;
- memset((char *)dst_header, 0, sizeof(struct wb_header));
-
- /* Populate the random_aes_block as requested. */
- {
- u32 *aes_block = (u32 *)&(dst_header->random_aes_block);
- u32 *end = (u32 *)(((u32)aes_block) +
- sizeof(dst_header->random_aes_block));
-
- do {
- *aes_block++ = 0;
- } while (aes_block < end);
- }
-
- /* Populate the header. */
- dst_header->length_insecure = length + sizeof(struct wb_header);
- dst_header->length_secure = length + sizeof(struct wb_header);
- dst_header->destination = NV_WB_RUN_ADDRESS;
- dst_header->entry_point = NV_WB_RUN_ADDRESS;
- dst_header->code_length = length;
-
- if (is_encrypted) {
- printf("!!!! Encryption is not supported !!!!\n");
- dst_header->length_insecure = 0;
- err = -EACCES;
- goto fail;
- } else
- /* copy the wb code directly following dst_header. */
- memcpy((char *)(dst_header+1), (char *)wb_start, length);
-
- if (is_signed)
- err = sign_wb_code(seg_address, dst_header->length_insecure,
- use_zero_key);
-
-fail:
- if (err)
- printf("Warning: warmboot code copy failed (error=%d)\n", err);
-
- return err;
-}
diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c
deleted file mode 100644
index 27ce5f4..0000000
--- a/arch/arm/cpu/tegra20-common/warmboot_avp.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * (C) Copyright 2010 - 2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/flow.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/ap.h>
-#include <asm/arch-tegra/apb_misc.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/warmboot.h>
-#include "warmboot_avp.h"
-
-#define DEBUG_RESET_CORESIGHT
-
-void wb_start(void)
-{
- struct apb_misc_pp_ctlr *apb_misc =
- (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- union osc_ctrl_reg osc_ctrl;
- union pllx_base_reg pllx_base;
- union pllx_misc_reg pllx_misc;
- union scratch3_reg scratch3;
- u32 reg;
-
- /* enable JTAG & TBE */
- writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
-
- /* Are we running where we're supposed to be? */
- asm volatile (
- "adr %0, wb_start;" /* reg: wb_start address */
- : "=r"(reg) /* output */
- /* no input, no clobber list */
- );
-
- if (reg != NV_WB_RUN_ADDRESS)
- goto do_reset;
-
- /* Are we running with AVP? */
- if (readl(NV_PA_PG_UP_BASE + PG_UP_TAG_0) != PG_UP_TAG_AVP)
- goto do_reset;
-
-#ifdef DEBUG_RESET_CORESIGHT
- /* Assert CoreSight reset */
- reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);
- reg |= SWR_CSITE_RST;
- writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);
-#endif
-
- /* TODO: Set the drive strength - maybe make this a board parameter? */
- osc_ctrl.word = readl(&clkrst->crc_osc_ctrl);
- osc_ctrl.xofs = 4;
- osc_ctrl.xoe = 1;
- writel(osc_ctrl.word, &clkrst->crc_osc_ctrl);
-
- /* Power up the CPU complex if necessary */
- if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) {
- reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START;
- writel(reg, &pmc->pmc_pwrgate_toggle);
- while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU))
- ;
- }
-
- /* Remove the I/O clamps from the CPU power partition. */
- reg = readl(&pmc->pmc_remove_clamping);
- reg |= CPU_CLMP;
- writel(reg, &pmc->pmc_remove_clamping);
-
- reg = EVENT_ZERO_VAL_20 | EVENT_MSEC | EVENT_MODE_STOP;
- writel(reg, &flow->halt_cop_events);
-
- /* Assert CPU complex reset */
- reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);
- reg |= CPU_RST;
- writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
-
- /* Hold both CPUs in reset */
- reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_CPURESET1 | CPU_CMPLX_DERESET0 |
- CPU_CMPLX_DERESET1 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DBGRESET1;
- writel(reg, &clkrst->crc_cpu_cmplx_set);
-
- /* Halt CPU1 at the flow controller for uni-processor configurations */
- writel(EVENT_MODE_STOP, &flow->halt_cpu1_events);
-
- /*
- * Set the CPU reset vector. SCRATCH41 contains the physical
- * address of the CPU-side restoration code.
- */
- reg = readl(&pmc->pmc_scratch41);
- writel(reg, EXCEP_VECTOR_CPU_RESET_VECTOR);
-
- /* Select CPU complex clock source */
- writel(CCLK_PLLP_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
-
- /* Start the CPU0 clock and stop the CPU1 clock */
- reg = CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 | CPU_CMPLX_CPU0_CLK_STP_RUN |
- CPU_CMPLX_CPU1_CLK_STP_STOP;
- writel(reg, &clkrst->crc_clk_cpu_cmplx);
-
- /* Enable the CPU complex clock */
- reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]);
- reg |= CLK_ENB_CPU;
- writel(reg, &clkrst->crc_clk_out_enb[TEGRA_DEV_L]);
-
- /* Make sure the resets were held for at least 2 microseconds */
- reg = readl(TIMER_USEC_CNTR);
- while (readl(TIMER_USEC_CNTR) <= (reg + 2))
- ;
-
-#ifdef DEBUG_RESET_CORESIGHT
- /*
- * De-assert CoreSight reset.
- * NOTE: We're leaving the CoreSight clock on the oscillator for
- * now. It will be restored to its original clock source
- * when the CPU-side restoration code runs.
- */
- reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);
- reg &= ~SWR_CSITE_RST;
- writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);
-#endif
-
- /* Unlock the CPU CoreSight interfaces */
- reg = 0xC5ACCE55;
- writel(reg, CSITE_CPU_DBG0_LAR);
- writel(reg, CSITE_CPU_DBG1_LAR);
-
- /*
- * Sample the microsecond timestamp again. This is the time we must
- * use when returning from LP0 for PLL stabilization delays.
- */
- reg = readl(TIMER_USEC_CNTR);
- writel(reg, &pmc->pmc_scratch1);
-
- pllx_base.word = 0;
- pllx_misc.word = 0;
- scratch3.word = readl(&pmc->pmc_scratch3);
-
- /* Get the OSC. For 19.2 MHz, use 19 to make the calculations easier */
- reg = (readl(TIMER_USEC_CFG) & USEC_CFG_DIVISOR_MASK) + 1;
-
- /*
- * According to the TRM, for 19.2MHz OSC, the USEC_DIVISOR is 0x5f, and
- * USEC_DIVIDEND is 0x04. So, if USEC_DIVISOR > 26, OSC is 19.2 MHz.
- *
- * reg is used to calculate the pllx freq, which is used to determine if
- * to set dccon or not.
- */
- if (reg > 26)
- reg = 19;
-
- /* PLLX_BASE.PLLX_DIVM */
- if (scratch3.pllx_base_divm == reg)
- reg = 0;
- else
- reg = 1;
-
- /* PLLX_BASE.PLLX_DIVN */
- pllx_base.divn = scratch3.pllx_base_divn;
- reg = scratch3.pllx_base_divn << reg;
-
- /* PLLX_BASE.PLLX_DIVP */
- pllx_base.divp = scratch3.pllx_base_divp;
- reg = reg >> scratch3.pllx_base_divp;
-
- pllx_base.bypass = 1;
-
- /* PLLX_MISC_DCCON must be set for pllx frequency > 600 MHz. */
- if (reg > 600)
- pllx_misc.dccon = 1;
-
- /* PLLX_MISC_LFCON */
- pllx_misc.lfcon = scratch3.pllx_misc_lfcon;
-
- /* PLLX_MISC_CPCON */
- pllx_misc.cpcon = scratch3.pllx_misc_cpcon;
-
- writel(pllx_misc.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_misc);
- writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
-
- pllx_base.enable = 1;
- writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
- pllx_base.bypass = 0;
- writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
-
- writel(0, flow->halt_cpu_events);
-
- reg = CPU_CMPLX_CPURESET0 | CPU_CMPLX_DBGRESET0 | CPU_CMPLX_DERESET0;
- writel(reg, &clkrst->crc_cpu_cmplx_clr);
-
- reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |
- PLLM_OUT1_RATIO_VAL_8;
- writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);
-
- reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
- SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |
- SCLK_SYS_STATE_IDLE;
- writel(reg, &clkrst->crc_sclk_brst_pol);
-
- /* avp_resume: no return after the write */
- reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);
- reg &= ~CPU_RST;
- writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
-
- /* avp_halt: */
-avp_halt:
- reg = EVENT_MODE_STOP | EVENT_JTAG;
- writel(reg, flow->halt_cop_events);
- goto avp_halt;
-
-do_reset:
- /*
- * Execution comes here if something goes wrong. The chip is reset and
- * a cold boot is performed.
- */
- writel(SWR_TRIG_SYS_RST, &clkrst->crc_rst_dev[TEGRA_DEV_L]);
- goto do_reset;
-}
-
-/*
- * wb_end() is a dummy function, and must be directly following wb_start(),
- * and is used to calculate the size of wb_start().
- */
-void wb_end(void)
-{
-}
diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.h b/arch/arm/cpu/tegra20-common/warmboot_avp.h
deleted file mode 100644
index 7b86acb..0000000
--- a/arch/arm/cpu/tegra20-common/warmboot_avp.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * (C) Copyright 2010, 2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _WARMBOOT_AVP_H_
-#define _WARMBOOT_AVP_H_
-
-#define TEGRA_DEV_L 0
-#define TEGRA_DEV_H 1
-#define TEGRA_DEV_U 2
-
-#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
-#define SIMPLE_PLLE (CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE)
-
-#define TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0)
-#define TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4)
-
-#define USEC_CFG_DIVISOR_MASK 0xffff
-
-#define CONFIG_CTL_TBE (1 << 7)
-#define CONFIG_CTL_JTAG (1 << 6)
-
-#define CPU_RST (1 << 0)
-#define CLK_ENB_CPU (1 << 0)
-#define SWR_TRIG_SYS_RST (1 << 2)
-#define SWR_CSITE_RST (1 << 9)
-
-#define PWRGATE_STATUS_CPU (1 << 0)
-#define PWRGATE_TOGGLE_PARTID_CPU (0 << 0)
-#define PWRGATE_TOGGLE_START (1 << 8)
-
-#define CPU_CMPLX_CPU_BRIDGE_CLKDIV_4 (3 << 0)
-#define CPU_CMPLX_CPU0_CLK_STP_STOP (1 << 8)
-#define CPU_CMPLX_CPU0_CLK_STP_RUN (0 << 8)
-#define CPU_CMPLX_CPU1_CLK_STP_STOP (1 << 9)
-#define CPU_CMPLX_CPU1_CLK_STP_RUN (0 << 9)
-
-#define CPU_CMPLX_CPURESET0 (1 << 0)
-#define CPU_CMPLX_CPURESET1 (1 << 1)
-#define CPU_CMPLX_DERESET0 (1 << 4)
-#define CPU_CMPLX_DERESET1 (1 << 5)
-#define CPU_CMPLX_DBGRESET0 (1 << 12)
-#define CPU_CMPLX_DBGRESET1 (1 << 13)
-
-#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0)
-#define PLLM_OUT1_CLKEN_ENABLE (1 << 1)
-#define PLLM_OUT1_RATIO_VAL_8 (8 << 8)
-
-#define SCLK_SYS_STATE_IDLE (1 << 28)
-#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
-#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
-#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
-#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
-
-#define EVENT_ZERO_VAL_20 (20 << 0)
-#define EVENT_MSEC (1 << 24)
-#define EVENT_JTAG (1 << 28)
-#define EVENT_MODE_STOP (2 << 29)
-
-#define CCLK_PLLP_BURST_POLICY 0x20004444
-
-#endif
diff --git a/arch/arm/cpu/tegra30-common/Makefile b/arch/arm/cpu/tegra30-common/Makefile
deleted file mode 100644
index d2d616e..0000000
--- a/arch/arm/cpu/tegra30-common/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
-#
-
-obj-y += clock.o funcmux.o pinmux.o
diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c
deleted file mode 100644
index 0eb0f0a..0000000
--- a/arch/arm/cpu/tegra30-common/clock.c
+++ /dev/null
@@ -1,744 +0,0 @@
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Tegra30 Clock control functions */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
-#include <div64.h>
-#include <fdtdec.h>
-
-/*
- * Clock types that we can use as a source. The Tegra30 has muxes for the
- * peripheral clocks, and in most cases there are four options for the clock
- * source. This gives us a clock 'type' and exploits what commonality exists
- * in the device.
- *
- * Letters are obvious, except for T which means CLK_M, and S which means the
- * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
- * datasheet) and PLL_M are different things. The former is the basic
- * clock supplied to the SOC from an external oscillator. The latter is the
- * memory clock PLL.
- *
- * See definitions in clock_id in the header file.
- */
-enum clock_type_id {
- CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
- CLOCK_TYPE_MCPA, /* and so on */
- CLOCK_TYPE_MCPT,
- CLOCK_TYPE_PCM,
- CLOCK_TYPE_PCMT,
- CLOCK_TYPE_PCMT16,
- CLOCK_TYPE_PDCT,
- CLOCK_TYPE_ACPT,
- CLOCK_TYPE_ASPTE,
- CLOCK_TYPE_PMDACD2T,
- CLOCK_TYPE_PCST,
-
- CLOCK_TYPE_COUNT,
- CLOCK_TYPE_NONE = -1, /* invalid clock type */
-};
-
-enum {
- CLOCK_MAX_MUX = 8 /* number of source options for each clock */
-};
-
-/*
- * Clock source mux for each clock type. This just converts our enum into
- * a list of mux sources for use by the code.
- *
- * Note:
- * The extra column in each clock source array is used to store the mask
- * bits in its register for the source.
- */
-#define CLK(x) CLOCK_ID_ ## x
-static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
- { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_30},
- { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
- CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_29},
- { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
- CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
- MASK_BITS_31_29},
- { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
- CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
- MASK_BITS_31_28}
-};
-
-/*
- * Clock type for each peripheral clock source. We put the name in each
- * record just so it is easy to match things up
- */
-#define TYPE(name, type) type
-static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
- /* 0x00 */
- TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
- TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
-
- /* 0x08 */
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
- TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
-
- /* 0x10 */
- TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
-
- /* 0x18 */
- TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
- TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
-
- /* 0x20 */
- TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
- TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
-
- /* 0x28 */
- TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
-
- /* 0x30 */
- TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
-
- /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
- TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
- TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
- TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
- TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
- TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
-
- /* 0x40 */
- TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
- TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
- TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
- TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
- TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
-
- /* 0x48 */
- TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
- TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
- TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
- TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
-
- /* 0x50 */
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
- TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
- TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
-};
-
-/*
- * This array translates a periph_id to a periphc_internal_id
- *
- * Not present/matched up:
- * uint vi_sensor; _VI_SENSOR_0, 0x1A8
- * SPDIF - which is both 0x08 and 0x0c
- *
- */
-#define NONE(name) (-1)
-#define OFFSET(name, value) PERIPHC_ ## name
-static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
- /* Low word: 31:0 */
- NONE(CPU),
- NONE(COP),
- NONE(TRIGSYS),
- NONE(RESERVED3),
- NONE(RESERVED4),
- NONE(TMR),
- PERIPHC_UART1,
- PERIPHC_UART2, /* and vfir 0x68 */
-
- /* 8 */
- NONE(GPIO),
- PERIPHC_SDMMC2,
- NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
- PERIPHC_I2S1,
- PERIPHC_I2C1,
- PERIPHC_NDFLASH,
- PERIPHC_SDMMC1,
- PERIPHC_SDMMC4,
-
- /* 16 */
- NONE(RESERVED16),
- PERIPHC_PWM,
- PERIPHC_I2S2,
- PERIPHC_EPP,
- PERIPHC_VI,
- PERIPHC_G2D,
- NONE(USBD),
- NONE(ISP),
-
- /* 24 */
- PERIPHC_G3D,
- NONE(RESERVED25),
- PERIPHC_DISP2,
- PERIPHC_DISP1,
- PERIPHC_HOST1X,
- NONE(VCP),
- PERIPHC_I2S0,
- NONE(CACHE2),
-
- /* Middle word: 63:32 */
- NONE(MEM),
- NONE(AHBDMA),
- NONE(APBDMA),
- NONE(RESERVED35),
- NONE(RESERVED36),
- NONE(STAT_MON),
- NONE(RESERVED38),
- NONE(RESERVED39),
-
- /* 40 */
- NONE(KFUSE),
- PERIPHC_SBC1,
- PERIPHC_NOR,
- NONE(RESERVED43),
- PERIPHC_SBC2,
- NONE(RESERVED45),
- PERIPHC_SBC3,
- PERIPHC_DVC_I2C,
-
- /* 48 */
- NONE(DSI),
- PERIPHC_TVO, /* also CVE 0x40 */
- PERIPHC_MIPI,
- PERIPHC_HDMI,
- NONE(CSI),
- PERIPHC_TVDAC,
- PERIPHC_I2C2,
- PERIPHC_UART3,
-
- /* 56 */
- NONE(RESERVED56),
- PERIPHC_EMC,
- NONE(USB2),
- NONE(USB3),
- PERIPHC_MPE,
- PERIPHC_VDE,
- NONE(BSEA),
- NONE(BSEV),
-
- /* Upper word 95:64 */
- PERIPHC_SPEEDO,
- PERIPHC_UART4,
- PERIPHC_UART5,
- PERIPHC_I2C3,
- PERIPHC_SBC4,
- PERIPHC_SDMMC3,
- NONE(PCIE),
- PERIPHC_OWR,
-
- /* 72 */
- NONE(AFI),
- PERIPHC_CSITE,
- NONE(PCIEXCLK),
- NONE(AVPUCQ),
- NONE(RESERVED76),
- NONE(RESERVED77),
- NONE(RESERVED78),
- NONE(DTV),
-
- /* 80 */
- PERIPHC_NANDSPEED,
- PERIPHC_I2CSLOW,
- NONE(DSIB),
- NONE(RESERVED83),
- NONE(IRAMA),
- NONE(IRAMB),
- NONE(IRAMC),
- NONE(IRAMD),
-
- /* 88 */
- NONE(CRAM2),
- NONE(RESERVED89),
- NONE(MDOUBLER),
- NONE(RESERVED91),
- NONE(SUSOUT),
- NONE(RESERVED93),
- NONE(RESERVED94),
- NONE(RESERVED95),
-
- /* V word: 31:0 */
- NONE(CPUG),
- NONE(CPULP),
- PERIPHC_G3D2,
- PERIPHC_MSELECT,
- PERIPHC_TSENSOR,
- PERIPHC_I2S3,
- PERIPHC_I2S4,
- PERIPHC_I2C4,
-
- /* 08 */
- PERIPHC_SBC5,
- PERIPHC_SBC6,
- PERIPHC_AUDIO,
- NONE(APBIF),
- PERIPHC_DAM0,
- PERIPHC_DAM1,
- PERIPHC_DAM2,
- PERIPHC_HDA2CODEC2X,
-
- /* 16 */
- NONE(ATOMICS),
- NONE(RESERVED17),
- NONE(RESERVED18),
- NONE(RESERVED19),
- NONE(RESERVED20),
- NONE(RESERVED21),
- NONE(RESERVED22),
- PERIPHC_ACTMON,
-
- /* 24 */
- NONE(RESERVED24),
- NONE(RESERVED25),
- NONE(RESERVED26),
- NONE(RESERVED27),
- PERIPHC_SATA,
- PERIPHC_HDA,
- NONE(RESERVED30),
- NONE(RESERVED31),
-
- /* W word: 31:0 */
- NONE(HDA2HDMICODEC),
- NONE(SATACOLD),
- NONE(RESERVED0_PCIERX0),
- NONE(RESERVED1_PCIERX1),
- NONE(RESERVED2_PCIERX2),
- NONE(RESERVED3_PCIERX3),
- NONE(RESERVED4_PCIERX4),
- NONE(RESERVED5_PCIERX5),
-
- /* 40 */
- NONE(CEC),
- NONE(RESERVED6_PCIE2),
- NONE(RESERVED7_EMC),
- NONE(RESERVED8_HDMI),
- NONE(RESERVED9_SATA),
- NONE(RESERVED10_MIPI),
- NONE(EX_RESERVED46),
- NONE(EX_RESERVED47),
-};
-
-/*
- * Get the oscillator frequency, from the corresponding hardware configuration
- * field. Note that T30 supports 3 new higher freqs, but we map back
- * to the old T20 freqs. Support for the higher oscillators is TBD.
- */
-enum clock_osc_freq clock_get_osc_freq(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- reg = readl(&clkrst->crc_osc_ctrl);
- reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
-
- if (reg & 1) /* one of the newer freqs */
- printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
-
- return reg >> 2; /* Map to most common (T20) freqs */
-}
-
-/* Returns a pointer to the clock source register for a peripheral */
-u32 *get_periph_source_reg(enum periph_id periph_id)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- enum periphc_internal_id internal_id;
-
- /* Coresight is a special case */
- if (periph_id == PERIPH_ID_CSI)
- return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
-
- assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
- internal_id = periph_id_to_internal_id[periph_id];
- assert(internal_id != -1);
- if (internal_id >= PERIPHC_VW_FIRST) {
- internal_id -= PERIPHC_VW_FIRST;
- return &clkrst->crc_clk_src_vw[internal_id];
- } else
- return &clkrst->crc_clk_src[internal_id];
-}
-
-/**
- * Given a peripheral ID and the required source clock, this returns which
- * value should be programmed into the source mux for that peripheral.
- *
- * There is special code here to handle the one source type with 5 sources.
- *
- * @param periph_id peripheral to start
- * @param source PLL id of required parent clock
- * @param mux_bits Set to number of bits in mux register: 2 or 4
- * @param divider_bits Set to number of divider bits (8 or 16)
- * @return mux value (0-4, or -1 if not found)
- */
-int get_periph_clock_source(enum periph_id periph_id,
- enum clock_id parent, int *mux_bits, int *divider_bits)
-{
- enum clock_type_id type;
- enum periphc_internal_id internal_id;
- int mux;
-
- assert(clock_periph_id_isvalid(periph_id));
-
- internal_id = periph_id_to_internal_id[periph_id];
- assert(periphc_internal_id_isvalid(internal_id));
-
- type = clock_periph_type[internal_id];
- assert(clock_type_id_isvalid(type));
-
- *mux_bits = clock_source[type][CLOCK_MAX_MUX];
-
- if (type == CLOCK_TYPE_PCMT16)
- *divider_bits = 16;
- else
- *divider_bits = 8;
-
- for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
- if (clock_source[type][mux] == parent)
- return mux;
-
- /* if we get here, either us or the caller has made a mistake */
- printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
- parent);
- return -1;
-}
-
-void clock_set_enable(enum periph_id periph_id, int enable)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *clk;
- u32 reg;
-
- /* Enable/disable the clock to this peripheral */
- assert(clock_periph_id_isvalid(periph_id));
- if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
- clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
- else
- clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
- reg = readl(clk);
- if (enable)
- reg |= PERIPH_MASK(periph_id);
- else
- reg &= ~PERIPH_MASK(periph_id);
- writel(reg, clk);
-}
-
-void reset_set_enable(enum periph_id periph_id, int enable)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 *reset;
- u32 reg;
-
- /* Enable/disable reset to the peripheral */
- assert(clock_periph_id_isvalid(periph_id));
- if (periph_id < PERIPH_ID_VW_FIRST)
- reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
- else
- reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
- reg = readl(reset);
- if (enable)
- reg |= PERIPH_MASK(periph_id);
- else
- reg &= ~PERIPH_MASK(periph_id);
- writel(reg, reset);
-}
-
-#ifdef CONFIG_OF_CONTROL
-/*
- * Convert a device tree clock ID to our peripheral ID. They are mostly
- * the same but we are very cautious so we check that a valid clock ID is
- * provided.
- *
- * @param clk_id Clock ID according to tegra30 device tree binding
- * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
- */
-enum periph_id clk_id_to_periph_id(int clk_id)
-{
- if (clk_id > PERIPH_ID_COUNT)
- return PERIPH_ID_NONE;
-
- switch (clk_id) {
- case PERIPH_ID_RESERVED3:
- case PERIPH_ID_RESERVED4:
- case PERIPH_ID_RESERVED16:
- case PERIPH_ID_RESERVED24:
- case PERIPH_ID_RESERVED35:
- case PERIPH_ID_RESERVED43:
- case PERIPH_ID_RESERVED45:
- case PERIPH_ID_RESERVED56:
- case PERIPH_ID_PCIEXCLK:
- case PERIPH_ID_RESERVED76:
- case PERIPH_ID_RESERVED77:
- case PERIPH_ID_RESERVED78:
- case PERIPH_ID_RESERVED83:
- case PERIPH_ID_RESERVED89:
- case PERIPH_ID_RESERVED91:
- case PERIPH_ID_RESERVED93:
- case PERIPH_ID_RESERVED94:
- case PERIPH_ID_RESERVED95:
- return PERIPH_ID_NONE;
- default:
- return clk_id;
- }
-}
-#endif /* CONFIG_OF_CONTROL */
-
-void clock_early_init(void)
-{
- tegra30_set_up_pllp();
-}
-
-void arch_timer_init(void)
-{
-}
-
-#define PMC_SATA_PWRGT 0x1ac
-#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
-#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
-
-#define PLLE_SS_CNTL 0x68
-#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
-#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
-#define PLLE_SS_CNTL_SSCBYP (1 << 12)
-#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
-#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
-#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
-
-#define PLLE_BASE 0x0e8
-#define PLLE_BASE_ENABLE_CML (1 << 31)
-#define PLLE_BASE_ENABLE (1 << 30)
-#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
-#define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
-#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
-#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
-
-#define PLLE_MISC 0x0ec
-#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
-#define PLLE_MISC_PLL_READY (1 << 15)
-#define PLLE_MISC_LOCK (1 << 11)
-#define PLLE_MISC_LOCK_ENABLE (1 << 9)
-#define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
-
-static int tegra_plle_train(void)
-{
- unsigned int timeout = 2000;
- unsigned long value;
-
- value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
- value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
- writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
-
- value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
- value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
- writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
-
- value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
- value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
- writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
-
- do {
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- if (value & PLLE_MISC_PLL_READY)
- break;
-
- udelay(100);
- } while (--timeout);
-
- if (timeout == 0) {
- error("timeout waiting for PLLE to become ready");
- return -ETIMEDOUT;
- }
-
- return 0;
-}
-
-int tegra_plle_enable(void)
-{
- unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000;
- u32 value;
- int err;
-
- /* disable PLLE clock */
- value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
- value &= ~PLLE_BASE_ENABLE_CML;
- value &= ~PLLE_BASE_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- /* clear lock enable and setup field */
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- value &= ~PLLE_MISC_LOCK_ENABLE;
- value &= ~PLLE_MISC_SETUP_BASE(0xffff);
- value &= ~PLLE_MISC_SETUP_EXT(0x3);
- writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- if ((value & PLLE_MISC_PLL_READY) == 0) {
- err = tegra_plle_train();
- if (err < 0) {
- error("failed to train PLLE: %d", err);
- return err;
- }
- }
-
- /* configure PLLE */
- value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- value &= ~PLLE_BASE_PLDIV_CML(0x0f);
- value |= PLLE_BASE_PLDIV_CML(cpcon);
-
- value &= ~PLLE_BASE_PLDIV(0x3f);
- value |= PLLE_BASE_PLDIV(p);
-
- value &= ~PLLE_BASE_NDIV(0xff);
- value |= PLLE_BASE_NDIV(n);
-
- value &= ~PLLE_BASE_MDIV(0xff);
- value |= PLLE_BASE_MDIV(m);
-
- writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- value |= PLLE_MISC_SETUP_BASE(0x7);
- value |= PLLE_MISC_LOCK_ENABLE;
- value |= PLLE_MISC_SETUP_EXT(0);
- writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
- PLLE_SS_CNTL_BYPASS_SS;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
- value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
- writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
-
- do {
- value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
- if (value & PLLE_MISC_LOCK)
- break;
-
- udelay(2);
- } while (--timeout);
-
- if (timeout == 0) {
- error("timeout waiting for PLLE to lock");
- return -ETIMEDOUT;
- }
-
- udelay(50);
-
- value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
- value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
- value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
-
- value &= ~PLLE_SS_CNTL_SSCINC(0xff);
- value |= PLLE_SS_CNTL_SSCINC(0x01);
-
- value &= ~PLLE_SS_CNTL_SSCBYP;
- value &= ~PLLE_SS_CNTL_INTERP_RESET;
- value &= ~PLLE_SS_CNTL_BYPASS_SS;
-
- value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
- value |= PLLE_SS_CNTL_SSCMAX(0x24);
- writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
-
- return 0;
-}
diff --git a/arch/arm/cpu/tegra30-common/funcmux.c b/arch/arm/cpu/tegra30-common/funcmux.c
deleted file mode 100644
index 409335c..0000000
--- a/arch/arm/cpu/tegra30-common/funcmux.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Tegra30 high-level function multiplexing */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pinmux.h>
-
-int funcmux_select(enum periph_id id, int config)
-{
- int bad_config = config != FUNCMUX_DEFAULT;
-
- switch (id) {
- case PERIPH_ID_UART1:
- switch (config) {
- case FUNCMUX_UART1_ULPI:
- pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1,
- PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2,
- PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3,
- PMUX_FUNC_UARTA);
- pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4,
- PMUX_FUNC_UARTA);
- pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1);
- pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2);
- pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3);
- pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4);
- break;
- }
- break;
-
- /* Add other periph IDs here as needed */
-
- default:
- debug("%s: invalid periph_id %d", __func__, id);
- return -1;
- }
-
- if (bad_config) {
- debug("%s: invalid config %d for periph_id %d", __func__,
- config, id);
- return -1;
- }
- return 0;
-}
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
deleted file mode 100644
index 7eb0574..0000000
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ /dev/null
@@ -1,276 +0,0 @@
-/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-
-#define PIN(pin, f0, f1, f2, f3) \
- { \
- .funcs = { \
- PMUX_FUNC_##f0, \
- PMUX_FUNC_##f1, \
- PMUX_FUNC_##f2, \
- PMUX_FUNC_##f3, \
- }, \
- }
-
-#define PIN_RESERVED {}
-
-static const struct pmux_pingrp_desc tegra30_pingroups[] = {
- /* pin, f0, f1, f2, f3 */
- /* Offset 0x3000 */
- PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI),
- PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI),
- PIN(ULPI_CLK_PY0, SPI1, RSVD2, UARTD, ULPI),
- PIN(ULPI_DIR_PY1, SPI1, RSVD2, UARTD, ULPI),
- PIN(ULPI_NXT_PY2, SPI1, RSVD2, UARTD, ULPI),
- PIN(ULPI_STP_PY3, SPI1, RSVD2, UARTD, ULPI),
- PIN(DAP3_FS_PP0, I2S2, RSVD2, DISPLAYA, DISPLAYB),
- PIN(DAP3_DIN_PP1, I2S2, RSVD2, DISPLAYA, DISPLAYB),
- PIN(DAP3_DOUT_PP2, I2S2, RSVD2, DISPLAYA, DISPLAYB),
- PIN(DAP3_SCLK_PP3, I2S2, RSVD2, DISPLAYA, DISPLAYB),
- PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4),
- PIN(SDMMC1_CLK_PZ0, SDMMC1, RSVD2, RSVD3, UARTA),
- PIN(SDMMC1_CMD_PZ1, SDMMC1, RSVD2, RSVD3, UARTA),
- PIN(SDMMC1_DAT3_PY4, SDMMC1, RSVD2, UARTE, UARTA),
- PIN(SDMMC1_DAT2_PY5, SDMMC1, RSVD2, UARTE, UARTA),
- PIN(SDMMC1_DAT1_PY6, SDMMC1, RSVD2, UARTE, UARTA),
- PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, UARTE, UARTA),
- PIN(PV2, OWR, RSVD2, RSVD3, RSVD4),
- PIN(PV3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
- PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
- PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4),
- PIN(LCD_PWR1_PC1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_PWR2_PC6, DISPLAYA, DISPLAYB, SPI5, HDCP),
- PIN(LCD_SDIN_PZ2, DISPLAYA, DISPLAYB, SPI5, RSVD4),
- PIN(LCD_SDOUT_PN5, DISPLAYA, DISPLAYB, SPI5, HDCP),
- PIN(LCD_WR_N_PZ3, DISPLAYA, DISPLAYB, SPI5, HDCP),
- PIN(LCD_CS0_N_PN4, DISPLAYA, DISPLAYB, SPI5, RSVD4),
- PIN(LCD_DC0_PN6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_SCK_PZ4, DISPLAYA, DISPLAYB, SPI5, HDCP),
- PIN(LCD_PWR0_PB2, DISPLAYA, DISPLAYB, SPI5, HDCP),
- PIN(LCD_PCLK_PB3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_DE_PJ1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_HSYNC_PJ3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_VSYNC_PJ4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D0_PE0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D1_PE1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D2_PE2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D3_PE3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D4_PE4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D5_PE5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D6_PE6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D7_PE7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D8_PF0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D9_PF1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D10_PF2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D11_PF3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D12_PF4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D13_PF5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D14_PF6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D15_PF7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D16_PM0, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D17_PM1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D18_PM2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D19_PM3, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D20_PM4, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D21_PM5, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D22_PM6, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_D23_PM7, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_CS1_N_PW0, DISPLAYA, DISPLAYB, SPI5, RSVD4),
- PIN(LCD_M1_PW1, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(LCD_DC1_PD2, DISPLAYA, DISPLAYB, RSVD3, RSVD4),
- PIN(HDMI_INT_PN7, HDMI, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4),
- PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4),
- PIN(CRT_HSYNC_PV6, CRT, RSVD2, RSVD3, RSVD4),
- PIN(CRT_VSYNC_PV7, CRT, RSVD2, RSVD3, RSVD4),
- PIN(VI_D0_PT4, DDR, RSVD2, VI, RSVD4),
- PIN(VI_D1_PD5, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D2_PL0, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D3_PL1, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D4_PL2, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D5_PL3, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D6_PL4, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D7_PL5, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D8_PL6, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D9_PL7, DDR, SDMMC2, VI, RSVD4),
- PIN(VI_D10_PT2, DDR, RSVD2, VI, RSVD4),
- PIN(VI_D11_PT3, DDR, RSVD2, VI, RSVD4),
- PIN(VI_PCLK_PT0, RSVD1, SDMMC2, VI, RSVD4),
- PIN(VI_MCLK_PT1, VI, VI_ALT1, VI_ALT2, VI_ALT3),
- PIN(VI_VSYNC_PD6, DDR, RSVD2, VI, RSVD4),
- PIN(VI_HSYNC_PD7, DDR, RSVD2, VI, RSVD4),
- PIN(UART2_RXD_PC3, UARTB, SPDIF, UARTA, SPI4),
- PIN(UART2_TXD_PC2, UARTB, SPDIF, UARTA, SPI4),
- PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4),
- PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4),
- PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, RSVD4),
- PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, RSVD4),
- PIN(UART3_CTS_N_PA1, UARTC, RSVD2, GMI, RSVD4),
- PIN(UART3_RTS_N_PC0, UARTC, PWM0, GMI, RSVD4),
- PIN(PU0, OWR, UARTA, GMI, RSVD4),
- PIN(PU1, RSVD1, UARTA, GMI, RSVD4),
- PIN(PU2, RSVD1, UARTA, GMI, RSVD4),
- PIN(PU3, PWM0, UARTA, GMI, RSVD4),
- PIN(PU4, PWM1, UARTA, GMI, RSVD4),
- PIN(PU5, PWM2, UARTA, GMI, RSVD4),
- PIN(PU6, PWM3, UARTA, GMI, RSVD4),
- PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4),
- PIN(DAP4_FS_PP4, I2S3, RSVD2, GMI, RSVD4),
- PIN(DAP4_DIN_PP5, I2S3, RSVD2, GMI, RSVD4),
- PIN(DAP4_DOUT_PP6, I2S3, RSVD2, GMI, RSVD4),
- PIN(DAP4_SCLK_PP7, I2S3, RSVD2, GMI, RSVD4),
- PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
- PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4),
- PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT),
- PIN(GMI_IORDY_PI5, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_WAIT_PI7, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_CLK_PK1, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, DTV),
- PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, DTV),
- PIN(GMI_CS2_N_PK3, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_CS3_N_PK4, RSVD1, NAND, GMI, GMI_ALT),
- PIN(GMI_CS4_N_PK2, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SATA),
- PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, GMI_ALT),
- PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD8_PH0, PWM0, NAND, GMI, RSVD4),
- PIN(GMI_AD9_PH1, PWM1, NAND, GMI, RSVD4),
- PIN(GMI_AD10_PH2, PWM2, NAND, GMI, RSVD4),
- PIN(GMI_AD11_PH3, PWM3, NAND, GMI, RSVD4),
- PIN(GMI_AD12_PH4, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD13_PH5, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD14_PH6, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_AD15_PH7, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_A16_PJ7, UARTD, SPI4, GMI, GMI_ALT),
- PIN(GMI_A17_PB0, UARTD, SPI4, GMI, DTV),
- PIN(GMI_A18_PB1, UARTD, SPI4, GMI, DTV),
- PIN(GMI_A19_PK7, UARTD, SPI4, GMI, RSVD4),
- PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_DQS_PI2, RSVD1, NAND, GMI, RSVD4),
- PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4),
- PIN(GEN2_I2C_SCL_PT5, I2C2, HDCP, GMI, RSVD4),
- PIN(GEN2_I2C_SDA_PT6, I2C2, HDCP, GMI, RSVD4),
- PIN(SDMMC4_CLK_PCC4, INVALID, NAND, GMI, SDMMC4),
- PIN(SDMMC4_CMD_PT7, I2C3, NAND, GMI, SDMMC4),
- PIN(SDMMC4_DAT0_PAA0, UARTE, SPI3, GMI, SDMMC4),
- PIN(SDMMC4_DAT1_PAA1, UARTE, SPI3, GMI, SDMMC4),
- PIN(SDMMC4_DAT2_PAA2, UARTE, SPI3, GMI, SDMMC4),
- PIN(SDMMC4_DAT3_PAA3, UARTE, SPI3, GMI, SDMMC4),
- PIN(SDMMC4_DAT4_PAA4, I2C3, I2S4, GMI, SDMMC4),
- PIN(SDMMC4_DAT5_PAA5, VGP3, I2S4, GMI, SDMMC4),
- PIN(SDMMC4_DAT6_PAA6, VGP4, I2S4, GMI, SDMMC4),
- PIN(SDMMC4_DAT7_PAA7, VGP5, I2S4, GMI, SDMMC4),
- PIN(SDMMC4_RST_N_PCC3, VGP6, RSVD2, RSVD3, SDMMC4),
- PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC4),
- PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC4),
- PIN(PBB0, I2S4, RSVD2, RSVD3, SDMMC4),
- PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC4),
- PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC4),
- PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC4),
- PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC4),
- PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, SDMMC4),
- PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, SDMMC4),
- PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC4),
- PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4),
- PIN(JTAG_RTCK_PU7, RTCK, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4),
- PIN(KB_ROW0_PR0, KBC, NAND, RSVD3, RSVD4),
- PIN(KB_ROW1_PR1, KBC, NAND, RSVD3, RSVD4),
- PIN(KB_ROW2_PR2, KBC, NAND, RSVD3, RSVD4),
- PIN(KB_ROW3_PR3, KBC, NAND, RSVD3, INVALID),
- PIN(KB_ROW4_PR4, KBC, NAND, TRACE, RSVD4),
- PIN(KB_ROW5_PR5, KBC, NAND, TRACE, OWR),
- PIN(KB_ROW6_PR6, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW7_PR7, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW8_PS0, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW9_PS1, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW10_PS2, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW11_PS3, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW12_PS4, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW13_PS5, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW14_PS6, KBC, NAND, SDMMC2, MIO),
- PIN(KB_ROW15_PS7, KBC, NAND, SDMMC2, MIO),
- PIN(KB_COL0_PQ0, KBC, NAND, TRACE, TEST),
- PIN(KB_COL1_PQ1, KBC, NAND, TRACE, TEST),
- PIN(KB_COL2_PQ2, KBC, NAND, TRACE, RSVD4),
- PIN(KB_COL3_PQ3, KBC, NAND, TRACE, RSVD4),
- PIN(KB_COL4_PQ4, KBC, NAND, TRACE, RSVD4),
- PIN(KB_COL5_PQ5, KBC, NAND, TRACE, RSVD4),
- PIN(KB_COL6_PQ6, KBC, NAND, TRACE, MIO),
- PIN(KB_COL7_PQ7, KBC, NAND, TRACE, MIO),
- PIN(CLK_32K_OUT_PA0, BLINK, RSVD2, RSVD3, RSVD4),
- PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4),
- PIN(CORE_PWR_REQ, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
- PIN(CPU_PWR_REQ, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
- PIN(PWR_INT_N, PWR_INT_N, RSVD2, RSVD3, RSVD4),
- PIN(CLK_32K_IN, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
- PIN(OWR, OWR, CEC, RSVD3, RSVD4),
- PIN(DAP1_FS_PN0, I2S0, HDA, GMI, SDMMC2),
- PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, SDMMC2),
- PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SDMMC2),
- PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, SDMMC2),
- PIN(CLK1_REQ_PEE2, DAP, HDA, RSVD3, RSVD4),
- PIN(CLK1_OUT_PW4, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
- PIN(SPDIF_IN_PK6, SPDIF, HDA, I2C1, SDMMC2),
- PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, I2C1, SDMMC2),
- PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, GMI),
- PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, GMI),
- PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, GMI),
- PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, GMI),
- PIN(SPI2_MOSI_PX0, SPI6, SPI2, SPI3, GMI),
- PIN(SPI2_MISO_PX1, SPI6, SPI2, SPI3, GMI),
- PIN(SPI2_CS0_N_PX3, SPI6, SPI2, SPI3, GMI),
- PIN(SPI2_SCK_PX2, SPI6, SPI2, SPI3, GMI),
- PIN(SPI1_MOSI_PX4, SPI2, SPI1, SPI2_ALT, GMI),
- PIN(SPI1_SCK_PX5, SPI2, SPI1, SPI2_ALT, GMI),
- PIN(SPI1_CS0_N_PX6, SPI2, SPI1, SPI2_ALT, GMI),
- PIN(SPI1_MISO_PX7, SPI3, SPI1, SPI2_ALT, RSVD4),
- PIN(SPI2_CS1_N_PW2, SPI3, SPI2, SPI2_ALT, I2C1),
- PIN(SPI2_CS2_N_PW3, SPI3, SPI2, SPI2_ALT, I2C1),
- PIN(SDMMC3_CLK_PA6, UARTA, PWM2, SDMMC3, SPI3),
- PIN(SDMMC3_CMD_PA7, UARTA, PWM3, SDMMC3, SPI2),
- PIN(SDMMC3_DAT0_PB7, RSVD1, RSVD2, SDMMC3, SPI3),
- PIN(SDMMC3_DAT1_PB6, RSVD1, RSVD2, SDMMC3, SPI3),
- PIN(SDMMC3_DAT2_PB5, RSVD1, PWM1, SDMMC3, SPI3),
- PIN(SDMMC3_DAT3_PB4, RSVD1, PWM0, SDMMC3, SPI3),
- PIN(SDMMC3_DAT4_PD1, PWM1, SPI4, SDMMC3, SPI2),
- PIN(SDMMC3_DAT5_PD0, PWM0, SPI4, SDMMC3, SPI2),
- PIN(SDMMC3_DAT6_PD3, SPDIF, SPI4, SDMMC3, SPI2),
- PIN(SDMMC3_DAT7_PD4, SPDIF, SPI4, SDMMC3, SPI2),
- PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4),
- PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4),
- PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4),
-};
-const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups;