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author | Ye Li <ye.li@nxp.com> | 2016-02-23 15:12:17 +0800 |
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committer | Ye Li <ye.li@nxp.com> | 2017-04-05 14:04:30 +0800 |
commit | 65d4c96e79090ba4ac5cf6d1887e39826a580500 (patch) | |
tree | 43924c1043892dadf677e5b6aedac385c3d889cb /arch/arm/cpu | |
parent | 9632ebeccc34d663e21bd19f2fe62de51947296e (diff) | |
download | u-boot-imx-65d4c96e79090ba4ac5cf6d1887e39826a580500.zip u-boot-imx-65d4c96e79090ba4ac5cf6d1887e39826a580500.tar.gz u-boot-imx-65d4c96e79090ba4ac5cf6d1887e39826a580500.tar.bz2 |
MLK-12437-1 mx6sx: Add support for LVDS display
The i.MX6SX uses a LVDS bridge to mux to the LCDIF interface. Implmement a
function for this muxing. So that on 6SX we can use a LVDS display.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 763658d9b497e44b7411581da592ef5b522e9cc9)
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 61 |
1 files changed, 60 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 84bc213..4614a1f 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -850,6 +850,65 @@ int enable_lcdif_clock(u32 base_addr, bool enable) return 0; } + +int enable_lvds_bridge(u32 lcd_base_addr) +{ + u32 reg = 0; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + if (is_cpu_type(MXC_CPU_MX6SX)) { + if ((lcd_base_addr != LCDIF1_BASE_ADDR) && + (lcd_base_addr != LCDIF2_BASE_ADDR)) { + puts("Wrong LCD interface!\n"); + return -EINVAL; + } + } else { + debug("This chip not support lvds bridge!\n"); + return 0; + } + + /* Turn on LDB DI0 clocks */ + reg = readl(&imx_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &imx_ccm->CCGR3); + + /* set LDB DI0 clk select to 011 PLL2 PFD3 200M*/ + reg = readl(&imx_ccm->cs2cdr); + reg &= ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK; + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET); + writel(reg, &imx_ccm->cs2cdr); + + reg = readl(&imx_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &imx_ccm->cscmr2); + + /* set LDB DI0 clock for LCDIF PIX clock */ + reg = readl(&imx_ccm->cscdr2); + if (lcd_base_addr == LCDIF1_BASE_ADDR) { + reg &= ~MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK; + reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET); + } else { + reg &= ~MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK; + reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET); + } + writel(reg, &imx_ccm->cscdr2); + + reg = IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[6]); + + reg = readl(&iomux->gpr[5]); + if (lcd_base_addr == LCDIF1_BASE_ADDR) + reg &= ~0x8; /* MUX LVDS to LCDIF1 */ + else + reg |= 0x8; /* MUX LVDS to LCDIF2 */ + writel(reg, &iomux->gpr[5]); + + return 0; +} + #endif #ifdef CONFIG_FSL_QSPI |