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| author | Tom Rini <trini@konsulko.com> | 2015-05-05 07:00:11 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-05-05 07:00:11 -0400 |
| commit | 3f2f1a00394eb7ce7176f9d0930e40e55ba2c79c (patch) | |
| tree | c91bddf10c0a179153e674309779e0afd4ab72ae /arch/arm/cpu | |
| parent | 622da1c36aee9c39075f2109848228a5737925c0 (diff) | |
| parent | b939689c7b87773c44275a578ffc8674a867e39d (diff) | |
| download | u-boot-imx-3f2f1a00394eb7ce7176f9d0930e40e55ba2c79c.zip u-boot-imx-3f2f1a00394eb7ce7176f9d0930e40e55ba2c79c.tar.gz u-boot-imx-3f2f1a00394eb7ce7176f9d0930e40e55ba2c79c.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/cache_v7.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 0f9d837..e8ee875 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets, } } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, @@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets, } } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } static void v7_maint_dcache_level_setway(u32 level, u32 operation) @@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* DSB to make sure the operation is complete */ - CP15DSB; + DSB; } /* Invalidate TLB */ @@ -228,9 +228,9 @@ static void v7_inval_tlb(void) /* Invalidate entire instruction TLB */ asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; + DSB; /* Full system ISB - make sure the instruction stream sees it */ - CP15ISB; + ISB; } void invalidate_dcache_all(void) @@ -343,10 +343,10 @@ void invalidate_icache_all(void) asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; + DSB; /* ISB - make sure the instruction stream sees it */ - CP15ISB; + ISB; } #else void invalidate_icache_all(void) |