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authorMarc Zyngier <marc.zyngier@arm.com>2014-07-12 14:24:05 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-07-28 17:19:26 +0200
commit38510a4b34a699a534121ad3cb9096cc0fd7a86e (patch)
treeecd164a2156446379570a7fd966cde326d1a813d /arch/arm/cpu
parentecf07a7930e9e9558bff70698515279f5a2c40d4 (diff)
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ARM: HYP/non-sec: add the option for a second-stage monitor
Allow the switch to a second stage secure monitor just before switching to non-secure. This allows a resident piece of firmware to be active once the kernel has been entered (the u-boot monitor is dead anyway, its pages being reused). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv7/nonsec_virt.S13
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 2a43e3c..745670e 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -44,10 +44,19 @@ _monitor_vectors:
* ip: target PC
*/
_secure_monitor:
+#ifdef CONFIG_ARMV7_PSCI
+ ldr r5, =_psci_vectors @ Switch to the next monitor
+ mcr p15, 0, r5, c12, c0, 1
+ isb
+
+ @ Obtain a secure stack, and configure the PSCI backend
+ bl psci_arch_init
+#endif
+
mrc p15, 0, r5, c1, c1, 0 @ read SCR
- bic r5, r5, #0x4e @ clear IRQ, FIQ, EA, nET bits
+ bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
orr r5, r5, #0x31 @ enable NS, AW, FW bits
-
+ @ FIQ preserved for secure mode
mov r6, #SVC_MODE @ default mode is SVC
is_cpu_virt_capable r4
#ifdef CONFIG_ARMV7_VIRT