diff options
author | Wolfgang Denk <wd@denx.de> | 2011-09-05 14:37:30 +0200 |
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committer | Wolfgang Denk <wd@denx.de> | 2011-09-07 21:46:40 +0200 |
commit | c1f8750f9f15a81e40566f2be6fe359649e91a00 (patch) | |
tree | bbd3b2874d97975dd5a044f23821e93c95c24834 /arch/arm/cpu | |
parent | 2c650e20107917ed90a36ca574a6816fb5d3342e (diff) | |
download | u-boot-imx-c1f8750f9f15a81e40566f2be6fe359649e91a00.zip u-boot-imx-c1f8750f9f15a81e40566f2be6fe359649e91a00.tar.gz u-boot-imx-c1f8750f9f15a81e40566f2be6fe359649e91a00.tar.bz2 |
ARM: remove broken "impa7" board.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Marius Gröger <mag@sysgo.de>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/arm720t/cpu.c | 29 | ||||
-rw-r--r-- | arch/arm/cpu/arm720t/interrupts.c | 14 | ||||
-rw-r--r-- | arch/arm/cpu/arm720t/start.S | 64 |
3 files changed, 5 insertions, 102 deletions
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c index 71d8d6b..974f288 100644 --- a/arch/arm/cpu/arm720t/cpu.c +++ b/arch/arm/cpu/arm720t/cpu.c @@ -36,10 +36,6 @@ #include <asm/hardware.h> #include <asm/system.h> -#if defined(CONFIG_IMPA7) -static void cache_flush(void); -#endif - int cleanup_before_linux (void) { /* @@ -50,20 +46,7 @@ int cleanup_before_linux (void) * and we set the CPU-speed to 73 MHz - see start.S for details */ -#if defined(CONFIG_IMPA7) - disable_interrupts (); - - /* turn off I-cache */ - icache_disable(); - dcache_disable(); - - /* flush I-cache */ - cache_flush(); -#ifdef CONFIG_ARM7_REVD - /* go to high speed */ - IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; -#endif -#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) +#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) @@ -73,13 +56,3 @@ int cleanup_before_linux (void) #endif return 0; } - -#if defined(CONFIG_IMPA7) -/* flush I/D-cache */ -static void cache_flush (void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -} -#endif diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c index 3cebf11..464dd30 100644 --- a/arch/arm/cpu/arm720t/interrupts.c +++ b/arch/arm/cpu/arm720t/interrupts.c @@ -149,18 +149,6 @@ int timer_init (void) /* set timer 2 counter */ lastdec = TIMER_LOAD_VAL; -#elif defined(CONFIG_IMPA7) - /* disable all interrupts */ - IO_INTMR1 = 0; - - /* operate timer 1 in prescale mode */ - IO_SYSCON1 |= SYSCON1_TC1M; - - /* select 2kHz clock source for timer 1 */ - IO_SYSCON1 &= ~SYSCON1_TC1S; - - /* set timer 1 counter */ - lastdec = IO_TC1D = TIMER_LOAD_VAL; #elif defined(CONFIG_S3C4510B) /* configure free running timer 0 */ PUT_REG( REG_TMOD, 0x0); @@ -207,7 +195,7 @@ int timer_init (void) */ -#if defined(CONFIG_IMPA7) || defined(CONFIG_NETARM) || defined(CONFIG_LPC2292) +#if defined(CONFIG_NETARM) || defined(CONFIG_LPC2292) ulong get_timer (ulong base) { diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index f2320ee..00fa8c9 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -272,25 +272,7 @@ _dynsym_start_ofs: ************************************************************************* */ -#if defined(CONFIG_IMPA7) - -/* Interrupt-Controller base addresses */ -INTMR1: .word 0x80000280 @ 32 bit size -INTMR2: .word 0x80001280 @ 16 bit size -INTMR3: .word 0x80002280 @ 8 bit size - -/* SYSCONs */ -SYSCON1: .word 0x80000100 -SYSCON2: .word 0x80001100 -SYSCON3: .word 0x80002200 - -#define CLKCTL 0x6 /* mask */ -#define CLKCTL_18 0x0 /* 18.432 MHz */ -#define CLKCTL_36 0x2 /* 36.864 MHz */ -#define CLKCTL_49 0x4 /* 49.152 MHz */ -#define CLKCTL_73 0x6 /* 73.728 MHz */ - -#elif defined(CONFIG_LPC2292) +#if defined(CONFIG_LPC2292) PLLCFG_ADR: .word PLLCFG PLLFEED_ADR: .word PLLFEED PLLCON_ADR: .word PLLCON @@ -301,35 +283,7 @@ MEMMAP_ADR: .word MEMMAP #endif cpu_init_crit: -#if defined(CONFIG_IMPA7) - - /* - * mask all IRQs by clearing all bits in the INTMRs - */ - mov r1, #0x00 - ldr r0, INTMR1 - str r1, [r0] - ldr r0, INTMR2 - str r1, [r0] - ldr r0, INTMR3 - str r1, [r0] - - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15,0,r0,c1,c0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - mcr p15,0,r0,c1,c0 -#elif defined(CONFIG_NETARM) +#if defined(CONFIG_NETARM) /* * prior to software reset : need to set pin PORTC4 to be *HRESET */ @@ -634,19 +588,7 @@ fiq: #endif -#if defined(CONFIG_IMPA7) - .align 5 -.globl reset_cpu -reset_cpu: - mov ip, #0 - mcr p15, 0, ip, c7, c7, 0 @ invalidate cache - mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) - mrc p15, 0, ip, c1, c0, 0 @ get ctrl register - bic ip, ip, #0x000f @ ............wcam - bic ip, ip, #0x2100 @ ..v....s........ - mcr p15, 0, ip, c1, c0, 0 @ ctrl register - mov pc, r0 -#elif defined(CONFIG_NETARM) +#if defined(CONFIG_NETARM) .align 5 .globl reset_cpu reset_cpu: |