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authorWolfgang Denk <wd@denx.de>2010-08-10 23:03:15 +0200
committerWolfgang Denk <wd@denx.de>2010-08-10 23:03:15 +0200
commitb9d51fbb18097975ff86d3a7b4a21a92a1b345f0 (patch)
tree1e062ddf881089872f49fb4ea3dcfc05c439f021 /arch/arm/cpu
parent42441b8a1a3e8b42459de60bbec6833a31cd6cd5 (diff)
parentb77f380115028ef4b6cc59fc5ba332a6e31b4326 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/arm926ejs/orion5x/cpu.c40
-rw-r--r--arch/arm/cpu/armv7/mx51/timer.c2
-rw-r--r--arch/arm/cpu/armv7/omap-common/timer.c9
-rw-r--r--arch/arm/cpu/armv7/omap4/Makefile1
-rw-r--r--arch/arm/cpu/armv7/omap4/board.c11
-rw-r--r--arch/arm/cpu/armv7/omap4/mem.c45
6 files changed, 78 insertions, 30 deletions
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
index f3c1e21..3740e33 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -87,56 +87,56 @@ int orion5x_config_adr_windows(void)
(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
/* Window 0: PCIE MEM address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
ORION5X_WIN_ENABLE), &winregs[0].ctrl);
- writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base);
- writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
- writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
+ writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
+ writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
+ writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
/* Window 1: PCIE IO address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
ORION5X_WIN_ENABLE), &winregs[1].ctrl);
- writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base);
- writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
- writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
+ writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
+ writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
+ writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
/* Window 2: PCI MEM address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
ORION5X_WIN_ENABLE), &winregs[2].ctrl);
- writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base);
+ writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
/* Window 3: PCI IO address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
ORION5X_WIN_ENABLE), &winregs[3].ctrl);
- writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base);
+ writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
/* Window 4: DEV_CS0 address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
ORION5X_WIN_ENABLE), &winregs[4].ctrl);
- writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base);
+ writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
/* Window 5: DEV_CS1 address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
ORION5X_WIN_ENABLE), &winregs[5].ctrl);
- writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base);
+ writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
/* Window 6: DEV_CS2 address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
ORION5X_WIN_ENABLE), &winregs[6].ctrl);
- writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base);
+ writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
/* Window 7: BOOT Memory address space */
- writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM,
+ writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
ORION5X_WIN_ENABLE), &winregs[7].ctrl);
- writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base);
+ writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
return 0;
}
diff --git a/arch/arm/cpu/armv7/mx51/timer.c b/arch/arm/cpu/armv7/mx51/timer.c
index 81c4a06..110edbf 100644
--- a/arch/arm/cpu/armv7/mx51/timer.c
+++ b/arch/arm/cpu/armv7/mx51/timer.c
@@ -89,7 +89,7 @@ ulong get_timer_masked(void)
timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ))
- lastinc) + val;
lastinc = val;
- return val;
+ return timestamp;
}
ulong get_timer(ulong base)
diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c
index 69e285f..6b8cf7b 100644
--- a/arch/arm/cpu/armv7/omap-common/timer.c
+++ b/arch/arm/cpu/armv7/omap-common/timer.c
@@ -41,12 +41,8 @@ static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
/*
* Nothing really to do with interrupts, just starts up a counter.
- * We run the counter with 13MHz, divided by 8, resulting in timer
- * frequency of 1.625MHz. With 32bit counter register, counter
- * overflows in ~44min
*/
-/* 13MHz / 8 = 1.625MHz */
#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
#define TIMER_LOAD_VAL 0xffffffff
@@ -84,11 +80,6 @@ void set_timer(ulong t)
/* delay x useconds */
void __udelay(unsigned long usec)
{
-#if defined(CONFIG_OMAP44XX)
- /* TODO temporary hack until OMAP4 clock setup routines are present */
- if (usec > 1000)
- usec = usec/1000;
-#endif
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
unsigned long now, last = readl(&timer_base->tcrr);
diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile
index ecf64f9..d926fbb 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -28,6 +28,7 @@ LIB = $(obj)lib$(SOC).a
SOBJS += lowlevel_init.o
COBJS += board.o
+COBJS += mem.o
COBJS += sys_info.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 5bf7173..2e80d1f 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -88,3 +88,14 @@ int checkboard(void)
return 0;
}
+/*
+* This function is called by start_armboot. You can reliably use static
+* data. Any boot-time function that require static data should be
+* called from here
+*/
+int arch_cpu_init(void)
+{
+ set_muxconf_regs();
+ return 0;
+}
+
diff --git a/arch/arm/cpu/armv7/omap4/mem.c b/arch/arm/cpu/armv7/omap4/mem.c
new file mode 100644
index 0000000..878f0e3
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/mem.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/sys_proto.h>
+
+struct gpmc *gpmc_cfg;
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+ gpmc_cfg = (struct gpmc *)GPMC_BASE;
+
+ /* global settings */
+ writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
+ writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
+
+ /*
+ * Disable the GPMC0 config set by ROM code
+ * It conflicts with our MPDB (both at 0x08000000)
+ */
+ writel(0, &gpmc_cfg->cs[0].config7);
+}