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| author | Tom Warren <twarren@nvidia.com> | 2012-05-30 14:06:09 -0700 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-07-07 14:07:21 +0200 |
| commit | 76e350b7a3c568c8d27cf72f98036ec3ddb64f31 (patch) | |
| tree | 3d9f1eb6e7d14549b3e7c7559d2b2dc3ebe62e1b /arch/arm/cpu | |
| parent | f9f2f12e2cace3685ea0dbb6b6d78789fb75f043 (diff) | |
| download | u-boot-imx-76e350b7a3c568c8d27cf72f98036ec3ddb64f31.zip u-boot-imx-76e350b7a3c568c8d27cf72f98036ec3ddb64f31.tar.gz u-boot-imx-76e350b7a3c568c8d27cf72f98036ec3ddb64f31.tar.bz2 | |
arm: Tegra: Use ODMDATA from BCT in IRAM
Walk the BIT and BCT to find the ODMDATA word in the
CustomerData field and put it into Scratch20 reg for
use by kernel, etc.
Built all Tegra builds OK; Booted on Seaboard and saw
ODMDATA in PMC scratch20 was the same as the value in my
burn-u-boot.sh file (0x300D8011). NOTE: All flash utilities
will have to specify the odmdata (nvflash --odmdata n) on
the command line or via a cfg file, or built in to their
BCT.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/tegra2/ap20.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index 24e582d..1aad387 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -314,9 +314,28 @@ void enable_scu(void) writel(reg, &scu->scu_ctrl); } +static u32 get_odmdata(void) +{ + /* + * ODMDATA is stored in the BCT in IRAM by the BootROM. + * The BCT start and size are stored in the BIT in IRAM. + * Read the data @ bct_start + (bct_size - 12). This works + * on T20 and T30 BCTs, which are locked down. If this changes + * in new chips (T114, etc.), we can revisit this algorithm. + */ + + u32 bct_start, odmdata; + + bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR); + odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); + + return odmdata; +} + void init_pmc_scratch(void) { struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + u32 odmdata; int i; /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ @@ -324,7 +343,8 @@ void init_pmc_scratch(void) writel(0, &pmc->pmc_scratch1+i); /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ - writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20); + odmdata = get_odmdata(); + writel(odmdata, &pmc->pmc_scratch20); #ifdef CONFIG_TEGRA2_LP0 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ |