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author | Stephen Warren <swarren@nvidia.com> | 2014-01-24 12:46:09 -0700 |
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committer | Tom Warren <twarren@nvidia.com> | 2014-02-03 09:46:46 -0700 |
commit | 41447fb2cf2fbeb448b1d606cb13ca1ae84f9737 (patch) | |
tree | f34a339f0750f74bee9bb2b8d86ee23b40300c51 /arch/arm/cpu | |
parent | cad38a57d3c4505d560f46bdc2640846656d0efb (diff) | |
download | u-boot-imx-41447fb2cf2fbeb448b1d606cb13ca1ae84f9737.zip u-boot-imx-41447fb2cf2fbeb448b1d606cb13ca1ae84f9737.tar.gz u-boot-imx-41447fb2cf2fbeb448b1d606cb13ca1ae84f9737.tar.bz2 |
ARM: tegra: enable PLLX only once it's been fully configured
This programming sequence is correct per Jimmy Zhang, and makes sense
too!
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/arm720t/tegra-common/cpu.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 03f67b1..322ce10 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -144,18 +144,23 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, reg |= (1 << PLL_DCCON_SHIFT); writel(reg, &pll->pll_misc); - /* Enable PLLX */ - reg = readl(&pll->pll_base); - reg |= PLL_ENABLE_MASK; - /* Disable BYPASS */ + reg = readl(&pll->pll_base); reg &= ~PLL_BYPASS_MASK; writel(reg, &pll->pll_base); + debug("pllx_set_rate: base = 0x%08X\n", reg); /* Set lock_enable to PLLX_MISC */ reg = readl(&pll->pll_misc); reg |= PLL_LOCK_ENABLE_MASK; writel(reg, &pll->pll_misc); + debug("pllx_set_rate: misc = 0x%08X\n", reg); + + /* Enable PLLX last, once it's all configured */ + reg = readl(&pll->pll_base); + reg |= PLL_ENABLE_MASK; + writel(reg, &pll->pll_base); + debug("pllx_set_rate: base final = 0x%08X\n", reg); return 0; } |