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authorTroy Kisky <troy.kisky@boundarydevices.com>2012-10-23 10:57:46 +0000
committerStefano Babic <sbabic@denx.de>2012-11-10 08:15:40 +0100
commit20332a066aff98f39419495821e14edd10b2a3f8 (patch)
treea50b4c4ee5150a4d3b127664ddc063fc0f8cc2b6 /arch/arm/cpu
parent3e4d27b06d7484040355e22eec2cbce7335d6dab (diff)
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mx6: soc: update get_cpu_rev and get_imx_type for mx6solo/sololite
Previously, the same value was returned for both mx6dl and mx6solo. Check number of processors to differeniate. Also, a freescale patch says that sololite has its cpu/rev stored at 0x280 instead of 0x260. I don't have a sololite to verify. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c32
1 files changed, 24 insertions, 8 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index bc65767..a8aad5d 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -31,17 +31,33 @@
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
+struct scu_regs {
+ u32 ctrl;
+ u32 config;
+ u32 status;
+ u32 invalidate;
+ u32 fpga_rev;
+};
+
u32 get_cpu_rev(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int reg = readl(&anatop->digprog);
-
- /* Read mx6 variant: quad, dual or solo */
- int system_rev = (reg >> 4) & 0xFF000;
- /* Read mx6 silicon revision */
- system_rev |= (reg & 0xFF) + 0x10;
-
- return system_rev;
+ u32 reg = readl(&anatop->digprog_sololite);
+ u32 type = ((reg >> 16) & 0xff);
+
+ if (type != MXC_CPU_MX6SL) {
+ reg = readl(&anatop->digprog);
+ type = ((reg >> 16) & 0xff);
+ if (type == MXC_CPU_MX6DL) {
+ struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+ u32 cfg = readl(&scu->config) & 3;
+
+ if (!cfg)
+ type = MXC_CPU_MX6SOLO;
+ }
+ }
+ reg &= 0xff; /* mx6 silicon revision */
+ return (type << 12) | (reg + 0x10);
}
void init_aips(void)