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authorTom Rini <trini@ti.com>2012-07-03 08:51:34 -0700
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-01 14:58:12 +0200
commitfda35eb982a6846c776bd94ba4b24bf43cbfe328 (patch)
tree654b377d8e836030fcecf20889dbb4c74315e356 /arch/arm/cpu
parentbce58fece5bcf3f18edbb85da651014a07203c72 (diff)
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am33xx: Pass to config_ddr the type of memory that is connected
We need to pass in the type of memory that is connected to the board. The only reliable way to do this is to know what type of board we are running on (which later will be knowable in s_init()). For now, pass in the value of DDR2. Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c3
-rw-r--r--arch/arm/cpu/armv7/am33xx/emif4.c38
2 files changed, 23 insertions, 18 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 1104655..ec542fd 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -27,6 +27,7 @@
#include <asm/arch/common_def.h>
#include <asm/io.h>
#include <asm/omap_common.h>
+#include <asm/emif.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -107,7 +108,7 @@ void s_init(void)
preloader_console_init();
- config_ddr();
+ config_ddr(EMIF_REG_SDRAM_TYPE_DDR2);
#endif
/* Enable MMC0 */
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 26c6a66..9b1a80c 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -22,6 +22,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
+#include <asm/emif.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -29,7 +30,6 @@ struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
-
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
@@ -143,33 +143,37 @@ static void config_emif_ddr2(void)
printf("Couldn't configure SDRAM\n");
}
-void config_ddr(void)
+void config_ddr(short ddr_type)
{
struct ddr_ioctrl ioctrl;
enable_emif_clocks();
- config_vtp();
+ if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
+ config_vtp();
- config_cmd_ctrl(&ddr2_cmd_ctrl_data);
+ config_cmd_ctrl(&ddr2_cmd_ctrl_data);
- config_ddr_data(0, &ddr2_data);
- config_ddr_data(1, &ddr2_data);
+ config_ddr_data(0, &ddr2_data);
+ config_ddr_data(1, &ddr2_data);
- writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
- writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
+ writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
+ writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
- ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
- ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
- ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
- ioctrl.data1ctl = DDR_IOCTRL_VALUE;
- ioctrl.data2ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
+ ioctrl.data1ctl = DDR_IOCTRL_VALUE;
+ ioctrl.data2ctl = DDR_IOCTRL_VALUE;
- config_io_ctrl(&ioctrl);
+ config_io_ctrl(&ioctrl);
- writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
- writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);
+ writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff,
+ &ddrctrl->ddrioctrl);
+ writel(readl(&ddrctrl->ddrckectrl) | 0x00000001,
+ &ddrctrl->ddrckectrl);
- config_emif_ddr2();
+ config_emif_ddr2();
+ }
}
#endif