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| author | Rajeshwari Shinde <rajeshwari.s@samsung.com> | 2012-10-28 19:32:54 +0000 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2012-11-15 21:08:20 +0900 |
| commit | fbb574330885d9f48c9e846970a912912f23f4fd (patch) | |
| tree | 2297661703251aec231c60247d7fbd5f4b77e79a /arch/arm/cpu | |
| parent | 363647143cafd6cbb8e1d9b0753cce9c5e89c535 (diff) | |
| download | u-boot-imx-fbb574330885d9f48c9e846970a912912f23f4fd.zip u-boot-imx-fbb574330885d9f48c9e846970a912912f23f4fd.tar.gz u-boot-imx-fbb574330885d9f48c9e846970a912912f23f4fd.tar.bz2 | |
EXYNOS5: Add pinmux support for SPI
This patch adds pinmux support for SPI channels
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/pinmux.c | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index d99daa0..f02f441 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -112,6 +112,7 @@ static int exynos5_mmc_config(int peripheral, int flags) s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); } + return 0; } @@ -240,6 +241,49 @@ static void exynos5_i2s_config(int peripheral) s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02)); } +void exynos5_spi_config(int peripheral) +{ + int cfg = 0, pin = 0, i; + struct s5p_gpio_bank *bank = NULL; + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct exynos5_gpio_part2 *gpio2 = + (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); + + switch (peripheral) { + case PERIPH_ID_SPI0: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI1: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 4; + break; + case PERIPH_ID_SPI2: + bank = &gpio1->b1; + cfg = GPIO_FUNC(0x5); + pin = 1; + break; + case PERIPH_ID_SPI3: + bank = &gpio2->f1; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI4: + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); + } + break; + } + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + s5p_gpio_cfg_pin(bank, i, cfg); + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -270,6 +314,13 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2S1: exynos5_i2s_config(peripheral); break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5_spi_config(peripheral); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; |