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authorLokesh Vutla <lokeshvutla@ti.com>2012-05-22 00:03:23 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:23 +0200
commiteb4e18e89eec8d63f064cb5ec597ba9387fe4987 (patch)
tree1dac807d2ea6ba79cff99637c7b2a474331d47fc /arch/arm/cpu
parent0a0bf7b217660589b846bd5d6fcebc1deef20971 (diff)
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OMAP5: Configure the io settings for omap5432 uevm board
This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv7/omap5/hwinit.c98
1 files changed, 79 insertions, 19 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index e2f76a1..df0b760 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -52,6 +52,81 @@ static struct gpio_bank gpio_bank_54xx[6] = {
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
#ifdef CONFIG_SPL_BUILD
+/* LPDDR2 specific IO settings */
+static void io_settings_lpddr2(void)
+{
+ struct omap_sys_ctrl_regs *ioregs_base =
+ (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch1_0));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch1_1));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch2_0));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ &(ioregs_base->control_ddrch2_1));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ &(ioregs_base->control_lpddr2ch1_0));
+ writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ &(ioregs_base->control_lpddr2ch1_1));
+ writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+ &(ioregs_base->control_ddrio_0));
+ writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+ &(ioregs_base->control_ddrio_1));
+ writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+ &(ioregs_base->control_ddrio_2));
+}
+
+/* DDR3 specific IO settings */
+static void io_settings_ddr3(void)
+{
+ u32 io_settings = 0;
+ struct omap_sys_ctrl_regs *ioregs_base =
+ (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+ writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddr3ch1_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch1_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch1_1));
+
+ writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddr3ch2_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch2_0));
+ writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ &(ioregs_base->control_ddrch2_1));
+
+ writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+ &(ioregs_base->control_ddrio_0));
+ writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+ &(ioregs_base->control_ddrio_1));
+ writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+ &(ioregs_base->control_ddrio_2));
+
+ /* omap5432 does not use lpddr2 */
+ writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
+ writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
+
+ writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+ &(ioregs_base->control_emif1_sdram_config_ext));
+ writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+ &(ioregs_base->control_emif2_sdram_config_ext));
+
+ /* Disable DLL select */
+ io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
+ & 0xFFEFFFFF);
+ writel(io_settings,
+ &(ioregs_base->control_port_emif1_sdram_config));
+
+ io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
+ & 0xFFEFFFFF);
+ writel(io_settings,
+ &(ioregs_base->control_port_emif2_sdram_config));
+}
+
/*
* Some tuning of IOs for optimal power and performance
*/
@@ -115,25 +190,10 @@ void do_io_settings(void)
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
- /* LPDDR2 io settings */
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch1_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch1_1));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch2_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch2_1));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- &(ioregs_base->control_lpddr2ch1_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- &(ioregs_base->control_lpddr2ch1_1));
- writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
- &(ioregs_base->control_ddrio_0));
- writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
- &(ioregs_base->control_ddrio_1));
- writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
- &(ioregs_base->control_ddrio_2));
+ if (omap_revision() <= OMAP5430_ES1_0)
+ io_settings_lpddr2();
+ else
+ io_settings_ddr3();
/* Efuse settings */
writel(EFUSE_1, &(ioregs_base->control_efuse_1));