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authorMarcel Ziswiler <marcel@ziswiler.com>2014-10-10 23:32:32 +0200
committerTom Warren <twarren@nvidia.com>2014-10-22 09:30:55 -0700
commit8c33ba7b1d85ea98d39171523858bbd7cd44f166 (patch)
tree5d52fd65356e5647d4d8c67f321f12569d19430e /arch/arm/cpu
parent4dab5549a85d695d4a2aa9b5afd096d6b56663c9 (diff)
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ARM: tegra: Use mem size from MC in combination with get_ram_size()
On popular request this now completes the Warren's work started for TK1: aeb3fcb35956461077804720b8a252d50758d7e0 ARM: tegra: Use mem size from MC rather than ODMDATA In addition to the move of using the Tegra memory controller (MC) register rather than ODMDATA for T20, T30 and T114 as well it further uses the generic get_ram_size() function (see "common/memsize.c") <supposed to be used in each and every U-Boot port>TM. Added benefit is that it should <catch 99% of hardware related (i. e. reliably reproducible) memory errors> as well. Thoroughly tested on the various Toradex line of Tegra modules available which unfortunately does not include T114 and T124 (yet at least) plus on the Jetson TK1. Based-on-work-by: Stephen Warren <swarren@nvidia.com> Based-on-work-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/tegra-common/board.c64
1 files changed, 13 insertions, 51 deletions
diff --git a/arch/arm/cpu/tegra-common/board.c b/arch/arm/cpu/tegra-common/board.c
index 433da09..b6a84a5 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/cpu/tegra-common/board.c
@@ -9,6 +9,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
+#include <asm/arch/mc.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/pmc.h>
@@ -27,55 +28,6 @@ enum {
UART_COUNT = 5,
};
-#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
- defined(CONFIG_TEGRA114)
-/*
- * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
- * so we are using this value to identify memory size.
- */
-unsigned int query_sdram_size(void)
-{
- struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- reg = readl(&pmc->pmc_scratch20);
- debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
-
-#if defined(CONFIG_TEGRA20)
- /* bits 30:28 in OdmData are used for RAM size on T20 */
- reg &= 0x70000000;
-
- switch ((reg) >> 28) {
- case 1:
- return 0x10000000; /* 256 MB */
- case 0:
- case 2:
- default:
- return 0x20000000; /* 512 MB */
- case 3:
- return 0x40000000; /* 1GB */
- }
-#else /* Tegra30/Tegra114 */
- /* bits 31:28 in OdmData are used for RAM size on T30 */
- switch ((reg) >> 28) {
- case 0:
- case 1:
- default:
- return 0x10000000; /* 256 MB */
- case 2:
- return 0x20000000; /* 512 MB */
- case 3:
- return 0x30000000; /* 768 MB */
- case 4:
- return 0x40000000; /* 1GB */
- case 8:
- return 0x7ff00000; /* 2GB - 1MB */
- }
-#endif
-}
-#else
-#include <asm/arch/mc.h>
-
/* Read the RAM size directly from the memory controller */
unsigned int query_sdram_size(void)
{
@@ -83,12 +35,22 @@ unsigned int query_sdram_size(void)
u32 size_mb;
size_mb = readl(&mc->mc_emem_cfg);
+#if defined(CONFIG_TEGRA20)
+ debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", size_mb);
+ size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024);
+#else
debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", size_mb);
+ size_mb = get_ram_size((void *)PHYS_SDRAM_1, size_mb * 1024 * 1024);
+#endif
- return size_mb * 1024 * 1024;
-}
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
+ /* External memory limited to 2047 MB due to IROM/HI-VEC */
+ if (size_mb == SZ_2G) size_mb -= SZ_1M;
#endif
+ return size_mb;
+}
+
int dram_init(void)
{
/* We do not initialise DRAM here. We just query the size */