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authorMikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>2012-07-09 08:52:41 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-01 14:58:10 +0200
commit89473d233f0d8ef74c6aac37fe3258ef3d3efc06 (patch)
treec798a414e8c103be95166def21606b5179f44c17 /arch/arm/cpu
parentc50afc1dab78a1a72bc37b60d97864e56b52cc5c (diff)
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arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138
follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of OMAP-L138 DSP+ARM Processor Technical Reference Manual Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c26
1 files changed, 19 insertions, 7 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index df7d6a2..ff2e2e3 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -190,13 +190,21 @@ int da850_ddr_setup(void)
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
-
- setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
}
-
+ setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
- clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
- (1 << DDR_SLEW_CMOSEN_BIT));
+
+ if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
+ /* DDR2 */
+ clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
+ (1 << DDR_SLEW_DDR_PDENA_BIT) |
+ (1 << DDR_SLEW_CMOSEN_BIT));
+ } else {
+ /* MOBILE DDR */
+ setbits_le32(&davinci_syscfg1_regs->ddr_slew,
+ (1 << DDR_SLEW_DDR_PDENA_BIT) |
+ (1 << DDR_SLEW_CMOSEN_BIT));
+ }
/*
* SDRAM Configuration Register (SDCR):
@@ -216,7 +224,11 @@ int da850_ddr_setup(void)
writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
/* write memory configuration and timing */
- writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
+ if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
+ /* MOBILE DDR only*/
+ writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+ &dv_ddr2_regs_ctrl->sdbcr2);
+ }
writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
@@ -240,7 +252,7 @@ int da850_ddr_setup(void)
/* disable self refresh */
clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
- DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
+ DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
return 0;