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author | Peng Fan <peng.fan@nxp.com> | 2015-12-23 10:52:01 +0800 |
---|---|---|
committer | Peng Fan <peng.fan@nxp.com> | 2015-12-23 10:52:01 +0800 |
commit | 5642edac6b797908cd2f30d1e0a6ad099fa95683 (patch) | |
tree | 519a55e806dc77f000d056a7ebbdc72f7bae8923 /arch/arm/cpu | |
parent | a2b6f031be1190f0c23138edf8733429e524a0ad (diff) | |
download | u-boot-imx-5642edac6b797908cd2f30d1e0a6ad099fa95683.zip u-boot-imx-5642edac6b797908cd2f30d1e0a6ad099fa95683.tar.gz u-boot-imx-5642edac6b797908cd2f30d1e0a6ad099fa95683.tar.bz2 |
MLK-12066 imx: mx7: default enable MDIO open drain
The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/armv7/mx7/soc.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index 58621ce..d718e67 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -170,6 +170,24 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog4->wmcr); } +static void imx_enet_mdio_fixup(void) +{ + struct iomuxc_gpr_base_regs *gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* + * The management data input/output (MDIO) requires open-drain, + * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports + * this feature. So to TO1.1, need to enable open drain by setting + * bits GPR0[8:7]. + */ + + if (is_soc_rev(CHIP_REV_1_1) >= 0) { + setbits_le32(&gpr_regs->gpr[0], + IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK); + } +} + static void set_epdc_qos(void) { #define REGS_QOS_BASE QOSC_IPS_BASE_ADDR @@ -208,6 +226,8 @@ int arch_cpu_init(void) imx_set_pcie_phy_power_down(); + imx_enet_mdio_fixup(); + #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ mxs_dma_init(); |