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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-03-19 10:10:07 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 14:40:29 +0800 |
| commit | 5028519b434d5dfbe53c48ac4b115ff8b69bbac7 (patch) | |
| tree | 32b3239b7d770dfee81f21530afb2289c7cf4ade /arch/arm/cpu | |
| parent | c0a8bf9ce4e747cac85c308658e0dbea0de448e7 (diff) | |
| download | u-boot-imx-5028519b434d5dfbe53c48ac4b115ff8b69bbac7.zip u-boot-imx-5028519b434d5dfbe53c48ac4b115ff8b69bbac7.tar.gz u-boot-imx-5028519b434d5dfbe53c48ac4b115ff8b69bbac7.tar.bz2 | |
MLK-10774-2 HDMI: splash screen function enhancement
-Change HDMI video mode to VGA.
-Add pixel clock fraction part setting in IPU driver,
fix video mode timing issue.
-Add overflow state clear workaround,
fix kernel hang in HDMI driver issue.
-Correct IPU clock to 264MHz.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
(cherry picked from commit 45d532a0237f5baf2ec95b4364ec5bc94d312689)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 0d1801c..06a9e6d 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -638,7 +638,8 @@ void imx_setup_hdmi(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; - int reg; + int reg, count; + u8 val; /* Turn on HDMI PHY clock */ reg = readl(&mxc_ccm->CCGR2); @@ -655,6 +656,15 @@ void imx_setup_hdmi(void) |(CHSCCDR_IPU_PRE_CLK_540M_PFD << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); writel(reg, &mxc_ccm->chsccdr); + + /* Workaround to clear the overflow condition */ + if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { + /* TMDS software reset */ + writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); + val = readb(&hdmi->fc_invidconf); + for (count = 0 ; count < 5 ; count++) + writeb(val, &hdmi->fc_invidconf); + } } #endif |