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| author | Tom Rini <trini@ti.com> | 2013-07-18 15:13:02 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-07-30 09:21:41 -0400 |
| commit | 392bba4ad0049832f50eb368a04992f9719744b0 (patch) | |
| tree | 6379459fe781ebbd3e3ed8ff2297f5e724d6678a /arch/arm/cpu | |
| parent | ace4275eb33b7833d96fa2db02d253e06cc1a734 (diff) | |
| download | u-boot-imx-392bba4ad0049832f50eb368a04992f9719744b0.zip u-boot-imx-392bba4ad0049832f50eb368a04992f9719744b0.tar.gz u-boot-imx-392bba4ad0049832f50eb368a04992f9719744b0.tar.bz2 | |
am33xx: Correct gpmc_cfg->irqstatus/enable
Based on our usage of the GPMC, either with NOR or NAND we do not need
to be setting the irqstatus or irqenable bits and should clear them like
we have historically.
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/mem.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index f81c9a8..03e8c66 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -69,8 +69,8 @@ void gpmc_init(void) #endif /* global settings */ writel(0x00000008, &gpmc_cfg->sysconfig); - writel(0x00000100, &gpmc_cfg->irqstatus); - writel(0x00000100, &gpmc_cfg->irqenable); + writel(0x00000000, &gpmc_cfg->irqstatus); + writel(0x00000000, &gpmc_cfg->irqenable); writel(0x00000012, &gpmc_cfg->config); /* * Disable the GPMC0 config set by ROM code |