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authorHans de Goede <hdegoede@redhat.com>2014-11-08 14:07:27 +0100
committerHans de Goede <hdegoede@redhat.com>2014-11-25 13:38:46 +0100
commit0bd51251331a341dae8c19ae2e36a3262ae2ef72 (patch)
tree70e469f8bc5c21526dddc65a60eefd1985fd17b4 /arch/arm/cpu
parent9d4b7d0bc83992277d4baad16bdc19624f28c51c (diff)
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sunxi: Add video pll clock functions
This is a preparation patch for adding support for HDMI out. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv7/sunxi/clock_sun4i.c27
-rw-r--r--arch/arm/cpu/armv7/sunxi/clock_sun6i.c29
2 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index a0e49d1..49f4032 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -180,6 +180,21 @@ void clock_set_pll1(unsigned int hz)
}
#endif
+void clock_set_pll3(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (clk == 0) {
+ clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
+ return;
+ }
+
+ /* PLL3 rate = 3000000 * m */
+ writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+ CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);
+}
+
unsigned int clock_get_pll5p(void)
{
struct sunxi_ccm_reg *const ccm =
@@ -200,3 +215,15 @@ unsigned int clock_get_pll6(void)
int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
return 24000000 * n * k / 2;
}
+
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
+{
+ int pll = clock_get_pll5p();
+ int div = 1;
+
+ while ((pll / div) > hz)
+ div++;
+
+ writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P |
+ CCM_DE_CTRL_M(div), clk_cfg);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 16ab6f3..8e949c6 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -127,6 +127,23 @@ void clock_set_pll1(unsigned int clk)
}
#endif
+void clock_set_pll3(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
+
+ if (clk == 0) {
+ clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
+ return;
+ }
+
+ /* PLL3 rate = 24000000 * n / m */
+ writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+ CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
+ &ccm->pll3_cfg);
+}
+
void clock_set_pll5(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
@@ -151,3 +168,15 @@ unsigned int clock_get_pll6(void)
int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
return 24000000 * n * k / 2;
}
+
+void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
+{
+ int pll = clock_get_pll6() * 2;
+ int div = 1;
+
+ while ((pll / div) > hz)
+ div++;
+
+ writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
+ clk_cfg);
+}