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| author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2011-09-23 04:29:15 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-10-27 21:56:34 +0200 |
| commit | 9e2538e11fc87fb51cfde707fd5ffae086f1b467 (patch) | |
| tree | 75cc65e733760507bdbdf2632dad4649d3e4a640 /arch/arm/cpu | |
| parent | 53430a4f251eacc32ada54b56258cc18856d0d8e (diff) | |
| download | u-boot-imx-9e2538e11fc87fb51cfde707fd5ffae086f1b467.zip u-boot-imx-9e2538e11fc87fb51cfde707fd5ffae086f1b467.tar.gz u-boot-imx-9e2538e11fc87fb51cfde707fd5ffae086f1b467.tar.bz2 | |
DaVinci: correct MDSTAT.STATE mask
MDSTAT.STATE occupies bits 0..5 according to all available documentation, so fix
the mask which previously was leaving out the intermediate state indicator bit.
While at it, introduce two #define's for that mask -- unfortunately, we can't
use a single #define as the assembly code can't include <asm/arch/hardware.h>
due to C-specfic constructs in it.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/psc.c | 4 |
2 files changed, 7 insertions, 5 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S index 0a4b2cf..7a169b1 100644 --- a/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S @@ -45,6 +45,8 @@ #include <config.h> +#define MDSTAT_STATE 0x3f + .globl lowlevel_init lowlevel_init: @@ -268,7 +270,7 @@ checkStatClkStop: checkDDRStatClkStop: ldr r6, MDSTAT_DDR2 ldr r7, [r6] - and r7, r7, $0x1f + and r7, r7, $MDSTAT_STATE cmp r7, $0x03 bne checkDDRStatClkStop @@ -343,7 +345,7 @@ checkStatClkStop2: checkDDRStatClkStop2: ldr r6, MDSTAT_DDR2 ldr r7, [r6] - and r7, r7, $0x1f + and r7, r7, $MDSTAT_STATE cmp r7, $0x01 bne checkDDRStatClkStop2 @@ -374,7 +376,7 @@ checkStatClkEn2: checkDDRStatClkEn2: ldr r6, MDSTAT_DDR2 ldr r7, [r6] - and r7, r7, $0x1f + and r7, r7, $MDSTAT_STATE cmp r7, $0x03 bne checkDDRStatClkEn2 diff --git a/arch/arm/cpu/arm926ejs/davinci/psc.c b/arch/arm/cpu/arm926ejs/davinci/psc.c index 8273a7f..707fa47 100644 --- a/arch/arm/cpu/arm926ejs/davinci/psc.c +++ b/arch/arm/cpu/arm926ejs/davinci/psc.c @@ -83,7 +83,7 @@ void lpsc_on(unsigned int id) while (readl(ptstat) & 0x01) continue; - if ((readl(mdstat) & 0x1f) == 0x03) + if ((readl(mdstat) & PSC_MDSTAT_STATE) == 0x03) return; /* Already on and enabled */ writel(readl(mdctl) | 0x03, mdctl); @@ -114,7 +114,7 @@ void lpsc_on(unsigned int id) while (readl(ptstat) & 0x01) continue; - while ((readl(mdstat) & 0x1f) != 0x03) + while ((readl(mdstat) & PSC_MDSTAT_STATE) != 0x03) continue; } |