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| author | Hadli, Manjunath <manjunath.hadli@ti.com> | 2012-02-06 00:30:44 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-12 10:11:32 +0100 |
| commit | 8f5d468721ef3931e4c6f9c6555348f26acdec19 (patch) | |
| tree | 991231570cd059ac3c5dd545648c0619421aa01e /arch/arm/cpu | |
| parent | 6678cebc09226f9d34fb7e5e0631d0009689918b (diff) | |
| download | u-boot-imx-8f5d468721ef3931e4c6f9c6555348f26acdec19.zip u-boot-imx-8f5d468721ef3931e4c6f9c6555348f26acdec19.tar.gz u-boot-imx-8f5d468721ef3931e4c6f9c6555348f26acdec19.tar.bz2 | |
davinci: add support for printing clock frequency
add support for printing various clock frequency info found
in SOC such as ARM core frequency, DSP core frequency and DDR
frequency as part of bdinfo command.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/davinci/cpu.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 1735555..b3c9fb7 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -25,6 +25,8 @@ #include <asm/arch/hardware.h> #include <asm/io.h> +DECLARE_GLOBAL_DATA_PTR; + /* offsets from PLL controller base */ #define PLLC_PLLCTL 0x100 #define PLLC_PLLM 0x110 @@ -187,6 +189,36 @@ unsigned int davinci_clk_get(unsigned int div) #endif #endif /* !CONFIG_SOC_DA8XX */ +int set_cpu_clk_info(void) +{ +#ifdef CONFIG_SOC_DA8XX + gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; + /* DDR PHY uses an x2 input clock */ + gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; +#else + + unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; +#if defined(CONFIG_SOC_DM365) + pllbase = DAVINCI_PLL_CNTRL1_BASE; +#endif + gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV); + +#ifdef DSP_PLLDIV + gd->bd->bi_dsp_freq = + pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV); +#else + gd->bd->bi_dsp_freq = 0; +#endif + + pllbase = DAVINCI_PLL_CNTRL1_BASE; +#if defined(CONFIG_SOC_DM365) + pllbase = DAVINCI_PLL_CNTRL0_BASE; +#endif + gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2; +#endif + return 0; +} + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() |