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| author | Ye.Li <Ye.Li@freescale.com> | 2014-08-20 17:18:24 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-09-09 16:30:40 +0200 |
| commit | 4aa7ac30a7173934f32db466bd4592cd292e7cc9 (patch) | |
| tree | 14572029507d437b8ddf842bd1d66c4b2ad233e5 /arch/arm/cpu | |
| parent | dc73cbe7b05851a3ff76beabdc0589d2b3ebb9a3 (diff) | |
| download | u-boot-imx-4aa7ac30a7173934f32db466bd4592cd292e7cc9.zip u-boot-imx-4aa7ac30a7173934f32db466bd4592cd292e7cc9.tar.gz u-boot-imx-4aa7ac30a7173934f32db466bd4592cd292e7cc9.tar.bz2 | |
iMX6: Disable the L2 before chaning the PL310 latency
The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.
But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.
Signed-off-by: Ye.Li <Ye.Li@freescale.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index ac84a1f..be4bf24 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -430,6 +430,9 @@ void v7_outer_cache_enable(void) } #endif + /* Must disable the L2 before changing the latency parameters */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + writel(0x132, &pl310->pl310_tag_latency_ctrl); writel(0x132, &pl310->pl310_data_latency_ctrl); |