ARM: tegra: pinctrl: remove duplication

Much of arch/arm/cpu/tegra*-common/pinmux.c is identical. Remove the
duplication by creating pinmux-common.c for all the identical code.

This leaves:
* arch/arm/include/asm/arch-tegra*/pinmux.h defining only the names of
  the various pins/pin groups, drive groups, and mux functions.
* arch/arm/cpu/tegra*-common/pinmux.c containing only the lookup table
  stating which pin groups support which mux functions.

The code in pinmux-common.c is semantically identical to that in the
various original pinmux.c, but had some consistency and cleanup fixes
applied during migration.

I removed the definition of struct pmux_tri_ctlr, since this is different
between SoCs (especially Tegra20 vs all others), and it's much simpler to
deal with this via the new REG/MUX_REG/... defines. spl.c, warmboot.c,
and warmboot_avp.c needed updates due to this, since they previously
hijacked this struct to encode the location of some non-pinmux registers.
Now, that code simply calculates these register addresses directly using
simple and obvious math. I like this method better irrespective of the
pinmux code cleanup anyway.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

1 files changed, 3 insertions, 397 deletions

diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
index 8eca0dd..a12b076 100644
--- a/arch/arm/cpu/tegra30-common/pinmux.c
+++ b/arch/arm/cpu/tegra30-common/pinmux.c
@@ -18,39 +18,10 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/tegra.h>
 #include <asm/arch/pinmux.h>
 
-struct tegra_pingroup_desc {
-	const char *name;
-	enum pmux_func funcs[4];
-	enum pmux_pin_io io;
-};
-
-#define PMUX_MUXCTL_SHIFT	0
-#define PMUX_PULL_SHIFT		2
-#define PMUX_TRISTATE_SHIFT	4
-#define PMUX_TRISTATE_MASK	(1 << PMUX_TRISTATE_SHIFT)
-#define PMUX_IO_SHIFT		5
-#define PMUX_OD_SHIFT		6
-#define PMUX_LOCK_SHIFT		7
-#define PMUX_IO_RESET_SHIFT	8
-
-#define PGRP_HSM_SHIFT		2
-#define PGRP_SCHMT_SHIFT	3
-#define PGRP_LPMD_SHIFT		4
-#define PGRP_LPMD_MASK		(3 << PGRP_LPMD_SHIFT)
-#define PGRP_DRVDN_SHIFT	12
-#define PGRP_DRVDN_MASK		(0x7F << PGRP_DRVDN_SHIFT)
-#define PGRP_DRVUP_SHIFT	20
-#define PGRP_DRVUP_MASK		(0x7F << PGRP_DRVUP_SHIFT)
-#define PGRP_SLWR_SHIFT		28
-#define PGRP_SLWR_MASK		(3 << PGRP_SLWR_SHIFT)
-#define PGRP_SLWF_SHIFT		30
-#define PGRP_SLWF_MASK		(3 << PGRP_SLWF_SHIFT)
-
 /* Convenient macro for defining pin group properties */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, iod)	\
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod)		\
 	{						\
 		.funcs = {				\
 			PMUX_FUNC_ ## f0,		\
@@ -58,7 +29,6 @@ struct tegra_pingroup_desc {
 			PMUX_FUNC_ ## f2,		\
 			PMUX_FUNC_ ## f3,		\
 		},					\
-		.io = PMUX_PIN_ ## iod,			\
 	}
 
 /* Input and output pins */
@@ -67,7 +37,7 @@ struct tegra_pingroup_desc {
 #define PINO(pg_name, vdd, f0, f1, f2, f3) \
 	PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
 
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+static const struct tegra_pingroup_desc tegra30_pingroups[PINGRP_COUNT] = {
 	/*	NAME	  VDD	   f0		f1	   f2	    f3  */
 	PINI(ULPI_DATA0,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
 	PINI(ULPI_DATA1,  BB,	   SPI3,	HSI,	   UARTA,   ULPI),
@@ -319,368 +289,4 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
 	PINI(PEX_L2_CLKREQ_N,	PEXCTL,   PCIE,	HDA,	   RSVD3,   RSVD4),
 	PINI(HDMI_CEC,		SYS,      CEC,	RSVD2,	   RSVD3,   RSVD4),
 };
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *tri = &pmt->pmt_ctl[pin];
-	u32 reg;
-
-	/* Error check on pin */
-	assert(pmux_pingrp_isvalid(pin));
-
-	reg = readl(tri);
-	if (enable)
-		reg |= PMUX_TRISTATE_MASK;
-	else
-		reg &= ~PMUX_TRISTATE_MASK;
-	writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
-	pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
-	pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pull = &pmt->pmt_ctl[pin];
-	u32 reg;
-
-	/* Error check on pin and pupd */
-	assert(pmux_pingrp_isvalid(pin));
-	assert(pmux_pin_pupd_isvalid(pupd));
-
-	reg = readl(pull);
-	reg &= ~(0x3 << PMUX_PULL_SHIFT);
-	reg |= (pupd << PMUX_PULL_SHIFT);
-	writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *muxctl = &pmt->pmt_ctl[pin];
-	int i, mux = -1;
-	u32 reg;
-
-	/* Error check on pin and func */
-	assert(pmux_pingrp_isvalid(pin));
-	assert(pmux_func_isvalid(func));
-
-	if (func & PMUX_FUNC_RSVD1) {
-		mux = func & 0x3;
-	} else {
-		/* Search for the appropriate function */
-		for (i = 0; i < 4; i++) {
-			if (tegra_soc_pingroups[pin].funcs[i] == func) {
-				mux = i;
-				break;
-			}
-		}
-	}
-	assert(mux != -1);
-
-	reg = readl(muxctl);
-	reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
-	reg |= (mux << PMUX_MUXCTL_SHIFT);
-	writel(reg, muxctl);
-
-}
-
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pin_io = &pmt->pmt_ctl[pin];
-	u32 reg;
-
-	/* Error check on pin and io */
-	assert(pmux_pingrp_isvalid(pin));
-	assert(pmux_pin_io_isvalid(io));
-
-	reg = readl(pin_io);
-	reg &= ~(0x1 << PMUX_IO_SHIFT);
-	reg |= (io & 0x1) << PMUX_IO_SHIFT;
-	writel(reg, pin_io);
-}
-
-static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pin_lock = &pmt->pmt_ctl[pin];
-	u32 reg;
-
-	/* Error check on pin and lock */
-	assert(pmux_pingrp_isvalid(pin));
-	assert(pmux_pin_lock_isvalid(lock));
-
-	if (lock == PMUX_PIN_LOCK_DEFAULT)
-		return 0;
-
-	reg = readl(pin_lock);
-	reg &= ~(0x1 << PMUX_LOCK_SHIFT);
-	if (lock == PMUX_PIN_LOCK_ENABLE)
-		reg |= (0x1 << PMUX_LOCK_SHIFT);
-	else {
-		/* lock == DISABLE, which isn't possible */
-		printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
-			__func__, lock);
-	}
-	writel(reg, pin_lock);
-
-	return 0;
-}
-
-static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pin_od = &pmt->pmt_ctl[pin];
-	u32 reg;
-
-	/* Error check on pin and od */
-	assert(pmux_pingrp_isvalid(pin));
-	assert(pmux_pin_od_isvalid(od));
-
-	if (od == PMUX_PIN_OD_DEFAULT)
-		return 0;
-
-	reg = readl(pin_od);
-	reg &= ~(0x1 << PMUX_OD_SHIFT);
-	if (od == PMUX_PIN_OD_ENABLE)
-		reg |= (0x1 << PMUX_OD_SHIFT);
-	writel(reg, pin_od);
-
-	return 0;
-}
-
-static int pinmux_set_ioreset(enum pmux_pingrp pin,
-				enum pmux_pin_ioreset ioreset)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pin_ioreset = &pmt->pmt_ctl[pin];
-	u32 reg;
-
-	/* Error check on pin and ioreset */
-	assert(pmux_pingrp_isvalid(pin));
-	assert(pmux_pin_ioreset_isvalid(ioreset));
-
-	if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
-		return 0;
-
-	reg = readl(pin_ioreset);
-	reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
-	if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
-		reg |= (0x1 << PMUX_IO_RESET_SHIFT);
-	writel(reg, pin_ioreset);
-
-	return 0;
-}
-
-void pinmux_config_pingroup(struct pingroup_config *config)
-{
-	enum pmux_pingrp pin = config->pingroup;
-
-	pinmux_set_func(pin, config->func);
-	pinmux_set_pullupdown(pin, config->pull);
-	pinmux_set_tristate(pin, config->tristate);
-	pinmux_set_io(pin, config->io);
-	pinmux_set_lock(pin, config->lock);
-	pinmux_set_od(pin, config->od);
-	pinmux_set_ioreset(pin, config->ioreset);
-}
-
-void pinmux_config_table(struct pingroup_config *config, int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++)
-		pinmux_config_pingroup(&config[i]);
-}
-
-static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
-				int slwf)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pad_slwf = &pmt->pmt_drive[pad];
-	u32 reg;
-
-	/* Error check on pad and slwf */
-	assert(pmux_padgrp_isvalid(pad));
-	assert(pmux_pad_slw_isvalid(slwf));
-
-	/* NONE means unspecified/do not change/use POR value */
-	if (slwf == PGRP_SLWF_NONE)
-		return 0;
-
-	reg = readl(pad_slwf);
-	reg &= ~PGRP_SLWF_MASK;
-	reg |= (slwf << PGRP_SLWF_SHIFT);
-	writel(reg, pad_slwf);
-
-	return 0;
-}
-
-static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pad_slwr = &pmt->pmt_drive[pad];
-	u32 reg;
-
-	/* Error check on pad and slwr */
-	assert(pmux_padgrp_isvalid(pad));
-	assert(pmux_pad_slw_isvalid(slwr));
-
-	/* NONE means unspecified/do not change/use POR value */
-	if (slwr == PGRP_SLWR_NONE)
-		return 0;
-
-	reg = readl(pad_slwr);
-	reg &= ~PGRP_SLWR_MASK;
-	reg |= (slwr << PGRP_SLWR_SHIFT);
-	writel(reg, pad_slwr);
-
-	return 0;
-}
-
-static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pad_drvup = &pmt->pmt_drive[pad];
-	u32 reg;
-
-	/* Error check on pad and drvup */
-	assert(pmux_padgrp_isvalid(pad));
-	assert(pmux_pad_drv_isvalid(drvup));
-
-	/* NONE means unspecified/do not change/use POR value */
-	if (drvup == PGRP_DRVUP_NONE)
-		return 0;
-
-	reg = readl(pad_drvup);
-	reg &= ~PGRP_DRVUP_MASK;
-	reg |= (drvup << PGRP_DRVUP_SHIFT);
-	writel(reg, pad_drvup);
-
-	return 0;
-}
-
-static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pad_drvdn = &pmt->pmt_drive[pad];
-	u32 reg;
-
-	/* Error check on pad and drvdn */
-	assert(pmux_padgrp_isvalid(pad));
-	assert(pmux_pad_drv_isvalid(drvdn));
-
-	/* NONE means unspecified/do not change/use POR value */
-	if (drvdn == PGRP_DRVDN_NONE)
-		return 0;
-
-	reg = readl(pad_drvdn);
-	reg &= ~PGRP_DRVDN_MASK;
-	reg |= (drvdn << PGRP_DRVDN_SHIFT);
-	writel(reg, pad_drvdn);
-
-	return 0;
-}
-
-static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pad_lpmd = &pmt->pmt_drive[pad];
-	u32 reg;
-
-	/* Error check pad and lpmd value */
-	assert(pmux_padgrp_isvalid(pad));
-	assert(pmux_pad_lpmd_isvalid(lpmd));
-
-	/* NONE means unspecified/do not change/use POR value */
-	if (lpmd == PGRP_LPMD_NONE)
-		return 0;
-
-	reg = readl(pad_lpmd);
-	reg &= ~PGRP_LPMD_MASK;
-	reg |= (lpmd << PGRP_LPMD_SHIFT);
-	writel(reg, pad_lpmd);
-
-	return 0;
-}
-
-static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pad_schmt = &pmt->pmt_drive[pad];
-	u32 reg;
-
-	/* Error check pad */
-	assert(pmux_padgrp_isvalid(pad));
-
-	reg = readl(pad_schmt);
-	reg &= ~(1 << PGRP_SCHMT_SHIFT);
-	if (schmt == PGRP_SCHMT_ENABLE)
-		reg |= (0x1 << PGRP_SCHMT_SHIFT);
-	writel(reg, pad_schmt);
-
-	return 0;
-}
-static int padgrp_set_hsm(enum pdrive_pingrp pad,
-			enum pgrp_hsm hsm)
-{
-	struct pmux_tri_ctlr *pmt =
-			(struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 *pad_hsm = &pmt->pmt_drive[pad];
-	u32 reg;
-
-	/* Error check pad */
-	assert(pmux_padgrp_isvalid(pad));
-
-	reg = readl(pad_hsm);
-	reg &= ~(1 << PGRP_HSM_SHIFT);
-	if (hsm == PGRP_HSM_ENABLE)
-		reg |= (0x1 << PGRP_HSM_SHIFT);
-	writel(reg, pad_hsm);
-
-	return 0;
-}
-
-void padctrl_config_pingroup(struct padctrl_config *config)
-{
-	enum pdrive_pingrp pad = config->padgrp;
-
-	padgrp_set_drvup_slwf(pad, config->slwf);
-	padgrp_set_drvdn_slwr(pad, config->slwr);
-	padgrp_set_drvup(pad, config->drvup);
-	padgrp_set_drvdn(pad, config->drvdn);
-	padgrp_set_lpmd(pad, config->lpmd);
-	padgrp_set_schmt(pad, config->schmt);
-	padgrp_set_hsm(pad, config->hsm);
-}
-
-void padgrp_config_table(struct padctrl_config *config, int len)
-{
-	int i;
-
-	for (i = 0; i < len; i++)
-		padctrl_config_pingroup(&config[i]);
-}
+const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra30_pingroups;