Tegra20: Move some code files to common directories for upcoming Tegra30 patches.

Move files that are going to be common between T20 and T30 into 'tegra-common'
subdirs in AVP (arm720t), CPU (armv7), and shared (arch/arm/cpu/.) areas. Any
files that are left behind in '/tegra20' will be copied to '/tegra30' subdirs
and modified for that SoC. The 'common' files should need only minor changes.

Include files (arch/arm/include/asm/arch-tegra/tegra20) will be done in a
follow-on patch.

Builds fine w/MAKEALL -s tegra20. Checkpatch.pl is clean.

Signed-off-by: Tom Warren <twarren@nvidia.com>

6 files changed, 1 insertions, 467 deletions

diff --git a/arch/arm/cpu/tegra20-common/Makefile b/arch/arm/cpu/tegra20-common/Makefile
index 9e91e5c..8184e5e 100644
--- a/arch/arm/cpu/tegra20-common/Makefile
+++ b/arch/arm/cpu/tegra20-common/Makefile
@@ -31,8 +31,7 @@ CFLAGS_arch/arm/cpu/tegra20-common/warmboot_avp.o += -march=armv4t
 
 LIB	= $(obj)lib$(SOC)-common.o
 
-SOBJS += lowlevel_init.o
-COBJS-y	+= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-y	+= clock.o funcmux.o pinmux.o
 COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
 COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
diff --git a/arch/arm/cpu/tegra20-common/ap20.c b/arch/arm/cpu/tegra20-common/ap20.c
deleted file mode 100644
index c0ca6eb..0000000
--- a/arch/arm/cpu/tegra20-common/ap20.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
-* (C) Copyright 2010-2011
-* NVIDIA Corporation <www.nvidia.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
-#include <asm/io.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/fuse.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/scu.h>
-#include <asm/arch/warmboot.h>
-#include <common.h>
-
-int tegra_get_chip_type(void)
-{
-	struct apb_misc_gp_ctlr *gp;
-	struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
-	uint tegra_sku_id, rev;
-
-	/*
-	 * This is undocumented, Chip ID is bits 15:8 of the register
-	 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
-	 * Tegra30
-	 */
-	gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
-	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
-
-	tegra_sku_id = readl(&fuse->sku_info) & 0xff;
-
-	switch (rev) {
-	case CHIPID_TEGRA20:
-		switch (tegra_sku_id) {
-		case SKU_ID_T20:
-			return TEGRA_SOC_T20;
-		case SKU_ID_T25SE:
-		case SKU_ID_AP25:
-		case SKU_ID_T25:
-		case SKU_ID_AP25E:
-		case SKU_ID_T25E:
-			return TEGRA_SOC_T25;
-		}
-		break;
-	}
-	/* unknown sku id */
-	return TEGRA_SOC_UNKNOWN;
-}
-
-static void enable_scu(void)
-{
-	struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
-	u32 reg;
-
-	/* If SCU already setup/enabled, return */
-	if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
-		return;
-
-	/* Invalidate all ways for all processors */
-	writel(0xFFFF, &scu->scu_inv_all);
-
-	/* Enable SCU - bit 0 */
-	reg = readl(&scu->scu_ctrl);
-	reg |= SCU_CTRL_ENABLE;
-	writel(reg, &scu->scu_ctrl);
-}
-
-static u32 get_odmdata(void)
-{
-	/*
-	 * ODMDATA is stored in the BCT in IRAM by the BootROM.
-	 * The BCT start and size are stored in the BIT in IRAM.
-	 * Read the data @ bct_start + (bct_size - 12). This works
-	 * on T20 and T30 BCTs, which are locked down. If this changes
-	 * in new chips (T114, etc.), we can revisit this algorithm.
-	 */
-
-	u32 bct_start, odmdata;
-
-	bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
-	odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
-
-	return odmdata;
-}
-
-static void init_pmc_scratch(void)
-{
-	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 odmdata;
-	int i;
-
-	/* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
-	for (i = 0; i < 23; i++)
-		writel(0, &pmc->pmc_scratch1+i);
-
-	/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
-	odmdata = get_odmdata();
-	writel(odmdata, &pmc->pmc_scratch20);
-}
-
-void s_init(void)
-{
-	/* Init PMC scratch memory */
-	init_pmc_scratch();
-
-	enable_scu();
-
-	/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
-	asm volatile(
-		"mrc	p15, 0, r0, c1, c0, 1\n"
-		"orr	r0, r0, #0x41\n"
-		"mcr	p15, 0, r0, c1, c0, 1\n");
-
-	/* FIXME: should have ap20's L2 disabled too? */
-}
diff --git a/arch/arm/cpu/tegra20-common/board.c b/arch/arm/cpu/tegra20-common/board.c
deleted file mode 100644
index 8a8d338..0000000
--- a/arch/arm/cpu/tegra20-common/board.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/funcmux.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/warmboot.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-enum {
-	/* UARTs which we can enable */
-	UARTA	= 1 << 0,
-	UARTB	= 1 << 1,
-	UARTD	= 1 << 3,
-	UART_COUNT = 4,
-};
-
-/*
- * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
- * so we are using this value to identify memory size.
- */
-
-unsigned int query_sdram_size(void)
-{
-	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-	u32 reg;
-
-	reg = readl(&pmc->pmc_scratch20);
-	debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
-
-	/* bits 31:28 in OdmData are used for RAM size  */
-	switch ((reg) >> 28) {
-	case 1:
-		return 0x10000000;	/* 256 MB */
-	case 2:
-	default:
-		return 0x20000000;	/* 512 MB */
-	case 3:
-		return 0x40000000;	/* 1GB */
-	}
-}
-
-int dram_init(void)
-{
-	/* We do not initialise DRAM here. We just query the size */
-	gd->ram_size = query_sdram_size();
-	return 0;
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
-	printf("Board: %s\n", sysinfo.board_string);
-	return 0;
-}
-#endif	/* CONFIG_DISPLAY_BOARDINFO */
-
-static int uart_configs[] = {
-#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
-	FUNCMUX_UART1_UAA_UAB,
-#elif defined(CONFIG_TEGRA_UARTA_GPU)
-	FUNCMUX_UART1_GPU,
-#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
-	FUNCMUX_UART1_SDIO1,
-#else
-	FUNCMUX_UART1_IRRX_IRTX,
-#endif
-	FUNCMUX_UART2_IRDA,
-	-1,
-	FUNCMUX_UART4_GMC,
-	-1,
-};
-
-/**
- * Set up the specified uarts
- *
- * @param uarts_ids	Mask containing UARTs to init (UARTx)
- */
-static void setup_uarts(int uart_ids)
-{
-	static enum periph_id id_for_uart[] = {
-		PERIPH_ID_UART1,
-		PERIPH_ID_UART2,
-		PERIPH_ID_UART3,
-		PERIPH_ID_UART4,
-	};
-	size_t i;
-
-	for (i = 0; i < UART_COUNT; i++) {
-		if (uart_ids & (1 << i)) {
-			enum periph_id id = id_for_uart[i];
-
-			funcmux_select(id, uart_configs[i]);
-			clock_ll_start_uart(id);
-		}
-	}
-}
-
-void board_init_uart_f(void)
-{
-	int uart_ids = 0;	/* bit mask of which UART ids to enable */
-
-#ifdef CONFIG_TEGRA_ENABLE_UARTA
-	uart_ids |= UARTA;
-#endif
-#ifdef CONFIG_TEGRA_ENABLE_UARTB
-	uart_ids |= UARTB;
-#endif
-#ifdef CONFIG_TEGRA_ENABLE_UARTD
-	uart_ids |= UARTD;
-#endif
-	setup_uarts(uart_ids);
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
diff --git a/arch/arm/cpu/tegra20-common/lowlevel_init.S b/arch/arm/cpu/tegra20-common/lowlevel_init.S
deleted file mode 100644
index d117f23..0000000
--- a/arch/arm/cpu/tegra20-common/lowlevel_init.S
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * SoC-specific setup info
- *
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <linux/linkage.h>
-
-	.align	5
-ENTRY(reset_cpu)
-	ldr	r1, rstctl			@ get addr for global reset
-						@ reg
-	ldr	r3, [r1]
-	orr	r3, r3, #0x10
-	str	r3, [r1]			@ force reset
-	mov	r0, r0
-_loop_forever:
-	b	_loop_forever
-rstctl:
-	.word	PRM_RSTCTRL
-ENDPROC(reset_cpu)
diff --git a/arch/arm/cpu/tegra20-common/sys_info.c b/arch/arm/cpu/tegra20-common/sys_info.c
deleted file mode 100644
index 1a0bb56..0000000
--- a/arch/arm/cpu/tegra20-common/sys_info.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-/* Print CPU information */
-int print_cpuinfo(void)
-{
-	puts("TEGRA20\n");
-
-	/* TBD: Add printf of major/minor rev info, stepping, etc. */
-	return 0;
-}
-#endif	/* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/tegra20-common/timer.c b/arch/arm/cpu/tegra20-common/timer.c
deleted file mode 100644
index 562e414..0000000
--- a/arch/arm/cpu/tegra20-common/timer.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * (C) Copyright 2008
- * Texas Instruments
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Moahmmed Khasim <khasim@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/timer.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* counter runs at 1MHz */
-#define TIMER_CLK	1000000
-#define TIMER_LOAD_VAL	0xffffffff
-
-/* timer without interrupts */
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-/* delay x useconds */
-void __udelay(unsigned long usec)
-{
-	long tmo = usec * (TIMER_CLK / 1000) / 1000;
-	unsigned long now, last = timer_get_us();
-
-	while (tmo > 0) {
-		now = timer_get_us();
-		if (last > now) /* count up timer overflow */
-			tmo -= TIMER_LOAD_VAL - last + now;
-		else
-			tmo -= now - last;
-		last = now;
-	}
-}
-
-ulong get_timer_masked(void)
-{
-	ulong now;
-
-	/* current tick value */
-	now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ);
-
-	if (now >= gd->lastinc)	/* normal mode (non roll) */
-		/* move stamp forward with absolute diff ticks */
-		gd->tbl += (now - gd->lastinc);
-	else	/* we have rollover of incrementer */
-		gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
-				- gd->lastinc) + now;
-	gd->lastinc = now;
-	return gd->tbl;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
-
-unsigned long timer_get_us(void)
-{
-	struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE;
-
-	return readl(&timer_base->cntr_1us);
-}