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| author | York Sun <yorksun@freescale.com> | 2014-09-11 13:32:06 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-25 08:36:20 -0700 |
| commit | f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb (patch) | |
| tree | 0d8686b5543a221089465049b6366fc993b826a1 /arch/arm/cpu/tegra20-common | |
| parent | 8aeb893a8ed97bac679149386cec53b275be3715 (diff) | |
| download | u-boot-imx-f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb.zip u-boot-imx-f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb.tar.gz u-boot-imx-f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb.tar.bz2 | |
driver/ddr/fsl: Fix DDR4 driver
When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.
Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu/tegra20-common')
0 files changed, 0 insertions, 0 deletions