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author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-05-30 03:19:38 +0000 |
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committer | Tom Rini <trini@ti.com> | 2013-06-10 08:43:10 -0400 |
commit | 97405d843ece2a53e67b801e02ee42005d26e172 (patch) | |
tree | 13c4b866c44ebbbb7033f7490921fcb6dffa6004 /arch/arm/cpu/tegra20-common | |
parent | 7f36c88f64ee1affd4db78b2c2f4a616abceb84c (diff) | |
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ARM: DRA7xx: clocks: Update PLL values
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/cpu/tegra20-common')
0 files changed, 0 insertions, 0 deletions