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author | Lucas Stach <dev@lynxeye.de> | 2012-09-25 20:21:13 +0000 |
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committer | Tom Rini <trini@ti.com> | 2012-10-15 11:54:07 -0700 |
commit | 65530a842eeaf7ad07e0613ac6f883f2f1f1e33f (patch) | |
tree | 01e704c3bbf59d1c5f7be1ba55ae8dcf656a5128 /arch/arm/cpu/tegra20-common/warmboot_avp.c | |
parent | 3f44e44f33899821c4703c3bd5f9c117bb328e8b (diff) | |
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tegra20: add clock_set_pllout function
Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware generated output divider.
This function adds a clean way to do so.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra20-common/warmboot_avp.c')
-rw-r--r-- | arch/arm/cpu/tegra20-common/warmboot_avp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c index bc6281d..bc46606 100644 --- a/arch/arm/cpu/tegra20-common/warmboot_avp.c +++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c @@ -214,7 +214,7 @@ void wb_start(void) reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE | PLLM_OUT1_RATIO_VAL_8; - writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out); + writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]); reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 | SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 | |