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| author | Stephen Warren <swarren@nvidia.com> | 2014-03-21 12:29:01 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-04-17 08:41:06 -0700 |
| commit | d68c9429271d31aadb048b536f177cc2a9bd5c26 (patch) | |
| tree | 42e0b4a7ad3a67a70aa885b31b184a929e8e58d2 /arch/arm/cpu/tegra124-common/funcmux.c | |
| parent | 1fa3a634137c9f40b207cff1079fe0dfbd9b3378 (diff) | |
| download | u-boot-imx-d68c9429271d31aadb048b536f177cc2a9bd5c26.zip u-boot-imx-d68c9429271d31aadb048b536f177cc2a9bd5c26.tar.gz u-boot-imx-d68c9429271d31aadb048b536f177cc2a9bd5c26.tar.bz2 | |
ARM: tegra: Tegra124 pinmux cleanup
This renames all the pinmux pins, drive groups, and functions so they
have a prefix which matches the type name. These lists are also auto-
generated using scripts that were also used to generate the kernel
pinctrl drivers. This ensures that the lists are consistent between the
two.
The entries in tegra124_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
There are differences in the set of drive groups. I have validated this
against the TRM. There are differences order of pin definitions in
pinmux.c; these previously had significant mismatches with the correct
order:-( I adjusted a few entries in pinmux-config-venice2.h since the
set of legal functions for some pins was updated to match the TRM.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra124-common/funcmux.c')
| -rw-r--r-- | arch/arm/cpu/tegra124-common/funcmux.c | 38 |
1 files changed, 20 insertions, 18 deletions
diff --git a/arch/arm/cpu/tegra124-common/funcmux.c b/arch/arm/cpu/tegra124-common/funcmux.c index d19fda0..cced787 100644 --- a/arch/arm/cpu/tegra124-common/funcmux.c +++ b/arch/arm/cpu/tegra124-common/funcmux.c @@ -20,20 +20,20 @@ int funcmux_select(enum periph_id id, int config) case PERIPH_ID_UART4: switch (config) { case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */ - pinmux_set_func(PINGRP_GPIO_PJ7, PMUX_FUNC_UARTD); - pinmux_set_func(PINGRP_GPIO_PB0, PMUX_FUNC_UARTD); - pinmux_set_func(PINGRP_GPIO_PB1, PMUX_FUNC_UARTD); - pinmux_set_func(PINGRP_GPIO_PK7, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD); + pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD); - pinmux_set_io(PINGRP_GPIO_PJ7, PMUX_PIN_OUTPUT); - pinmux_set_io(PINGRP_GPIO_PB0, PMUX_PIN_INPUT); - pinmux_set_io(PINGRP_GPIO_PB1, PMUX_PIN_INPUT); - pinmux_set_io(PINGRP_GPIO_PK7, PMUX_PIN_OUTPUT); + pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT); + pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT); - pinmux_tristate_disable(PINGRP_GPIO_PJ7); - pinmux_tristate_disable(PINGRP_GPIO_PB0); - pinmux_tristate_disable(PINGRP_GPIO_PB1); - pinmux_tristate_disable(PINGRP_GPIO_PK7); + pinmux_tristate_disable(PMUX_PINGRP_PJ7); + pinmux_tristate_disable(PMUX_PINGRP_PB0); + pinmux_tristate_disable(PMUX_PINGRP_PB1); + pinmux_tristate_disable(PMUX_PINGRP_PK7); break; } break; @@ -41,14 +41,16 @@ int funcmux_select(enum periph_id id, int config) case PERIPH_ID_UART1: switch (config) { case FUNCMUX_UART1_KBC: - pinmux_set_func(PINGRP_KB_ROW9, PMUX_FUNC_UARTA); - pinmux_set_func(PINGRP_KB_ROW10, PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1, + PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2, + PMUX_FUNC_UARTA); - pinmux_set_io(PINGRP_KB_ROW9, PMUX_PIN_OUTPUT); - pinmux_set_io(PINGRP_KB_ROW10, PMUX_PIN_INPUT); + pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT); + pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT); - pinmux_tristate_disable(PINGRP_KB_ROW9); - pinmux_tristate_disable(PINGRP_KB_ROW10); + pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1); + pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2); break; } break; |