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| author | Tom Warren <twarren@nvidia.com> | 2013-04-01 15:48:54 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-04-15 11:01:38 -0700 |
| commit | b40f734af9fdc47a0993f1f94f32d40a86f30587 (patch) | |
| tree | 21ba340509d52b689be86e0b6dd48ad7e75978b0 /arch/arm/cpu/tegra114-common | |
| parent | d0edce4fa394325a0ccfd38a5d668fb5ee1af34d (diff) | |
| download | u-boot-imx-b40f734af9fdc47a0993f1f94f32d40a86f30587.zip u-boot-imx-b40f734af9fdc47a0993f1f94f32d40a86f30587.tar.gz u-boot-imx-b40f734af9fdc47a0993f1f94f32d40a86f30587.tar.bz2 | |
Tegra114: Initialize System Counter (TSC) with osc frequency
T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra114-common')
| -rw-r--r-- | arch/arm/cpu/tegra114-common/clock.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c index 9b29ce1..5c4305a 100644 --- a/arch/arm/cpu/tegra114-common/clock.c +++ b/arch/arm/cpu/tegra114-common/clock.c @@ -19,6 +19,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/timer.h> @@ -653,3 +654,24 @@ void clock_early_init(void) writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); udelay(2); } + +void arch_timer_init(void) +{ + struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE; + u32 freq, val; + + freq = clock_get_rate(CLOCK_ID_OSC); + debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq); + + /* ARM CNTFRQ */ + asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq)); + + /* Only T114 has the System Counter regs */ + debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq); + writel(freq, &sysctr->cntfid0); + + val = readl(&sysctr->cntcr); + val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG; + writel(val, &sysctr->cntcr); + debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); +} |