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| author | Tom Warren <twarren@nvidia.com> | 2013-04-01 15:48:54 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-04-15 11:01:38 -0700 |
| commit | b40f734af9fdc47a0993f1f94f32d40a86f30587 (patch) | |
| tree | 21ba340509d52b689be86e0b6dd48ad7e75978b0 /arch/arm/cpu/tegra-common | |
| parent | d0edce4fa394325a0ccfd38a5d668fb5ee1af34d (diff) | |
| download | u-boot-imx-b40f734af9fdc47a0993f1f94f32d40a86f30587.zip u-boot-imx-b40f734af9fdc47a0993f1f94f32d40a86f30587.tar.gz u-boot-imx-b40f734af9fdc47a0993f1f94f32d40a86f30587.tar.bz2 | |
Tegra114: Initialize System Counter (TSC) with osc frequency
T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra-common')
| -rw-r--r-- | arch/arm/cpu/tegra-common/clock.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 49a0633..9156d00 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -557,4 +557,7 @@ void clock_init(void) debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]); debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]); debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]); + + /* Do any special system timer/TSC setup */ + arch_timer_init(); } |