diff options
author | Wang Dongsheng <dongsheng.wang@nxp.com> | 2016-01-18 11:02:40 +0800 |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2016-01-31 16:32:56 +0100 |
commit | c5e954eccd473c1601d60d144bc18f90893cb3ac (patch) | |
tree | 2648911c249c2837d2517dac87b7f5ccc56e518d /arch/arm/cpu/armv8 | |
parent | 11aa6a32eb5f38dd670342072b9e885269013d62 (diff) | |
download | u-boot-imx-c5e954eccd473c1601d60d144bc18f90893cb3ac.zip u-boot-imx-c5e954eccd473c1601d60d144bc18f90893cb3ac.tar.gz u-boot-imx-c5e954eccd473c1601d60d144bc18f90893cb3ac.tar.bz2 |
ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't defined
"DISCARD" will remove ._secure.text relocate, but PSCI framework
has already used some absolute address those need to relocate.
Use readelf -t -r u-boot show us:
.__secure_start addr: 601408e4
.__secure_end addr: 60141460
60141140 00000017 R_ARM_RELATIVE
46 _secure_monitor:
47 #ifdef CONFIG_ARMV7_PSCI
48 ldr r5, =_psci_vectors
60141194 00000017 R_ARM_RELATIVE
6014119c 00000017 R_ARM_RELATIVE
601411a4 00000017 R_ARM_RELATIVE
601411ac 00000017 R_ARM_RELATIVE
64 _psci_table:
66 .word psci_cpu_suspend
...
72 .word psci_migrate
60141344 00000017 R_ARM_RELATIVE
6014145c 00000017 R_ARM_RELATIVE
202 ldr r5, =psci_text_end
Solutions:
1. Change absolute address to RelAdr.
Based on LDR (immediate, ARM), we only have 4K offset to jump.
Now PSCI code size is close to 4K size that is LDR limit jump size,
so even if the LDR is based on the current instruction address,
there is also have a risk for RelAdr. If we use two jump steps I
think we can fix this issue, but looks too hack, so give up this way.
2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined.
If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure
will in the BASE address that is absolute.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv8')
0 files changed, 0 insertions, 0 deletions