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| author | York Sun <yorksun@freescale.com> | 2015-01-06 13:11:22 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-02-24 13:08:22 -0800 |
| commit | 6c747f4ad4eef87152f8d6de2169efe0a6a7a57f (patch) | |
| tree | 646fad6db1a85fb8aa6bb91d94cc7f1d9fd5b4c4 /arch/arm/cpu/armv8 | |
| parent | 9c66ce662c076fc1f5e57c4e72126e41d56d0b80 (diff) | |
| download | u-boot-imx-6c747f4ad4eef87152f8d6de2169efe0a6a7a57f.zip u-boot-imx-6c747f4ad4eef87152f8d6de2169efe0a6a7a57f.tar.gz u-boot-imx-6c747f4ad4eef87152f8d6de2169efe0a6a7a57f.tar.bz2 | |
armv8/fsl-lsch3: Change normal memory shareability
According to hardware implementation, a single outer shareable global
coherence group is defined. Inner shareable has not bee enabled.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv8')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 47b947f..ada1690 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -150,7 +150,7 @@ static inline void final_mmu_setup(void) * set level 2 table 0 to cache-inhibit, covering 0 to 1GB */ section_l1t0 = 0; - section_l1t1 = BLOCK_SIZE_L0; + section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE; section_l2 = 0; for (i = 0; i < 512; i++) { set_pgtable_section(level1_table_0, i, section_l1t0, @@ -168,10 +168,10 @@ static inline void final_mmu_setup(void) (u64)level2_table_0 | PMD_TYPE_TABLE; level1_table_0[2] = 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_NORMAL); + PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); level1_table_0[3] = 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_NORMAL); + PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); /* Rewrite table to enable cache */ set_pgtable_section(level2_table_0, |