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| author | York Sun <yorksun@freescale.com> | 2014-02-26 13:26:04 -0800 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-04-07 17:43:41 +0200 |
| commit | 1e6ad55c058200010bb0649524a2c874e7049242 (patch) | |
| tree | ce208690a42037bb29a34a24ea512b8d0edd0835 /arch/arm/cpu/armv8/start.S | |
| parent | 83571bcab10bc8d6d73dc77b64442dbd281afc99 (diff) | |
| download | u-boot-imx-1e6ad55c058200010bb0649524a2c874e7049242.zip u-boot-imx-1e6ad55c058200010bb0649524a2c874e7049242.tar.gz u-boot-imx-1e6ad55c058200010bb0649524a2c874e7049242.tar.bz2 | |
armv8/cache: Change cache invalidate and flush function
When SoC first boots up, we should invalidate the cache but not flush it.
We can use the same function for invalid and flush mostly, with a wrapper.
Invalidating large cache can ben slow on emulator, so we postpone doing
so until I-cache is enabled, and before enabling D-cache.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
Diffstat (limited to 'arch/arm/cpu/armv8/start.S')
| -rw-r--r-- | arch/arm/cpu/armv8/start.S | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index e70c51d..4f95289 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -64,10 +64,12 @@ reset: msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: - /* Cache/BPB/TLB Invalidate */ - bl __asm_flush_dcache_all /* dCache clean&invalidate */ - bl __asm_invalidate_icache_all /* iCache invalidate */ - bl __asm_invalidate_tlb_all /* invalidate TLBs */ + /* + * Cache/BPB/TLB Invalidate + * i-cache is invalidated before enabled in icache_enable() + * tlb is invalidated before mmu is enabled in dcache_enable() + * d-cache is invalidated before enabled in dcache_enable() + */ /* Processor specific initialization */ bl lowlevel_init |