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| author | York Sun <york.sun@nxp.com> | 2016-07-22 10:52:23 -0700 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-07-26 09:03:06 -0700 |
| commit | ed7a3943d580f4cf72e5ef8a20c43fa93e889d14 (patch) | |
| tree | 1146e48cc144ea82f104ca393b6598a8ea79e253 /arch/arm/cpu/armv8/fsl-layerscape | |
| parent | 3288628a8d23681c865e91e65a341d48eb5fed73 (diff) | |
| download | u-boot-imx-ed7a3943d580f4cf72e5ef8a20c43fa93e889d14.zip u-boot-imx-ed7a3943d580f4cf72e5ef8a20c43fa93e889d14.tar.gz u-boot-imx-ed7a3943d580f4cf72e5ef8a20c43fa93e889d14.tar.bz2 | |
armv8: fsl-layerscape: mmu: Fix enabling MMU
MMU bit in SCTLR needs to be set explicitly after tables are
created. It isn't an issue for EL3 becuase this bit is already
set by early MMU setup. But for other exception levels this
bit was not set.
Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index eaff166..e12b773 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -145,11 +145,14 @@ static inline void final_mmu_setup(void) set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), MEMORY_ATTRIBUTES); /* - * MMU is already enabled, just need to invalidate TLB to load the + * EL3 MMU is already enabled, just need to invalidate TLB to load the * new table. The new table is compatible with the current table, if * MMU somehow walks through the new table before invalidation TLB, * it still works. So we don't need to turn off MMU here. + * When EL2 MMU table is created by calling this function, MMU needs + * to be enabled. */ + set_sctlr(get_sctlr() | CR_M); } u64 get_page_table_size(void) |