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authorMans Rullgard <mans@mansr.com>2010-04-14 16:10:28 +0100
committerSandeep Paulraj <s-paulraj@ti.com>2010-09-08 14:51:13 -0400
commit0c0a0e07811965188d5f64cdbc186331c0598fa6 (patch)
tree29295b0d3ea9d85cccfd7afeccebc35e4564b1b1 /arch/arm/cpu/armv7
parent096ca838b514be0a20e62500413e42f0a2bb7481 (diff)
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ARMV7: OMAP3: Apply Cortex-A8 errata workarounds only on affected revisions
The workarounds for errata 621766 and 725233 should only be applied on affected Cortex-A8 revisions. Recent chips use r3px cores where these have been fixed. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
-rw-r--r--arch/arm/cpu/armv7/omap3/cache.S13
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S
index 5a19051..24e950f 100644
--- a/arch/arm/cpu/armv7/omap3/cache.S
+++ b/arch/arm/cpu/armv7/omap3/cache.S
@@ -163,15 +163,22 @@ l2_cache_disable:
* general use.
*****************************************************************************/
setup_auxcr:
+ mrc p15, 0, r0, c0, c0, 0 @ read main ID register
+ and r2, r0, #0x00f00000 @ variant
+ and r3, r0, #0x0000000f @ revision
+ orr r1, r3, r2, lsr #20-4 @ combine variant and revision
mov r12, #0x3
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #0x10 @ Enable ASA
- orr r0, r0, #1 << 5 @ Enable L1NEON
+ @ Enable L1NEON on pre-r2p1 (erratum 621766 workaround)
+ cmp r1, #0x21
+ orrlt r0, r0, #1 << 5
.word 0xE1600070 @ SMC
mov r12, #0x2
mrc p15, 1, r0, c9, c0, 2
- @ Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround)
- orr r0, r0, #1 << 27
+ @ Set PLD_FWD bit in L2AUXCR on pre-r2p1 (erratum 725233 workaround)
+ cmp r1, #0x21
+ orrlt r0, r0, #1 << 27
.word 0xE1600070 @ SMC
bx lr